JP2001156441A - Method for repairing csp/bga - Google Patents

Method for repairing csp/bga

Info

Publication number
JP2001156441A
JP2001156441A JP33809599A JP33809599A JP2001156441A JP 2001156441 A JP2001156441 A JP 2001156441A JP 33809599 A JP33809599 A JP 33809599A JP 33809599 A JP33809599 A JP 33809599A JP 2001156441 A JP2001156441 A JP 2001156441A
Authority
JP
Japan
Prior art keywords
csp
bga
wiring board
bank
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33809599A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sehata
浩之 瀬畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Ibaraki Ltd
Original Assignee
NEC Ibaraki Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Ibaraki Ltd filed Critical NEC Ibaraki Ltd
Priority to JP33809599A priority Critical patent/JP2001156441A/en
Publication of JP2001156441A publication Critical patent/JP2001156441A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Abstract

PROBLEM TO BE SOLVED: To provide a method by which no unsoldered part is produced during remounting CSP/BGA. SOLUTION: This method includes a step (d) for supplying a highly active flux 5 to the inside of a dam block 4 and heating it with a heater 6 provided under a wiring board 1; a step (e) for removing the dam block 4, cleaning and removing the remaining flux 5, applying a low active flux to the area of the wiring board 1 where a BGA (or CSP) is remounted, and remounting a non- defective BGA (or CSP) 2b; and a step (f) for bonding the wiring board 1 and non-defective BGA (or CSP) 2b by reflow.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はCSP・BGAのリ
ペア工法、特に、電子回路装置を作製する工程で、一度
搭載された半導体装置が不良であった場合に、不良半導
体装置を半導体装置搭載用基板より取り外し、再度新た
な半導体装置を半導体装置搭載用基板に搭載するCSP
・BGAのリペア工法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of repairing a CSP / BGA, and more particularly, to a method of manufacturing an electronic circuit device, the method of mounting a defective semiconductor device when the semiconductor device once mounted is defective. CSP that removes from the substrate and mounts a new semiconductor device on the semiconductor device mounting substrate again
・ Related to BGA repair method.

【0002】[0002]

【従来の技術】この種のリペアー工法において、不良の
半導体装置(電子部品)を配線基板(半導体装置搭載用
基板)から取り外すと、配線基板上の接続部、即ちラン
ドには、例えば金属ロウからなる半田残渣が残留する。
この半田残渣の高さは不均一であるため、この状態で新
たな半導体装置を再搭載すると、接続不良を引き起こ
し、断線等の原因となる。そこで、接続不良を防止する
ために、以下に示す(1),(2)の工程を行ってい
た。
2. Description of the Related Art In this type of repair method, when a defective semiconductor device (electronic component) is removed from a wiring board (substrate for mounting a semiconductor device), a connection portion on the wiring board, that is, a land, is, for example, a metal brazing. Solder residue remains.
Since the height of the solder residue is not uniform, if a new semiconductor device is mounted again in this state, a connection failure is caused, which causes disconnection and the like. Therefore, the following steps (1) and (2) have been performed to prevent poor connection.

【0003】(1)まず、半田に濡れる金属板を半田残
渣に押し当て、この状態で金属板を加熱し、金属板側に
半田残渣を回収することにより、配線基板上の半田残渣
を完全に除去する。
(1) First, a metal plate that is wetted by solder is pressed against the solder residue, the metal plate is heated in this state, and the solder residue is collected on the metal plate side, thereby completely removing the solder residue on the wiring board. Remove.

【0004】(2)そして、再搭載では、新たな半導体
装置の半田突起電極自体が、加熱することにより溶融
し、配線基板に接続できるので、ランドにフラックスを
塗布し、酸化を防止した上で、半田突起電極を加熱・溶
融して両者の接続を行う。なお、半田突起電極の加熱・
溶融は、雰囲気炉を用いたり、或いは半田突起電極に加
熱空気を当てていた。
(2) In remounting, the solder bump electrode itself of a new semiconductor device is melted by heating and can be connected to a wiring board, so that flux is applied to the land to prevent oxidation. Then, the solder bump electrodes are heated and melted to connect them. In addition, heating and
For melting, an atmosphere furnace was used, or heated air was applied to the solder bump electrodes.

【0005】ところで、半田突起電極を用いて回路基板
に電子部品をフリップチップ実装する場合、半導体装置
と配線基板の熱膨張係数に差があると、半田突起電極が
加熱・溶融されている温度と常温との温度差或いは半導
体装置の動作状態での温度と停止(保存)状態での温度
差等によって生じる半導体装置と配線基板との伸び縮み
の差、つまり熱応力に起因して、半田突起電極部分に歪
みが発生し、接続不良を誘発するおそれがある。それ
故、熱膨張係数の差に起因する歪みは、製品の信頼性を
低下させる原因となっていた。
By the way, when an electronic component is flip-chip mounted on a circuit board using a solder bump electrode, if there is a difference in the coefficient of thermal expansion between the semiconductor device and the wiring board, the temperature at which the solder bump electrode is heated and melted is reduced. Due to a difference in expansion and contraction between the semiconductor device and the wiring board caused by a temperature difference from room temperature or a temperature difference between an operating state of the semiconductor device and a temperature in a stopped (preserved) state, that is, a thermal projection stress, There is a possibility that distortion is generated in the portion and a connection failure is induced. Therefore, the distortion resulting from the difference in the coefficient of thermal expansion has reduced the reliability of the product.

【0006】しかるに、上記従来のリペアー法では、半
田残渣を完全に除去し、かつ、半田電極自体のみの半田
量による接続であったため、半田量は少ない。このた
め、接続部の高さHjを大きくすることができず、製品
の信頼性を向上することが困難であった。
However, in the above-mentioned conventional repair method, since the solder residue is completely removed and the connection is made only by the solder amount of the solder electrode itself, the solder amount is small. For this reason, the height Hj of the connection cannot be increased, and it has been difficult to improve the reliability of the product.

【0007】従来のCSP・BGAのリペア工法につい
て図面を参照して詳細に説明する。
A conventional CSP / BGA repair method will be described in detail with reference to the drawings.

【0008】図2は第1の従来例を示す流れ図である。
(例えば、特開平10−163624号公報参照)図2
に示すリペア工法は、まず、ステップS101で、配線
基板上の半導体装置が不良であることを確認すると、ス
テップS102で不良半導体装置をランプで加熱し、半
田突起電極を熔融させて配線基板から半導体装置を取り
外す。
FIG. 2 is a flowchart showing a first conventional example.
(See, for example, JP-A-10-163624)
First, in step S101, when it is confirmed that the semiconductor device on the wiring board is defective, in step S102, the defective semiconductor device is heated with a lamp to melt the solder bump electrodes, thereby removing the semiconductor from the wiring board. Remove the device.

【0009】次に、ステップS103で、不良半導体装
置を取り外した後に、配線基板上に残留する半田残渣
を、均一量だけ残すようにし、余分な半田は除去する。
Next, in step S103, after removing the defective semiconductor device, a uniform amount of solder residue remaining on the wiring board is left, and excess solder is removed.

【0010】次に、ステップS104で、新たな半導体
装置を用意し、この新たな半導体装置の半田突起電極の
先端部に半田ペーストを転写法で供給し、再搭載の準備
をする(ステップS105)。
Next, in step S104, a new semiconductor device is prepared, and a solder paste is supplied to the tip of the solder bump electrode of the new semiconductor device by a transfer method to prepare for remounting (step S105). .

【0011】次に、ステップS106で、半田ペースト
を転写した新たな半導体装置と、均一量の半田残渣が残
る配線基板とを位置合わせする。
Next, in step S106, a new semiconductor device to which the solder paste has been transferred is aligned with a wiring board on which a uniform amount of solder residue remains.

【0012】次に、ステップS107で、再搭載した半
導体装置をランプの光で加熱し、半田突起電極と半田ペ
ーストを熔融させ、両者を接続し、これでリペアー工程
を終了する(ステップS108)。
Next, in step S107, the remounted semiconductor device is heated by the light of a lamp to melt the solder bump electrode and the solder paste, and connect the two, thereby completing the repair process (step S108).

【0013】ここで、ランプとしては、以下に示す理由
により、近赤外ランプ(IRランプ)が好ましい。即
ち、半導体装置では、主に回路基板の材質としてSiが
用いられており、Siは近赤外領域(波長で1μm〜5
μm)の光をよく透過する性質があり、その波長の光を
用いると、Siを透過して直接半田突起電極と半田ペー
ストを効率良く加熱できるからである。
Here, a near-infrared lamp (IR lamp) is preferable as the lamp for the following reasons. That is, in a semiconductor device, Si is mainly used as a material of a circuit board, and Si is in a near infrared region (1 μm to 5 μm in wavelength).
μm) is well transmitted, and if light of that wavelength is used, the solder bump electrode and the solder paste can be efficiently heated directly through the Si.

【0014】この技術によれば、半田残渣を半田の表面
張力に対応した均一量だけ残し、かつ、新たな半導体装
置側に半田ペーストを供給する手法をとるので、リペア
ーされた半導体装置に対しても十分な半田量を確保する
ことができる。このため、コフィン・マンソンの接続疲
労寿命式からわかるように、接続部の高さHjを高くで
き、接続部における最大歪みγmaxを少なくできるの
で、接続不良、即ち断線を発生することがない。よっ
て、半導体装置の信頼性を向上できる。
According to this technique, a solder residue is left in a uniform amount corresponding to the surface tension of the solder, and a method of supplying a solder paste to a new semiconductor device is adopted. Also, a sufficient amount of solder can be secured. For this reason, as can be seen from the Coffin-Manson connection fatigue life equation, the height Hj of the connection portion can be increased and the maximum strain γmax at the connection portion can be reduced, so that poor connection, that is, disconnection does not occur. Therefore, the reliability of the semiconductor device can be improved.

【0015】次に、再はんだ供給ができないためにリペ
アできず廃棄していた金バンプ採用のフリップチップ型
半導体装置をリペア可能とする技術について説明する。
LSIチップと配線基板との接続バンプが金の場合は、
LSIチップ除去後の基板に再はんだ供給することが難
しいことから、リペア方法が確立されていなかった。即
ち、LSIチップの除去後に、各バンプ接合部分におい
てはんだの溶融濡れ状態が相違するため、斑にはんだが
除去されるところ、配線基板の実装用パッド上にはんだ
が不均一に残り、はんだの再供給を難しくしていた。
Next, a technique for repairing a flip-chip type semiconductor device employing a gold bump which cannot be repaired because re-solder cannot be supplied and has been discarded will be described.
If the connection bump between the LSI chip and the wiring board is gold,
The repair method has not been established because it is difficult to supply the solder again to the substrate after removing the LSI chip. That is, after the removal of the LSI chip, the molten and wet state of the solder is different at each of the bump bonding portions. Therefore, when the solder is removed at the spots, the solder remains unevenly on the mounting pads of the wiring board, and the solder is re-used. Supply was difficult.

【0016】ここで、接続用バンプに金が使用されてい
るLSIチップの初期取り付けは、一般に、配線基板の
LSI実装用パッドに予めはんだを付与し、このはんだ
とLSIチップの金バンプを接続させて行う。この基板
側へのはんだ供給方法として、昭和電工(株)のスーパ
ージャフィット法や古川電工(株)のスーパーソルダー
法等があるが、いずれも部品実装前の配線基板において
LSI実装用パッドにはんだを供給する方法ゆえ、LS
Iチップを取り替える場合の再はんだ供給には不向きで
ある。
Here, in the initial mounting of an LSI chip in which gold is used for the connection bump, generally, solder is previously applied to the LSI mounting pad of the wiring board, and the solder is connected to the gold bump of the LSI chip. Do it. As a method of supplying the solder to the board side, there are a Super Jafit method of Showa Denko KK and a super solder method of Furukawa Denko KK. LS
It is not suitable for re-solder supply when replacing an I chip.

【0017】図3(a)〜(f)は第2の従来例を示す
工程順に示す側面図である。(例えば、特開平10−0
22340号公報参照)。
FIGS. 3A to 3F are side views showing a second conventional example in the order of steps. (For example, Japanese Patent Application Laid-Open No. 10-0
No. 22340).

【0018】LSIチップは、配線基板205に取り付
けた後、図3(b)に示すように封止樹脂206で完全
に接着するが、その前に、電気的な動作チェックを行
い、LSIの良否を判断するのが通例である。今、この
判断の結果図3(a)のLSIチップ202が不良であ
ったとする。
After the LSI chip is mounted on the wiring board 205, it is completely adhered with a sealing resin 206 as shown in FIG. 3B. Before that, an electrical operation check is performed to determine whether the LSI is good or bad. Is usually determined. Now, it is assumed that as a result of this determination, the LSI chip 202 in FIG. 3A is defective.

【0019】まず、不良LSIチップ202の除去方法
について説明する。図3(a)の如く、LSI吸着加熱
手段201を不良LSIチップ202に吸着させた後、
不良LSIチップ202を加熱してはんだを溶融させ、
不良LSI202を配線基板205上から引き剥す。L
SI吸着加熱手段201は、加熱加圧機構を有すると共
にLSIチップの吸引機構を備えたものである。このと
き、不良LSI202と配線基板205との接合部分2
04に窒素ガスを吹き付けながら不良LSIチップ20
2を配線基板より引き剥す。不良LSIチップ202の
除去は、当該不良LSIチップ202を吸引保持したL
SI吸着加熱手段201を操作して行う。
First, a method of removing the defective LSI chip 202 will be described. As shown in FIG. 3A, after the LSI adsorption and heating means 201 is adsorbed on the defective LSI chip 202,
Heating the defective LSI chip 202 to melt the solder,
The defective LSI 202 is peeled off from the wiring substrate 205. L
The SI adsorption heating means 201 has a heating and pressurizing mechanism and an LSI chip suction mechanism. At this time, the bonding portion 2 between the defective LSI 202 and the wiring board 205
04 defective nitrogen chip 20 while blowing nitrogen gas
2 is peeled off from the wiring board. The defective LSI chip 202 is removed by sucking and holding the defective LSI chip 202.
This is performed by operating the SI adsorption heating means 201.

【0020】これによると、LSIチップ202を除去
した後、LSI実装用パッド211に残存するはんだの
ばらつきが抑制され、チップ再取付のためにLSI実装
用パッド211の表面を平滑化する工程を省略すること
ができ、リペア工程を簡略化することができる。
According to this, after the LSI chip 202 is removed, the variation of the solder remaining on the LSI mounting pad 211 is suppressed, and the step of smoothing the surface of the LSI mounting pad 211 for reattaching the chip is omitted. And the repair process can be simplified.

【0021】封止樹脂206には、エポキシ封止樹脂を
用いる。LSI吸着加熱手段201による不良LSIチ
ップ202の加熱は、250〜300〔℃〕であり、窒
素ガスは、酸素濃度が500ppm以下の条件で吹き付
ける。
As the sealing resin 206, an epoxy sealing resin is used. Heating of the defective LSI chip 202 by the LSI adsorption and heating means 201 is 250 to 300 [° C.], and nitrogen gas is blown under the condition that the oxygen concentration is 500 ppm or less.

【0022】次に、代替LSIチップの取付方法を説明
する。図3(b)は、不良LSIチップ202を除去し
た後の状態を示す。配線基板205上には、一組のLS
I実装用パッド211が残されている。この状態におい
て、まず、LSI実装用パッド211にフラックス21
3を層状に塗布する。続いて、ダイス207の面上に展
開した層状のはんだフィルム208を当該ダイス207
と共に実装用パッド211の上方に位置づけ、ポンチ2
09を用いてはんだフィルム208を打ち抜く。これに
より、打ち抜いた層状のはんだディスク210をLSI
実装用パッド211の上層に付与する(以下、このはん
だ供給方法をマイクロプレス法という)。はんだディス
ク210は、LSI実装用パッド211に予め塗布した
フラックス213により当該LSI実装用パッド211
に接着させる(図3(d))。
Next, a method of mounting the alternative LSI chip will be described. FIG. 3B shows a state after the defective LSI chip 202 is removed. On the wiring board 205, a set of LS
The pad 211 for I mounting is left. In this state, first, the flux 21 is applied to the LSI mounting pad 211.
3 is applied in layers. Subsequently, the layered solder film 208 spread on the surface of the die 207 is
With the punch 2
09 is used to punch out the solder film 208. As a result, the punched layered solder disk 210 is
The solder is supplied to the upper layer of the mounting pad 211 (hereinafter, this solder supply method is referred to as a micro press method). The solder disk 210 is bonded to the LSI mounting pad 211 by a flux 213 applied to the LSI mounting pad 211 in advance.
(FIG. 3D).

【0023】続いて、図3(e)の如く、新しい代替L
SIチップ212をLSI吸着加熱手段201に吸着さ
せ、LSI実装用パット211の上方にて位置合わせを
行う。そして、LSI吸着加熱手段201を所定温度に
加熱して新しいLSIチップ212を昇温させた後、配
線基板205に加圧してはんだディスク210を溶融さ
せる。これにより、新しいLSIチップ212とLSI
実装用パッド211とを接合する。その後、図3(f)
の如く封止樹脂206で接着固定する。
Subsequently, as shown in FIG.
The SI chip 212 is adsorbed by the LSI adsorption / heating means 201, and alignment is performed above the LSI mounting pad 211. Then, after heating the LSI adsorption and heating means 201 to a predetermined temperature to raise the temperature of the new LSI chip 212, the wiring board 205 is pressed to melt the solder disk 210. As a result, the new LSI chip 212 and LSI
The mounting pad 211 is bonded. Then, FIG.
As shown in FIG.

【0024】これによると、チップ再取付位置の周囲に
既に実装された部品があるときでも、LSI実装用パッ
ド211に対応した所望の位置にはんだディスク210
を供給することができ、リペア作業の容易化を図ること
ができる。
According to this, even when there are already mounted components around the chip re-attachment position, the solder disk 210 is placed at a desired position corresponding to the LSI mounting pad 211.
And repair work can be facilitated.

【0025】フラックス213は、比較的粘着性が高い
ものが望ましいことから、千住金属製デルタラックス5
27−7を用い、はんだフィルム208には50〔μ
m〕厚の錫銀はんだを用い、これを打ち抜いて直径80
〔μm〕の錫銀はんだディスク210を形成する。LS
I吸着加圧手段201の加熱は、250〜300℃とし
た。LSIチップ212は、配線基板205に0.5k
gで加圧する。このとき、LSIチップ212と配線基
板205との隙間に窒素ガスを吹き付け、酸素濃度を5
00ppm以下とする。
Since it is desirable that the flux 213 has relatively high tackiness, the Deltalux 5 made by Senju Metal Co., Ltd.
27-7, and 50 [μ]
m] using a thick tin-silver solder and punching it out to a diameter of 80
[Μm] tin-silver solder disk 210 is formed. LS
The heating of the I-adsorption pressurizing means 201 was performed at 250 to 300 ° C. The LSI chip 212 has a wiring board 205 of 0.5 k
Pressurize with g. At this time, nitrogen gas is blown into the gap between the LSI chip 212 and the wiring substrate 205 to reduce the oxygen concentration to 5%.
The content is set to 00 ppm or less.

【0026】図4(a)〜(f)は第3の従来例を示す
工程順に示す側断面図である。BGA(またはCSP)
をリペアする際は、図4(c)に示すように配線基板1
側のはんだ表面の酸化膜3を除去するために、高活性フ
ラックス4を薄く塗布してからCSP・BGA2を再搭
載し、続けて図4(d)に示すようにリフロー、洗浄し
てはんだ接続を行っていた。
FIGS. 4A to 4F are side sectional views showing a third conventional example in the order of steps. BGA (or CSP)
When repairing the wiring board 1 as shown in FIG.
In order to remove the oxide film 3 on the solder surface on the side, a highly active flux 4 is applied thinly, and the CSP / BGA 2 is mounted again. Then, as shown in FIG. Had gone.

【0027】しかしながら、リペアの回数が増えてはん
だ表面の酸化が進行すると、この工法では、はんだ表面
の酸化が十分に除去できず、結果として図4(d)に示
すような未はんだ部8となる不具合が発生していた。ま
た、この不具合を改善するため、図4(e)に示すよう
に高活性フラックス5の塗布量を多くすると、酸化膜は
除去され未はんだ部8はなくなるが、その反面、図4
(f)に示すようにリフロー後の洗浄で高活性フラック
ス残り9が発生し信頼性上問題となっていた。この高活
性フラックス残り9は、高集積化にともなう多ピン・狭
ピッチ化により顕著に発生していた。
However, when the number of repairs increases and the oxidation of the solder surface progresses, this method cannot sufficiently remove the oxidation of the solder surface, and as a result, the unsoldered portion 8 as shown in FIG. Problem had occurred. When the amount of the high-active flux 5 applied is increased as shown in FIG. 4 (e) in order to improve this problem, the oxide film is removed and the unsoldered portion 8 disappears.
As shown in (f), the washing after the reflow resulted in a high active flux residue 9, which was a problem in reliability. The high active flux residue 9 was remarkably generated due to the increase in the number of pins and the narrow pitch accompanying the high integration.

【0028】[0028]

【発明が解決しようとする課題】上述した従来のCSP
・BGAのリペア工法は、リペアの回数が増えてはんだ
表面の酸化が進行すると、はんだ表面の酸化が十分に除
去できないので、CSP・BGAの再搭載の際に未はん
だ部が発生するという欠点があった。
SUMMARY OF THE INVENTION The above-mentioned conventional CSP
-The BGA repair method has the disadvantage that when the number of repairs increases and the oxidation of the solder surface progresses, the oxidation of the solder surface cannot be sufficiently removed, so that when the CSP / BGA is remounted, unsoldered portions are generated. there were.

【0029】[0029]

【課題を解決するための手段】第1の発明のCSP・B
GAのリペア工法は、不良のBGA(またはCSP)を
配線基板から取り外す工程と、BGA(またはCSP)
を再搭載する配線基板の領域の周辺に土手を形成する工
程と、土手の内側に高活性フラックスを供給し、これを
配線基板の下部に設置した加熱器により加熱する工程
と、土手を撤去し、残存する高活性フラックスを洗浄・
除去し、BGA(またはCSP)を再搭載する配線基板
の領域に低活性フラックスを塗布し、良品のBGA(ま
たはCSP)を再搭載する工程と、リフローして配線基
板と良品のBGA(またはCSP)を接合する工程とを
含んで構成される。
Means for Solving the Problems CSP · B of the first invention
The GA repair method includes a step of removing a defective BGA (or CSP) from a wiring board, and a step of removing the BGA (or CSP).
The step of forming a bank around the area of the wiring board for reloading, the step of supplying a highly active flux to the inside of the bank and heating it with a heater installed at the bottom of the wiring board, and the step of removing the bank , Cleaning residual high activity flux
Removing, applying a low-activity flux to the area of the wiring board on which the BGA (or CSP) is to be remounted, and reloading a good BGA (or CSP); and reflowing the wiring board and the good BGA (or CSP). ) Is joined.

【0030】第2の発明のCSP・BGAのリペア工法
は、第1の発明において、前記土手の形状が矩形であ
る。
In a CSP / BGA repair method according to a second aspect, in the first aspect, the shape of the bank is rectangular.

【0031】第3の発明のCSP・BGAのリペア工法
は、第1の発明において、前記土手の形状が多角形であ
る。
According to a third aspect of the invention, in the CSP / BGA repair method according to the first aspect, the bank has a polygonal shape.

【0032】第4の発明のCSP・BGAのリペア工法
は、第1の発明において、前記土手の形状が円形であ
る。
In a CSP / BGA repair method according to a fourth aspect, in the first aspect, the shape of the bank is circular.

【0033】第5の発明のCSP・BGAのリペア工法
は、第1の発明において、前記土手の素材がエポキシ樹
脂である。
According to a CSP / BGA repair method of a fifth invention, in the first invention, the material of the bank is an epoxy resin.

【0034】第6の発明のCSP・BGAのリペア工法
は、第1の発明において、前記土手の高さが配線基板1
のランドに付着させた半田(バンプ)の高さを越えてい
る。
According to a sixth aspect of the present invention, there is provided the CSP / BGA repair method according to the first aspect, wherein
Exceeds the height of the solder (bump) attached to the land.

【0035】第7の発明のCSP・BGAのリペア工法
は、第1の発明において、前記土手の主材が射出成形さ
れた合成樹脂枠である。
The repair method for CSP / BGA of the seventh invention is the synthetic resin frame in which the main material of the bank is injection-molded in the first invention.

【0036】第8の発明のCSP・BGAのリペア工法
は、第1の発明において、前記土手を筆あるいはシリン
ジによりエポキシ樹脂を前記配線基板に塗布して形成す
る。
In a CSP / BGA repair method according to an eighth aspect, in the first aspect, the bank is formed by applying an epoxy resin to the wiring board with a brush or a syringe.

【0037】第9の発明のCSP・BGAのリペア工法
は、第1の発明において、前記土手を撤去し、残存する
前記高活性フラックスを洗浄・除去するのにメチルエチ
ルケトン等の有機溶剤を用いる。
In a CSP / BGA repair method according to a ninth aspect, in the first aspect, the bank is removed, and an organic solvent such as methyl ethyl ketone is used to wash and remove the remaining high-activity flux.

【0038】[0038]

【発明の実施の形態】次に、本発明について図面を参照
して詳細に説明する。
Next, the present invention will be described in detail with reference to the drawings.

【0039】図1(a)〜(f)は本発明の一実施形態
を工程順に示す側断面図である。図1(a)〜(f)に
示すCSP・BGAのリペア工法は、不良のBGA(ま
たはCSP)2aを配線基板1から取り外す工程(図1
(b))と、BGA(またはCSP)を再搭載する配線
基板1の領域の周辺に土手4を形成する工程(図1
(c))と、土手4の内側に高活性フラックス5を供給
し、これを配線基板1の下部に設置した加熱器6により
加熱する工程(図1(d))と、土手4を撤去し、残存
する高活性フラックス5を洗浄・除去し、BGA(また
はCSP)を再搭載する配線基板1の領域に低活性フラ
ックス7を塗布し、良品のBGA(またはCSP)2b
を再搭載する工程(図1(e))と、リフローして配線
基板1と良品のBGA(またはCSP)2bとを接合す
る工程(図1(f))と、を含んで構成される。
1A to 1F are side sectional views showing an embodiment of the present invention in the order of steps. The CSP / BGA repair method shown in FIGS. 1A to 1F is a step of removing a defective BGA (or CSP) 2 a from the wiring board 1 (FIG. 1).
(B)) and a step of forming a bank 4 around the area of the wiring board 1 on which the BGA (or CSP) is to be remounted (FIG. 1)
(C)), a step of supplying the highly active flux 5 to the inside of the bank 4 and heating the flux by a heater 6 installed at the lower part of the wiring board 1 (FIG. 1D), and removing the bank 4 Then, the remaining high-activity flux 5 is washed and removed, and the low-activity flux 7 is applied to the region of the wiring board 1 on which the BGA (or CSP) is to be mounted again, and a good BGA (or CSP) 2b
(FIG. 1 (e)), and a step (FIG. 1 (f)) of reflowing and joining the wiring board 1 and a non-defective BGA (or CSP) 2b.

【0040】土手4の形状は、矩形,多角形あるいは円
形であり、その素材は例えばエポキシ等であり、その高
さは配線基板1のランドに付着させた半田(バンプ)の
高さを越えていれば良い。
The shape of the bank 4 is rectangular, polygonal or circular, and its material is, for example, epoxy or the like, and its height exceeds the height of the solder (bump) attached to the land of the wiring board 1. Just do it.

【0041】土手4を形成させるには、矩形,多角形あ
るいは円形の合成樹脂枠を配線基板1に接着させるか、
または、筆あるいはシリンジによりエポキシ樹脂を配線
基板1に塗布してもよい。
To form the bank 4, a rectangular, polygonal or circular synthetic resin frame is adhered to the wiring board 1,
Alternatively, an epoxy resin may be applied to the wiring board 1 with a brush or a syringe.

【0042】土手4を撤去し、残存する高活性フラック
ス5を洗浄・除去するにはメチルエチルケトン等の有機
溶剤を用いればよい。
The bank 4 is removed, and the remaining high-activity flux 5 is washed and removed by using an organic solvent such as methyl ethyl ketone.

【0043】次に動作を説明する。まず図1(b)に示
すように、リペアするCSP・BGA2を取り外す。次
に図1(C)に示すように、配線基板1のはんだバンプ
エリアの外周に沿って高活性フラックス5の流れ出しを
防止するための土手4をエポキシ等で形成する。次に図
1(d)に示すように、上記(c)にて形成した土手4
の内側に配線基板1側のはんだが十分浸る量の高活性フ
ラックス5を供給し、加熱器6で加熱してはんだ表面の
酸化膜3を除去する。
Next, the operation will be described. First, as shown in FIG. 1B, the CSP / BGA 2 to be repaired is removed. Next, as shown in FIG. 1C, a bank 4 for preventing the high-active flux 5 from flowing out along the outer periphery of the solder bump area of the wiring board 1 is formed of epoxy or the like. Next, as shown in FIG. 1D, the bank 4 formed in (c) above is used.
Is supplied with a high active flux 5 in an amount sufficient to immerse the solder on the wiring board 1 side, and heated by a heater 6 to remove the oxide film 3 on the solder surface.

【0044】次に、図1(e)に示すように、メチルエ
チルケトン等の有機溶剤で高活性フラックス5、および
土手4を洗浄・除去し、低活性フラックス7を薄く塗布
してからCSP・BGA2を再搭載して、最後に図1
(f)に示すように、リフローを行ってリペア工事を完
了させる。なお最後に使用した低活性フラックス7は活
性力が低いため、リフロー後に除去しなくても信頼性上
問題はない。
Next, as shown in FIG. 1 (e), the high-activity flux 5 and the bank 4 are washed and removed with an organic solvent such as methyl ethyl ketone, and the low-activity flux 7 is applied thinly, and then the CSP / BGA 2 is removed. Reload and finally Figure 1
As shown in (f), reflow is performed to complete the repair work. Since the low activity flux 7 used last has low activity, there is no problem in reliability even if it is not removed after reflow.

【0045】[0045]

【発明の効果】本発明のCSP・BGAのリペア工法
は、高活性フラックスによる配線基板側のはんだ表面の
酸化膜除去と、高活性フラックス洗浄工程をCSP・B
GAの搭載前に実施することで、未はんだや高活性フラ
ックス残りといった不具合を防止でき、信頼性の高い高
密度実装のリペア工事ができる効果がある。
According to the CSP / BGA repair method of the present invention, the removal of the oxide film from the solder surface on the wiring board side by the high-active flux and the high-active flux cleaning step are performed by the CSP / B.
By performing the process before mounting the GA, defects such as unsoldering and high active flux remaining can be prevented, and there is an effect that a highly reliable high-density mounting repair work can be performed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)〜(f)は本発明の一実施形態を示す側
断面図である。
FIGS. 1A to 1F are side sectional views showing an embodiment of the present invention.

【図2】第1の従来例を示す流れ図である。FIG. 2 is a flowchart showing a first conventional example.

【図3】(a)〜(f)は第2の従来例を示す工程順に
示す側面図である。
FIGS. 3A to 3F are side views showing a second conventional example in the order of steps.

【図4】(a)〜(f)は第3の従来例を示す工程順に
示す側断面図である。
FIGS. 4A to 4F are side sectional views showing a third conventional example in the order of steps.

【符号の説明】[Explanation of symbols]

1 配線基板 2b BGA 3 はんだ表面の酸化膜 4 土手 5 高活性フラックス 6 加熱器 7 低活性フラックス 8 未はんだ部 9 高活性フラックス残り DESCRIPTION OF SYMBOLS 1 Wiring board 2b BGA 3 Oxide film on solder surface 4 Embankment 5 High active flux 6 Heater 7 Low active flux 8 Non-solder part 9 High active flux remaining

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】不良のBGA(またはCSP)を配線基板
から取り外す工程と、 BGA(またはCSP)を再搭載する配線基板の領域の
周辺に土手を形成する工程と、 土手の内側に高活性フラックスを供給し、これを配線基
板の下部に設置した加熱器により加熱する工程と、 土手を撤去し、残存する高活性フラックスを洗浄・除去
し、BGA(またはCSP)を再搭載する配線基板の領
域に低活性フラックスを塗布し、良品のBGA(または
CSP)を再搭載する工程と、 リフローして配線基板と良品のBGA(またはCSP)
を接合する工程とを含むことを特徴とするCSP・BG
Aのリペア工法。
1. A step of removing a defective BGA (or CSP) from a wiring board; a step of forming a bank around a region of the wiring board on which the BGA (or CSP) is to be mounted; and a high active flux inside the bank. And heating it with a heater installed at the bottom of the wiring board, removing the bank, washing and removing the remaining high-activity flux, and re-mounting the BGA (or CSP) on the wiring board. A process of applying a low-activity flux to the substrate and re-mounting a good BGA (or CSP); and reflowing the wiring board and a good BGA (or CSP).
And a step of joining the CSP and the BG
A repair method.
【請求項2】 前記土手の形状が矩形である請求項1記
載のCSP・BGAのリペア工法。
2. The CSP / BGA repair method according to claim 1, wherein the shape of the bank is rectangular.
【請求項3】 前記土手の形状が多角形である請求項1
記載のCSP・BGAのリペア工法。
3. The bank according to claim 1, wherein said bank has a polygonal shape.
CSP / BGA repair method described.
【請求項4】 前記土手の形状が円形である請求項1記
載のCSP・BGAのリペア工法。
4. The CSP / BGA repair method according to claim 1, wherein the shape of the bank is circular.
【請求項5】 前記土手の素材がエポキシ樹脂である請
求項1記載のCSP・BGAのリペア工法。
5. The CSP / BGA repair method according to claim 1, wherein the material of the bank is an epoxy resin.
【請求項6】 前記土手の高さが配線基板1のランドに
付着させた半田(バンプ)の高さを越えている請求項1
記載のCSP・BGAのリペア工法。
6. The height of the bank exceeds a height of solder (bump) attached to a land of the wiring board 1.
CSP / BGA repair method described.
【請求項7】 前記土手の主材が射出成形された合成樹
脂枠である請求項1記載のCSP・BGAのリペア工
法。
7. The CSP / BGA repair method according to claim 1, wherein the main material of the bank is an injection-molded synthetic resin frame.
【請求項8】 前記土手を筆あるいはシリンジによりエ
ポキシ樹脂を前記配線基板に塗布して形成する請求項1
記載のCSP・BGAのリペア工法。
8. The wiring board is formed by applying epoxy resin to the wiring board with a brush or a syringe.
CSP / BGA repair method described.
【請求項9】 前記土手を撤去し、残存する前記高活性
フラックスを洗浄・除去するにはメチルエチルケトン等
の有機溶剤を用いる請求項1記載のCSP・BGAのリ
ペア工法。
9. The CSP / BGA repair method according to claim 1, wherein the bank is removed and an organic solvent such as methyl ethyl ketone is used to wash and remove the remaining highly active flux.
JP33809599A 1999-11-29 1999-11-29 Method for repairing csp/bga Pending JP2001156441A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33809599A JP2001156441A (en) 1999-11-29 1999-11-29 Method for repairing csp/bga

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33809599A JP2001156441A (en) 1999-11-29 1999-11-29 Method for repairing csp/bga

Publications (1)

Publication Number Publication Date
JP2001156441A true JP2001156441A (en) 2001-06-08

Family

ID=18314869

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33809599A Pending JP2001156441A (en) 1999-11-29 1999-11-29 Method for repairing csp/bga

Country Status (1)

Country Link
JP (1) JP2001156441A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006202905A (en) * 2005-01-19 2006-08-03 Seiko Epson Corp Method of manufacturing semiconductor device and method of processing electric connection
JP2008047928A (en) * 2007-09-06 2008-02-28 Seiko Epson Corp Method of manufacturing semiconductor device and method of processing electric connection
JP2020109877A (en) * 2020-04-16 2020-07-16 日亜化学工業株式会社 Method for manufacturing light-emitting device
US10881007B2 (en) 2017-10-04 2020-12-29 International Business Machines Corporation Recondition process for BGA using flux
CN115206817A (en) * 2022-09-16 2022-10-18 江苏长电科技股份有限公司 Method for improving welding quality of flip structure

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006202905A (en) * 2005-01-19 2006-08-03 Seiko Epson Corp Method of manufacturing semiconductor device and method of processing electric connection
US7608479B2 (en) 2005-01-19 2009-10-27 Seiko Epson Corporation Method of manufacturing semiconductor device and method of treating electrical connection section
JP2008047928A (en) * 2007-09-06 2008-02-28 Seiko Epson Corp Method of manufacturing semiconductor device and method of processing electric connection
US10881007B2 (en) 2017-10-04 2020-12-29 International Business Machines Corporation Recondition process for BGA using flux
JP2020109877A (en) * 2020-04-16 2020-07-16 日亜化学工業株式会社 Method for manufacturing light-emitting device
JP7007607B2 (en) 2020-04-16 2022-01-24 日亜化学工業株式会社 Manufacturing method of light emitting device
CN115206817A (en) * 2022-09-16 2022-10-18 江苏长电科技股份有限公司 Method for improving welding quality of flip structure

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