JPH06188365A - Manufacture of integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of manufacturing processes of a stacked capacitor having fin structure, and improve manufacturing yield and reliability of an integrated circuit device. CONSTITUTION:A layer insulating film 3 covering an Si semiconductor substrate 1 and an a-C film 11 are formed in order. A laminate composed of an Si film 12 and an SiO2 film 13 is formed. The laminated is etched under the condition that the selection ratio to the a-C film is obtained. Thereby a part of a storage electrode contact-hole is formed. By etching the a-C film 11 and the layer insulating film 3, the storage electrode contact-hole is penetrated, and the Si film 12 is formed on the surface containing the storage electrode contact-hole. The Si film 12 formed on the surface containing the storage electrode contact-hole and the laminate are patterned to be a storage electrode form under the condition that the selection ratio to the a-C film 11 is obtained and the SiO2 film 13 and the a-C film 11 are eliminated. Thereby a storage electrode which has Si fins 12A, 12B, 12C stretching in a branch type from the trunk part 12CX is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
Random access memory (dynamic ran)
The present invention relates to a method suitable for manufacturing an integrated circuit device having a capacitor such as a dom access memory (DRAM).

Generally, in a DRAM, a memory cell area (a flat area per 1 bit) is small in accordance with an increase in storage capacity, and a capacity capable of accumulating charges sufficient for storage retention / reading. There is a demand for a structure of a storage electrode having a large size.

In order to reduce the memory cell area and increase the capacitance of the capacitor, it is necessary to increase the surface area of the storage electrode. Therefore, it is necessary to increase the surface area of the storage electrode. It is preferable that the stacked capacitor has a fin structure (in particular, "IEDM Tec
h. Dig. (1988), pp592) "or" I
EDM Tech. Dig. (1991), pp47
7) ”and the like) are effective.

However, since the stacked capacitor with fin structure has various difficulties in manufacturing,
We must improve these one by one.

[0005]

2. Description of the Related Art Generally, when forming a fin structure in a stacked capacitor with a fin structure, a laminated body formed by alternately laminating a required number of layers, for example, a SiO ₂ film and a polycrystalline Si film is formed on the polycrystalline Si. SiO ₂ with selectivity for
The etching process and the etching process of polycrystalline Si having selectivity to SiO ₂ are alternately used for processing.

In this processing, for example, a laminated body in which a SiO ₂ film and a polycrystalline Si film are alternately laminated is patterned into a shape of a storage electrode in a capacitor, and then Si is formed.
A process to remove the O ₂ film is needed.

At this time, in etching each film, each film must be completely etched and removed, and each film has a film thickness distribution, and
It is essential to perform so-called over-etching in order to compensate for the existence of an etching rate distribution.

When patterning the shape of the storage electrode, anisotropic etching is used in order to precisely transfer the resist pattern. However, since a residual film is likely to occur in the step portion existing on the base, This too must be removed by over-etching. From this, Si
In the etching process of the O ₂ film and the polycrystalline Si film,
Sufficient selectivity is required.

[0009]

By the way, in a memory cell having a stacked capacitor with a fin structure, in order to improve the degree of integration, the memory cell area is reduced, and accordingly, the storage electrode of the capacitor is reduced. It is also necessary to reduce the area of the plane in that area.

In such a case, in order to secure the required surface area of the storage electrode, it is necessary to deal with it by increasing the number of fins. At present, for example, in the case of 256 MDRAM, it is necessary to increase the number to five or more. It has become.

Generally, the number of steps for forming the storage electrode as described above is such that each fin requires two steps for forming an opening of an electrode contact hole and two steps for forming the shape of the storage electrode. However, in forming the opening of the electrode contact hole, since the uppermost polycrystalline Si film is grown after the opening of the electrode contact hole, the number of steps is reduced, and the lowermost SiO ₂ film is the SiO ₂ film between the fins. Since it suffices that they are removed at the same time as the removal, the etching for patterning is not necessary, and the number of steps is similarly reduced. Therefore, the number of steps for forming the storage electrode is
(Number of fins x 5-2) process.

In practice, with respect to the above-mentioned number of steps, chemical vapor deposition (Chemical Vapor Deposition) is used to form a polycrystalline Si film and a SiO ₂ film per fin.
However, the number of steps is (the number of fins × 6−2),
For example, in the case of five fins, it is difficult to manufacture inexpensively because the etching process alone requires nine steps for forming the electrode contact hole opening and nine steps for forming the shape of the storage electrode. Further, as the number of steps increases, defective parts due to particles and the like generated in each step accumulate, which causes a problem that both manufacturing yield and reliability decrease.

In response to this problem, the wafer is transferred under vacuum, and the reaction chamber for SiO ₂ etching and the polycrystalline S are successively introduced.
Although it is possible to solve the problem to some extent by using a so-called multi-chamber type manufacturing apparatus that performs processing in the i-etching reaction chamber, the manufacturing apparatus is enormous and depends on it. In this case, the manufacturing cost is still high.

The present invention can significantly reduce the number of manufacturing steps of a memory including a memory cell having a stacked capacitor with a fin structure, and as a result, improve the manufacturing yield and reliability of this type of integrated circuit device. Try to.

[0015]

According to the present invention, a polycrystalline Si film to be a finned storage electrode and a polycrystalline Si film to be a finned storage electrode are used by using an amorphous carbon film as the lowermost layer underlayer of fins in a stacked capacitor with fin structure. Basically, it is possible to etch a laminated body composed of a SiO ₂ film, which is a spacer film for generating a fin gap of a finned storage electrode, under a single condition.

Therefore, in the method of manufacturing an integrated circuit device according to the present invention, (1) an insulating film (for example, the interlayer insulating film 3) covering the surface of the substrate (for example, the substrate 1) on which the transfer transistor and the like are formed.
After forming the amorphous carbon film (for example, a-
A step of forming a C film 11), and then a step of forming a laminated body including a Si film (for example, a polycrystalline Si film 12) to be a storage electrode and a SiO ₂ film (for example, a SiO ₂ film 13) which is a spacer film. Then, the stacked body composed of the Si film and the SiO ₂ film is etched under a condition that a selection ratio with the amorphous carbon film can be obtained, to thereby form a storage electrode contact hole (for example, a storage electrode contact hole).
A step of forming a part of the hole 15), then a step of etching the amorphous carbon film and the insulating film to extend through the storage electrode contact hole to expose a part of the substrate, and A step of forming a Si film on the surface including the inside of the storage electrode contact hole, and then forming the Si film formed on the surface including the inside of the storage electrode contact hole and the laminated body into the amorphous carbon film. The SiO ₂ film and the amorphous carbon film are removed after patterning the storage electrode shape under the condition that the selection ratio can be obtained from the trunk of Si in the storage electrode contact hole (for example, trunk 12CX). A storage electrode (eg, storage electrode) having Si fins (for example, fins 12A, 12B, 12C, etc.) that spread in the shape of Includes a step of completing the 17), characterized by comprising either or

(2) In the above-mentioned (1), a step of forming a laminate of a Si film to be a storage electrode on an amorphous carbon film and a SiO ₂ film as a spacer film so as to start with the Si film. Is included, or

(3) In the above (1), a laminated body composed of a Si film to be a storage electrode on an amorphous carbon film and a SiO ₂ film which is a spacer film is formed so as to begin with the SiO ₂ film. Step, and thereafter, patterning the Si film existing on the surface including the inside of the storage electrode contact hole and the laminated body into a storage electrode shape under the condition that a selection ratio with the amorphous carbon film is obtained,
And removing the O ₂ film and the amorphous carbon film in that order.

[0019]

In the present invention, as described above, as the spacer film for forming the inter-fin gap of the storage electrode made of the Si film such as the polycrystalline Si film or the amorphous Si film in the stacked capacitor with fin structure, As in the past, a SiO ₂ film that is easy to create and handle is used, and an amorphous carbon film is formed on the base of the SiO ₂ film, and the Si film and the SiO ₂ film can be etched at substantially the same rate by selecting different conditions. Taking advantage of the fact that isotropic etching can establish an etching selection ratio between an amorphous carbon film and the conventional technology, the etching processing with conventional technology is four times the number of fins minus two. The number of steps required, for example, if the number of fins is five, eighteen steps are required, but the present invention can be basically completed in only three steps. The manufacturing yield and reliability of this kind of integrated circuit device are greatly improved.

[0020]

1 to 8 are sectional side views of an essential part of an integrated circuit device at a process step for explaining a first embodiment of the present invention. Hereinafter, with reference to these drawings, FIG. The details will be described.

1- (1) At this stage, the field insulating film 2 on the Si semiconductor substrate 1
In the active region surrounded by, a transfer transistor represented by a gate electrode acting as a word line WL and a bit line B are formed.
In a state where L is formed and the surface is covered with the interlayer insulating film 3 made of SiN having a thickness of 400 [Å],
After that, the process of forming a capacitor and the subsequent steps are started.

1- (2) By applying the sputtering method, the thickness is, for example, 5
00 [Å] amorphous carbon (a-C) film 11
To form.

1- (3) Chemical vapor deposition
position (CVD) method,
The thickness to be the fin of the storage electrode is, for example, 300 [Å]
The polycrystalline Si film 12 of is formed.

1- (4) By applying the CVD method, a SiO ₂ film 13 having a thickness of 300 [Å] to be a spacer film is formed.

1- (5) The steps 1- (3) and 1- (4) are repeated a required number of times to form a multi-layered structure including the polycrystalline Si film 12 and the SiO ₂ film 13. In the present embodiment, the number of repetitions is twice, so that the number of laminated layers of the polycrystalline Si film 12 and the SiO ₂ film 13 is two.

1- (6) A resist film 14 having a thickness of, for example, 1 [μm] having an opening 14A for forming a storage electrode contact hole is formed by applying a resist process in the lithography technique.

See FIG. 2 2- (1) Reactive ions containing CF ₄ gas as etching gas
Etching (reactive ion etch)
g: RIE) method is applied to obtain the SiO ₂ film 1
3 and the polycrystalline Si film 12 are anisotropically etched at a substantially constant rate to form a storage electrode contact hole 15.

Even if this etching is performed, a
The etching rate of the -C film 11 can be set to 1/3 or less of the etching rate of the laminated body. Even if some over-etching is performed to complete the etching of the laminated body, the aC film 11 is sufficiently left, and the protective function of the interlayer insulating film 3 and thus the Si semiconductor substrate 1 can be maintained. At this stage, the storage electrode contact hole 1
5 is not yet finished.

See FIG. 3 3- (1) By applying the RIE method using O ₂ as an etching gas, the aC film 11 is etched to extend the storage electrode contact hole 15. As a result, a part of the surface of the interlayer insulating film 3 is exposed in the storage electrode contact hole 15.

See FIG. 4. 4- (1) By applying the RIE method using a mixed gas of (CF ₄ + CHF ₃ ) as an etching gas, the SiO ₂ exposed in the storage electrode contact hole 15 The inter-layer insulating film 3 is etched to extend and penetrate the storage electrode contact hole 15. As a result, a part of the surface of the Si semiconductor substrate 1 is exposed in the storage electrode contact hole 15.

Referring to FIG. 5, 5- (1) by applying the plasma ashing method using O ₂ gas, the resist film 14 used as the etching mask in the steps described with reference to FIGS. 1 to 4 is removed. .
At this time, the a-C film 11 is laterally etched by about 500 [Å].
The generated void only has a structure in which polycrystalline Si that will be formed later enters and contacts the fin made of polycrystalline Si, and no problem occurs. If it is desired to avoid lateral etching in the aC film 11, the resist film 14 may be anisotropically ashed by applying the RIE method using O ₂ . Further, after removing only a part from the surface of the resist film 14 by ashing, concentrated sulfuric acid and hydrogen peroxide are mixed with 100:
The remaining resist film 14 may be removed with a stripping solution having a temperature of 130 [° C.] mixed at a ratio of about 1. It has been found that this stripper hardly etches aC. Therefore, by suppressing the ashing amount to be low, the etching amount in the lateral direction can be reduced.

5- (2) By applying the CVD method, the storage electrode contact
A polycrystalline Si film 12 having a thickness of, for example, 300 [Å] is formed on the entire surface including the inside of the hole 15. This uppermost polycrystalline Si
Part of the film 12 is the storage electrode contact hole 15
The storage electrode contact hole 1 has a structure that extends inside and contacts the Si semiconductor substrate 1 and has a different structure from the polycrystalline Si film 12 of the lowermost layer or the intermediate layer.
The portion extending within 5 will be specifically referred to as the trunk portion 12CX. 5- (3) The resist film 16 in the shape of the storage electrode is formed by applying a resist process in the lithography technique.

See FIG. 6 6- (1) By applying the RIE method using CF ₄ gas as an etching gas, a laminated body composed of the polycrystalline Si film 12 and the SiO ₂ film 13 is formed into a storage electrode shape. By patterning, fins 12A, 12B, and 12C having a shape extending in a dendritic form from the trunk portion 12CX are formed.

Due to the step existing on the base, for example, 12
Even when over-etching of about 00 [Å] is required, the thickness of the aC film 11 is 500 [Å] as described above.
Yes, and its etching rate is 1 compared to the laminate.
Since it can be made / 3 or less, the film loss 11A in the aC film 11 is about 400 [Å], and
Since more than 00 [Å] remains, the underlying interlayer insulating film 3 can be protected.

See FIG. 7 7- (1) O ₂ plasma or down flow of O ₂ plasma or UV
(Ultraviolet) / O ₃ based oxygen radicals are used to form the resist film 16 and a of the storage electrode pattern.
-C film 11 is removed. See FIG. 8 8- (1) By immersing in a hydrofluoric acid solution, the fin 12
The SiO ₂ film 13 existing between A and the fin 12B and between the fin 12B and the fin 12C is removed. By doing so, the storage electrode 17 having the three fins 12A to 12C for forming the stacked capacitor with the fin structure can be obtained. After this, the storage electrode 17 created above
Then, the capacitor can be completed by using a usual technique, and then the memory can be completed.

The order of the removal of the aC film and the removal of the SiO ₂ film is reversed, and first, the film is immersed in hydrofluoric acid to form Si.
The O ₂ film 13 is removed, and subsequently the resist film 16 and the aC film 11 of the storage electrode pattern are removed by using oxygen radicals by O ₂ plasma, O ₂ plasma downflow or UV / O ₃ method. May be. In this way, since the aC film 11 protects the base when immersed in hydrofluoric acid, a SiO ₂ film can be used on the surface of the interlayer insulating film. In this case, before dipping in hydrofluoric acid,
a light O ₂ plasma treatment for the aC film 11, that is,
If O ₂ plasma treatment is performed to such an extent that the protective effect can be maintained, the permeation of hydrofluoric acid between the fins will be ensured.

Although the number of fins is three in the above embodiment,
In order to show that the advantages of the present invention are remarkable, the case of five fins will be described. In the conventional technique, nine times are required to open the storage electrode contact hole.
The patterning of the storage electrode shape requires 9 times, so that a total of 18 etching processes are required. If the steps of the above-mentioned embodiment are adopted, the storage electrode contact hole is formed 3 times and the storage electrode is formed. A total of four etching processes for patterning the shape are completed.

FIG. 9 is a sectional side view of a main part of an integrated circuit device at a process step for explaining the second embodiment of the present invention, which will be described in detail below with reference to this figure. The same symbols as those used in FIGS. 1 to 8 represent the same parts or have the same meanings. The steps up to forming the resist film 14 having the storage electrode contact hole forming opening 14A for forming the storage electrode contact hole 15 are exactly the same as those in the first embodiment described with reference to FIGS. Therefore, as the second embodiment,
I will explain from the next stage.

In the first embodiment described above, the etching process was applied three times to form the storage electrode contact hole 15, but in the present embodiment, the etching process is performed.
Increasing the etch rate for a-C depending on the addition of SF ₆ in the gas CF _4, as shown, to simultaneously etched from the surface of the laminate to a-C film 11, the storage electrode contact Part of the interlayer insulating film 3 is exposed in the hole 15.

Then, an etching gas (CF ₄ + C
RIE using a mixed gas of HF ₃ ) is applied to etch the interlayer insulating film 3 made of SiO ₂ to extend and penetrate the storage electrode contact hole 15. Depending on this,
A part of the surface of the Si semiconductor substrate 1 is exposed in the storage electrode contact hole 15. Incidentally, the subsequent steps may be carried out in the same manner as in the first embodiment. Further, an etching gas obtained by adding SF ₆ to the CF ₄ and replaced with CF _4, by performing a sufficiently long over-etching, it is possible to obtain the same result.

It goes without saying that according to the second embodiment, the etching process is reduced once more as compared with the first embodiment.

FIGS. 10 to 12 are side sectional views of an essential part of the integrated circuit device in the process steps for explaining the third embodiment of the present invention. Hereinafter, with reference to these drawings, FIG. The details will be described. Note that the same symbols as those used in FIGS. 1 to 9 represent the same parts or have the same meanings, and in this embodiment, they are surrounded by the field insulating film 2 on the Si semiconductor substrate 1. A transfer transistor represented by a gate electrode acting as a word line WL and a bit line BL are formed in the active region, and an interlayer insulating film 3 made of SiO ₂ having a thickness of 400 [Å] and a thickness of 500
It is assumed that the aC film 11 of [Å] is laminated.

See FIG. 10 10- (1) By applying the CVD method, the thickness is, for example, 100.
The SiO ₂ film 18 of [Å] is formed. 10- (2) Here, as in the case of the first embodiment, a multilayer body including the polycrystalline Si film 12 and the SiO ₂ film 13 that is a spacer film is formed in multiple layers. This is exactly the same as the first embodiment described with reference to FIG.

10- (3) Taking the same steps as in the first embodiment, the storage electrode contact
Although the holes 15 are formed, what is different from the first embodiment is that the thin SiO ₂ film 18 exists under the laminated body, but this is etched at the same time as the laminated body. No problem.

11- (1) The resist film 14 used as the etching mask in the step described with reference to FIG. 10 is removed by taking the same steps as in the first embodiment. 11- (2) By taking the same steps as in the first embodiment, a polycrystalline Si film 12 having a thickness of 300 [Å] to be the fins and trunks of the uppermost layer is formed. Here again, the polycrystalline Si film in the storage electrode contact hole 15 is used as the trunk portion 12CX.

11- (3) By adopting the same steps as in the first embodiment, the resist film 16 in the shape of the storage electrode is formed. 11- (4) By applying the RIE method using CF ₄ gas as the etching gas, the laminated body composed of the polycrystalline Si film 12 and the SiO ₂ film 13 and the SiO ₂ film 18 are formed into the storage electrode shape. By patterning, fins 12A, 12B, and 12C having a shape extending in a dendritic form from the trunk portion 12CX are formed.

See FIG. 12 12- (1) The aC film 1 is obtained by immersing in a hydrofluoric acid solution.
1 between the fin 12A, between the fins 12A and 12B, between the fins 12B and 12C SiO ₂
The film 18 and the SiO ₂ film 13 are removed. Depending on this,
The SiO ₂ film 1 is provided between the aC film 11 and the fin 12A.
A gap of 100 [Å], which was 8 thick, is created.

12- (2) O ₂ plasma or UV (ultraviolet) /
The resist film 16 of the storage electrode pattern and the aC film 11 are removed by using O ₂ radicals derived from O ₃ . By doing so, the storage electrode 17 having the three fins 12A to 12C for forming the stacked capacitor with fin structure can be obtained.

12- (3) After that, the storage electrode 17 formed as described above may be used to complete a capacitor by a conventional technique, and subsequently to complete a memory.

According to the third embodiment, at the stage where the aC film 11 is removed, the aC film 11 is formed on the upper surface of the aC film 11, that is, between the fins 12A.
Since there is a gap of about 0 [Å], O ₂
The radicals satisfactorily wrap around, so the removal of the aC film 11 is quicker than in the first embodiment.

The present invention is not limited to the above embodiments,
Many modifications can be made, a few examples are given below.

When anisotropically etching a laminate of a polycrystalline Si film and a SiO ₂ film at a constant rate, a CF ₄ gas was used as an etching gas. However, if the purpose can be achieved, other etching gas may be used. , For example, NF ₃ can be used.

Good results can be obtained by using amorphous Si instead of polycrystalline Si. In any case, the doping step can be omitted by using P-containing polycrystalline Si or P-containing amorphous Si. Needless to say.

As an etching gas for selectively etching SiO ₂ , a mixed gas of (CF ₄ + CHF ₃ ) has been exemplified. In addition to this, C ₂ F ₆ and (CF ₄ + CH) may be used.
₂ F _2), it is also possible to use a gas, such as _{(C 4 F 8 + CH 2} F 2).

The RIE method has been exemplified as the etching technique, but ECR (electron cyclotron) is used.
Good results can be obtained by applying a magnetic field etching method such as resonance), and the anisotropy can be improved by cooling the substrate.

Although the sputtering method has been exemplified as the film forming technique of the aC film, it may be formed by, for example, the CVD method using hydrocarbon as a raw material gas.

For pattern formation, EB (electron)
In the case of using (beam) exposure or X-ray exposure, of course, PMMA (polym
ethylmethacrylate, PMSS (p
olymethylsilsesquioxane),
Other resists will be used, but in any case,
If desired, a thick resist mask can be used utilizing the multi-layer resist method.

The thickness and the number of fins in the storage electrode can be designed according to the requirements for the device characteristics of the integrated circuit device, and the combination of the etching conditions should be appropriately selected within the scope of the present disclosure. Is easy.

[0059]

In the method for manufacturing an integrated circuit device according to the present invention, a laminated body including a Si film and a SiO ₂ film is formed after forming an insulating film covering the surface of the substrate and then forming an amorphous carbon film. To form a part of the storage electrode contact hole by etching the laminated body under a condition that a selection ratio with the amorphous carbon film is obtained, and etching the amorphous carbon film and the insulating film to form a storage electrode contact hole. To expose a part of the substrate, and to form Si on the surface including the storage electrode contact hole.
After the film is formed, the Si film and the laminated body formed on the surface including the storage electrode contact hole are patterned into a storage electrode shape under the condition that a selection ratio is obtained with the amorphous carbon film, and then the SiO ₂ film and the amorphous The carbon film is removed to complete the storage electrode with Si fins that dendriticly extend from the Si trunk in the storage electrode contact hole.

As described above, in the present invention, the spacer film is used as the spacer film in order to generate the inter-fin gap of the storage electrode made of the Si film such as the polycrystalline Si film or the amorphous Si film in the stacked capacitor with fin structure.
As in the past, an SiO ₂ film that is easy to create and handle is used, and an amorphous carbon film is formed on the base of the SiO ₂ film, and conditions are selected so that the Si film and the SiO ₂ film can be etched at a substantially constant rate. Taking advantage of the fact that anisotropic etching can provide an etching selection ratio with an amorphous carbon film, and with conventional technology, the number of steps required for etching is four times the number of fins. For example, if the number of fins is 5, the number of steps required is 18, but the present invention can basically be completed in only 3 steps, and the manufacturing yield and reliability of this type of integrated circuit device are greatly improved.

[Brief description of drawings]

FIG. 1 is a side sectional view of an essential part of an integrated circuit device in a process key part for explaining a first embodiment of the present invention.

FIG. 2 is a side sectional view of an essential part of the integrated circuit device at a process key point for explaining the first embodiment of the present invention.

FIG. 3 is a side sectional view of a main part of an integrated circuit device in a process main part for explaining a first embodiment of the present invention.

FIG. 4 is a side sectional view of a main part of an integrated circuit device at a process main part for explaining a first embodiment of the present invention.

FIG. 5 is a cutaway side view of a main part of an integrated circuit device at a process key point for explaining a first embodiment of the present invention.

FIG. 6 is a side sectional view of a main part of an integrated circuit device at a process main part for explaining the first embodiment of the present invention.

FIG. 7 is a sectional side view of a main part of the integrated circuit device at a process key point for explaining the first embodiment of the present invention.

FIG. 8 is a side sectional view of a main part of an integrated circuit device at a process main part for explaining the first embodiment of the present invention.

FIG. 9 is a cutaway side view of a main part of an integrated circuit device at a process key point for explaining a second embodiment of the present invention.

FIG. 10 is a side sectional view of a main part of an integrated circuit device at a process main part for explaining a third embodiment of the present invention.

FIG. 11 is a side sectional view of a main part of an integrated circuit device in a process key point for explaining a third embodiment of the present invention.

FIG. 12 is a cutaway side view of an essential part of an integrated circuit device in a process key point for explaining a third embodiment of the present invention.

[Explanation of symbols]

1 Si semiconductor substrate 2 field insulating film 3 interlayer insulating film WL word line BL bit line 11 a-C film 12 polycrystalline Si film 12A fin 12B fin 12C fin 12CX trunk part 13 SiO ₂ film 14 resist film 14A opening 15 storage electrode contact・ Hole 16 Resist film 17 Storage electrode 18 SiO ₂ film

Claims (3)

[Claims] 1. A step of forming an amorphous carbon film after forming an insulating film covering a surface of a substrate in which transfer transistors and the like are formed, and then a Si film and a spacer film SiO to be a storage electrode. A step of forming a laminated body composed of _two films, and then etching the laminated body composed of the Si film and the SiO ₂ film under the condition that a selection ratio with the amorphous carbon film can be obtained to form one of the storage electrode contact holes. A step of forming a portion, and then performing a step of etching the amorphous carbon film and the insulating film to extend and penetrate the storage electrode contact hole to expose a part of the substrate. Forming a Si film on the surface including the hole, and then forming on the surface including the storage electrode contact hole The storage electrode contact the Si film and the laminates and removing the SiO ₂ film and the amorphous carbon film after patterning the storage electrode shape under the condition that the selection ratio between the amorphous carbon film can be obtained,
Si that spreads in a dendritic form from the trunk of Si in the hall
And a step of completing a storage electrode having a fin. 2. A step of forming a stack of a Si film to be a storage electrode on an amorphous carbon film and a SiO ₂ film as a spacer film so as to start with the Si film. The method for manufacturing an integrated circuit device according to claim 1. 3. A step of forming a laminated body of a Si film to be a storage electrode on an amorphous carbon film and a SiO ₂ film which is a spacer film so as to start with a SiO ₂ film, and thereafter, a storage electrode contact / The Si film existing on the surface including the inside of the hole and the laminated body are patterned into a storage electrode shape under a condition that a selection ratio with the amorphous carbon film is obtained, and then the SiO ₂ film is removed and the amorphous carbon film is removed. The method of manufacturing an integrated circuit device according to claim 1, further comprising: