JP2000036491A - Fabrication of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To etch an oxide film without causing any damage on a silicon nitride film by etching an interlayer insulation film with first specified etching gas until a nitride film is exposed partially and then etching the remaining interlayer insulation film with second specified etching gas. SOLUTION: As a first stage, an interlayer insulation film 13 is etched from the surface to the corner P of second coating layer 12b with first etching gas containing at least Cx1Fx1 gas to form the majority on the upper side of contact holes 15, 16. The first etching gas is typically a mixed gas containing C4F8 gas, CO gas, or the like. In second stage etching process, the interlayer insulation film 13a remaining in the contact holes 15, 16 is etched with second etching gas containing at least CHx2Fx2 gas for form the remaining part of storage contact holes 15, 16. The second etching gas is typically a mixed gas containing CHF3 gas, Ar gas, or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for forming an extremely fine contact hole into a self-aligned contact (SAC).
The present invention relates to a method for manufacturing a semiconductor device having a step realized by using an ontact technique. Further, the principle of the present invention can be applied to formation of a damascene wiring layer which has been developed in recent years.

[0002]

2. Description of the Related Art With the miniaturization of elements and patterns of large-scale semiconductor integrated circuits (LSIs), SAC technology has been adopted. In the SAC technique, when wiring is connected to two MOS transistors having one impurity diffusion layer as a common component, an insulating layer on the surface of two gate electrodes is used.
This regulates the connection position of the wiring.

As described above, the use of the SAC makes it possible to easily and surely connect the wiring with the impurity diffusion layer between the gate electrodes, which has become narrower with miniaturization. Here, a conventional method for manufacturing a semiconductor device employing the SAC technology will be described. 1 to 4 show SA
Conventional DRAM cell (dynamic rand)
om access memory cell) as an example.

[0004] As shown in FIG.
01, LOCOS (local oxidation of silico
n), an element isolation region 102 of
One element formation region S is surrounded by the element isolation region 102. A gate oxide film 103 is formed on the upper surface of the silicon substrate 101 in the element formation region S. On the gate oxide film 103, two gate electrodes 104 having a multilayer structure are formed. The gate electrode 104 is composed of a silicon layer, a silicide layer, an oxide film, an antireflection film, and the like in order from the bottom. The word line WL of the DRAM passes over the gate oxide film 103 and the element isolation region 102, and a portion of the element formation region S that passes over the gate oxide film 103 functions as the gate electrode 104 of the MOS transistor.

By implanting an impurity of the first conductivity type on the upper surface of the silicon substrate 101 using the gate electrode 104 as a mask, a shallow low-concentration impurity diffusion layer 109 is formed.
To form An oxide layer is formed on the entire surface, and this oxide layer is etched in the vertical direction to leave a part of the oxide layer on both sides of the gate electrode 104. To form

Thereafter, using the sidewalls 110, the gate electrode 104 and the like as a mask, an impurity is introduced and activated to form a deep high-concentration impurity diffusion layer 111. The deep impurity diffusion layer 111 and the shallow impurity diffusion layer 109 are formed. Thus, an LDD is formed. Subsequently, on the entire surface to form a second coating layer 113 made of the first coating layer 112 and the Si ₃ N ₄ consisting of SiO _2, to form the SiO ₂ which functions as an interlayer insulating layer 114 thereon.

After that, a photoresist 115 is applied on the interlayer insulating film 114, and is exposed and developed to form a window (opening) 1.
15a is formed. 1 (B) through this window 115a.
As shown in, using the C _X F _Y-based gas dry etching the interlayer insulating film 114 in the vertical direction as an etchant, as subsequently shown in FIG. 2 (A), a second covering layer 1
13 is etched using an SF ₆ -based gas, and the first coating film 112 is etched using a CHF ₃ gas to form contact holes 116 and 117.

After that, as shown in FIG. 2B, the photoresist 115 is removed, and the first conductive film 118 and the dielectric film 11 are formed on the inner peripheral surface of the storage contact hole 117.
9, a second conductive film 120 is formed, and at the same time, a first conductive film 118 is formed on the inner peripheral surface of the bit line contact hole 116.
A dielectric film 119 and a second conductive film 120 are formed. The first conductive film 118 is removed from the uppermost surface of the interlayer insulating film 114.

The first in the bit line contact hole 116
Is connected to a predetermined bit line. In the two storage contact holes 117,
The first conductive film 118, the dielectric film 119, and the second
The capacitors C ₁ and C ₂ made of the conductive film 120 are formed. Next, as shown in FIG. 3A, a BPS is formed on the second conductive film 120 made of polysilicon containing impurities.
A second interlayer insulating film 121 made of G is formed. Further, a second resist pattern 122 having a wiring pattern passing above the storage contact hole 117 is formed.
Is formed on the interlayer insulating film 121 of FIG.

Then, the second interlayer insulating film 121 and the second conductive film 120 exposed from the resist pattern 122 are removed by etching in order. As a result, the lead wiring 1 made of polysilicon is formed on the first interlayer insulating film 114.
23a and 123b are formed. Next, the extraction wiring 123
Insulating sidewalls 124a and 124b as shown in FIG. 3B are formed on both sides of a and 123b.

Thereafter, as shown in FIG. 4, a bit line 125 having a three-layer structure made of titanium (Ti), titanium nitride (TiN) and tungsten (W) is formed on the bit line contact hole 116 in order from the bottom. Is done. Bit line 12
4 is connected to the impurity diffusion layer 111 via the first conductive film 118 in the bit line contact hole 116.

[0012]

SUMMARY OF THE INVENTION
The method has been described with reference to FIGS. 1 (B) and 2 (A).
Thus, a photoresist 115 is coated on the oxide film 113.
Cloth, exposure and development to form window (opening) 115a
You. Through this window, C as an etchant_XF_YSystem
Dry etch the interlayer insulating film 114 in the vertical direction
And then SF ₆System gas (for example, SF₆+ HBr + N_Two
Or SF₆+ O_Two+ N_Two) To remove the second coating layer 113.
And CHF_ThreeFirst covering layer 11 using gas
2 is being etched.

In this case, ideally, it is preferable that the etching gas selectively etches only the interlayer insulating film 114 without damaging the second coating layer 113.
That is, the “second etching rate” of “interlayer insulating film 114 etching rate”
Of the coating layer 113 is preferably high. That is, when the interlayer insulating film 114 is made of a silicon oxide film and the second coating layer 113 is made of a silicon nitride film, the ratio of “etching speed of silicon oxide film” to “etching speed of silicon nitride film” is high. preferable. This ratio, (etching rate of silicon oxide film) / (etching rate of silicon nitride film), is also called an etching selectivity of the silicon nitride film to the silicon oxide film.

Second etching rate of interlayer insulating film 114
If the ratio of the coating layer 113 to the etching rate is not sufficiently high, the corner portion 111 of the second coating layer (Si ₃ N ₄ film) 113 during the etching of the interlayer insulating film (SiO ₂ film) 114
3a will be scraped and damaged as shown in FIG. If such damage is large, the contact hole 11
6, 117, the gate electrode 104 and the first conductive film 118
Short circuit.

In such a semiconductor manufacturing method, it is necessary to develop a process for increasing the etching selectivity of the silicon nitride film to the silicon oxide film. Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming a contact hole by selectively etching a silicon oxide film without damaging the silicon nitride film.

[0016]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having an etching step of partially exposing a nitride film when etching an interlayer insulating film made of an oxide film. And at least C _X1 F _Y1
(X1, Y1 is the number of components) using a first etching gas system having a gas until the nitride film is partially exposed.
A first etching step of etching the interlayer insulating film;
A second etching step of etching the remaining interlayer insulating film using a second etching gas system having at least a CH _X2 F _Y2 (X2, Y2 is the number of components) gas.

In such a semiconductor device manufacturing method,
The nitride film covers the wiring layer. Those wiring layers are SA
There are two or more contact holes in a contact hole formed by using the C technique, and the contact hole can be formed by using the first etching step and the second etching step. In the above-described semiconductor device manufacturing method, the wiring layer may be a polysilicon wiring layer, a polycide wiring layer, or a metal wiring layer. The silicon oxide film is made of silicon dioxide, BPSG (boro-phospho silicate).
glass), PSG (phospho silicate glass), BSG (b
Oro silocate glass) or SOG (spin on glass) may be used.

Further, in the above-described method for manufacturing a semiconductor device, the first etching gas system may include C ₂ F ₆ gas and C ₂ F ₆ gas.
_It may be any one gas selected from the group consisting of ₃ F ₈ gas and C ₄ F ₈ gas or a mixed gas of any two or more thereof. The first etching gas system is typically a C ₄ F ₈ , CO, Ar, O ₂ mixed gas system.

In the method of manufacturing a semiconductor device according to the present invention, in the method of manufacturing a semiconductor device described above, the second etching gas system may include a CHF ₃ gas, a CH ₂ F ₂ gas and a CH ₃ F gas.
It may be any one gas selected from the group consisting of gases or a mixed gas of any two or more thereof. The second etching gas system typically comprises CHF ₃ , A
r, O ₂ mixed gas system.

The nitride film may be a silicon oxynitride film or a silicon nitride film. The method of manufacturing a semiconductor according to the present invention is a method of manufacturing a semiconductor device having a step of forming a contact hole by etching a silicon oxide film.
_Using a first etching gas system having _X1 F _Y1 gas,
A first etching step of etching the interlayer insulating film up to the vicinity of the nitride film, and a second etching step having at least a CH _X2 F _Y2 gas.
A second etching step of etching and etching the remaining interlayer insulating film using an etching gas system of (1), wherein an organic fluoride is formed on the surface of the nitride film and the remaining interlayer insulating film by the first etching step. In the second etching step, the thin layer of the organic fluoride on the silicon nitride film functions as an etching stop layer to protect the silicon nitride film and remove the remaining silicon nitride film. The thin layer of the organic fluoride on the oxide film can be etched, and thus the remaining interlayer insulating film is selectively etched.

The method of manufacturing a semiconductor device according to the present invention can be applied to etching of a dual damascene structure having an insulating layer, a silicon nitride film and an insulating layer. One of the features of the present invention is that a two-stage etching process is employed in the SAC etching process in order to avoid the corner portions of the coating layer made of the silicon nitride film from being scraped.

First, as a first step, a silicon oxide film is
Etching is performed using a first etching gas system having at least C _X1 F _Y1 gas over a depth until a portion of the silicon nitride film is exposed from the surface to form a large portion above the contact hole. In the first-stage etching, if the silicon nitride film is etched to the bottom of the hole, the corner portion on the side of the electrode is damaged or scraped.

Next, as a second etching step,
Etching the remaining silicon oxide film left unetched in the contact hole using a second etching gas system having at least CH _X2 F _Y2 gas,
The formation of the remaining portion of the contact hole prevents the corner of the silicon nitride film from being cut.

This two-step etching process has the following features. In the first stage of etching, the plasma is temporarily stopped before the corners of the silicon nitride film are damaged or scraped. At the end of this stage, a polymer is formed on the exposed surfaces of the silicon nitride film and silicon oxide film in the contact holes. In the etching step of the second stage, the film is not etched by the film type under the polymer formed in the etching of the first stage, or is etched in the opposite direction. That is, while the silicon nitride film under the polymer remains without being etched, the remaining silicon oxide film under the polymer and the silicon nitride film under the silicon oxide film are selectively etched.

Such selective etching characteristics can also be applied to etching for forming a dual damascene structure.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor device manufacturing method according to the present invention will be described in detail with reference to the accompanying drawings. In the figure, for the same element,
The same reference numerals are used to omit redundant description. First Embodiment (Semiconductor Device Manufacturing Method) FIGS. 6 to 10 show a self-aligned contact (SAC; Self Align) taking a DRAM cell as an example.
The semiconductor device manufacturing method employing the ed Contact) technology is shown in the order of each process.

As shown in FIG. 6A, an element isolation region 2 composed of a field oxide film formed by a selective oxidation method is formed on a silicon substrate (semiconductor substrate) 1.
Two adjacent element formation regions S are surrounded by the element isolation region 2. The method for forming the element isolation region 2 may be a generally known method. Element formation region S
On the upper surface of the silicon substrate 1, a gate oxide film 3 made of, for example, about 60 ° SiO ₂ is formed.

Next, the gate oxide film 3 in each element formation region S
A gate electrode 4 is formed thereon. This gate electrode 4
May be any of a polysilicon wiring layer, a polycide wiring layer, and a metal wiring layer. As shown in FIG. 6B, the gate electrode 4 of this embodiment includes a silicon layer 5 and a silicide layer 6 formed on the gate oxide film 3 in this order.
An oxide film 7 and an antireflection film 8 are formed on the silicide layer 6 in this order from the bottom. The oxide film 7 serves as the gate electrode 4
Functions as a cap layer. Then, the antireflection film 8
Prevents the exposure light from being reflected by the oxide film 7 in the photolithography process at the time of pattern formation.

The silicon layer 5 has, for example, a thickness of about 500.degree.
The silicide layer 6 is made of, for example, tungsten silicide (W
The oxide film 7 is, for example, an SiO ₂ film having a thickness of about 800 °, and the antireflection film 8 is, for example, a silicon nitride (Si _{3) having} a thickness of about 350 °.
N ₄ ).

These layers and films are patterned into stripes by photolithography using a resist mask (not shown) as shown in FIG. Form. The striped silicon layer 5 and the silicide layer 6 are used as word lines WL of the DRAM. The word line WL passes over the gate oxide film 3 and the element isolation region 2, and a portion passing over the gate oxide film 3 functions as the gate electrode 4 of the MOS transistor.

Next, as shown in FIG. 6B, an impurity of the first conductivity type is introduced into the upper surface of the silicon substrate 1 using the gate electrode 4 and the element isolation region 2 as a mask. Then, a shallow low-concentration impurity diffusion layer 9 is formed in the silicon substrate 1. This impurity has a conductivity type opposite to that of the impurity contained in silicon substrate 1. Subsequently, an insulating film made of, for example, SiO ₂ having a thickness of 1000 ° is formed on the entire surface of the silicon substrate 1. Further, this insulating film is vertically etched using an RIE (reactive ion etching) apparatus to leave a part thereof, thereby forming sidewalls 10 on both side surfaces of the gate electrode 4.

Thereafter, using the side walls 10, the gate electrode 4 and the like as a mask, impurities are introduced into the silicon substrate 1 through the space between the two side walls 10 facing each other, and are activated to form a deep high-concentration impurity. Diffusion layer 11
Is formed in the silicon substrate 1. The source / drain of the LDD (Lightly Doped Drain) structure of the MOS transistor is formed by the deep impurity diffusion layer 11 and the shallow impurity diffusion layer 9.

Subsequently, as shown in FIG.
That is, the exposed gate electrode 4 and sidewall 1
0, a first coating film 12a made of, for example, SiO ₂ and a second coating layer 12b made of Si ₃ N ₄ are formed by a CVD method so as to cover the element isolation region 2 and the like. Furthermore, for example, SiO ₂ or BPSG (borophospho) is formed on the second coating layer 12b.
o-silicate glass)
μm) of the interlayer insulating layer 13 is formed.

Thereafter, as shown in FIG. 7A, a photoresist 14 is applied on the interlayer insulating film 13, and is exposed and developed to form a window (opening) 14a. The window 14a of the photoresist 14 is formed above the high-concentration impurity diffusion layer 11 so that a capacitor (not shown) is electrically connected to the high-concentration impurity diffusion layer 11 through a contact hole to be described below. It is formed to be positioned.

Next, as shown in FIGS. 7B and 8A,
Utilizing the window 14 a formed in the photoresist 14, the lower end (back surface) is vertically formed from the surface of the interlayer insulating film 13.
Are formed by etching. The contact hole 1 to be formed from the high-concentration impurity layer 11 positioned between the side walls 10 facing the two adjacent gate electrodes 4 is formed.
Since the second and fifth coating layers 5 and 16 are positioned by the second coating layer 12b coated on the side walls 11, the contact holes 15 and 16 and the corresponding high-concentration impurity layers 11 are inevitably aligned with each other. Have been.
The etching step for forming the contact hole is also called “SAC etching step”.

The contact holes 15, 16
According to the function, the one adjacent to the element isolation region 2 is called a storage contact hole 15 and the contact hole between the two storage contact holes 15 is called a bit line contact hole 16.
One of the features of the present embodiment is that in the SAC etching step, a two-step etching step described below is devised in order to prevent the corner portion of the second coating layer 12b from being scraped. The etching apparatus used in this two-stage etching process is a high-frequency parallel plate etcher in which two types of high-frequency (RF) power sources are connected to upper and lower two electrodes, respectively. Occurs. Specifically, the upper electrode has 27.1.
2 MHz is connected, and a high frequency power supply of 800 kHz is connected to the lower electrode.

First, as a first step, as shown in FIG. 7B, an interlayer insulating film 13 is formed on the surface of the second insulating layer 12b from the surface thereof.
At least C _X1 F over the depth to the corner P of
Etching is performed using a first etching gas system having _X1 gas to form most of the upper portions of the contact holes 15 and 16. The first etching gas system typically comprises
A mixed gas system containing C ₄ F ₈ gas, CO gas, Ar gas, and O ₂ gas (hereinafter referred to as “C ₄ F ₈ / CO / Ar / O
₂ mixed gas system ". ). The flow rates of the respective gases of the C ₄ F ₈ / CO / Ar / O ₂ mixed gas system used in the first stage etching step are as follows, for example.

C ₄ F ₈ : 10 ml / min. CO: 100 ml / min. Ar: 400 ml / min. O ₂ : 5 ml / min. Alternatively, the first etching gas system is a C ₂ F ₆ gas,
Any one gas selected from the group consisting of C ₃ F ₈ gas and C ₄ F ₈ gas or a mixed gas of any two or more thereof may be used.

As will be described in detail later, the feature of the first-stage etching is stopped before the corner portion P of the second coating layer 12b, which has conventionally been a problem (see FIG. 5), is abraded. It is in. Next, as a second stage etching step, as shown in FIGS. 7B and 8A, at least the remaining interlayer insulating film 13a remaining without being etched in the contact holes 15 and 16 is removed. The remaining portions of the storage contact hole 15 and the bit line contact hole 16 are formed by etching using a second etching gas system having CH _X F _X gas.

The second etching gas system typically comprises
It is a mixed gas system containing a CHF ₃ gas, an Ar gas, and an O ₂ gas (hereinafter, also referred to as “CHF ₃ / Ar / O ₂ mixed gas system”). That is, the remaining interlayer insulating film 13a is etched by the CHF ₃ / Ar / O ₂ mixed gas system, and the second covering layer 12b corresponding to the bottom surfaces of the contact holes 15 and 16 and the second covering layer 12b therebelow. One coating layer 12a is selectively etched. Thus,
Contact holes 15 and 16 reach impurity diffusion layer 11. CHF ₃ used in the second etching process
The flow rate of each gas of the / Ar / O ₂ mixed gas system is as follows as an example.

CHF ₃ : 50 ml / min. Ar: 300 ml / min. O ₂ : 5 ml / min. Alternatively, the second etching gas system is CHF ₃ gas,
Any one gas selected from the group consisting of CH ₂ F ₂ gas and CH ₃ F gas or a mixed gas of any two or more thereof may be used.

It has been found that the two-stage etching process has the following advantages and effects. (1) In the first stage etching, the second etching made of Si ₃ N ₄
Is not etched, and as a result, the corner portions P of the second coating layer 12b cannot be removed. (2) In the second stage etching step, the second coating layer 12b is not etched similarly, and the remaining interlayer insulating film 13
Only a is selectively etched.

(3) In the second stage etching step, a portion of the second coating layer 12b which is close to the gate oxide film 3 is selectively etched. (4) If only the second stage etching is performed without performing the first stage etching, the second coating layer 12b made of Si ₃ N ₄ is etched. The details of the two-step etching process that provides such advantages and effects will be described later.

Thereafter, as shown in FIG. 8B, the photoresist 14 is removed, and a first conductive film (electrode) 18 made of, for example, polysilicon is formed by a CVD method. Thereafter, a portion of the first conductive film 18 on the outermost surface of the interlayer insulating film 13 is polished and removed. Further, as shown in FIG. 9A, the surface of the interlayer insulating film 13 is
A dielectric film 19 made of, for example, SiO ₂ , SiN or the like is formed on the first conductive film 17 in each of the layers 5 and 16 by a CVD method.

Further, a second conductive film (electrode) 20 made of, for example, polysilicon is grown in the contact holes 15 and 16 by the CVD method. In the storage contact hole 15, a capacitor Ca including a first conductive film 18, a dielectric film 19, and a second conductive film 20,
Cb is formed. In addition, if necessary, the interlayer insulating film 1
By providing an intermediate wiring layer on 3 and further forming another interlayer insulating film on this intermediate layer, the number of wiring layers can be two or more.

Next, a second interlayer insulating film 21 made of BPSG is formed on the second conductive film 20 made of polysilicon containing impurities. Further, as shown in FIG.
A resist pattern having a wiring pattern passing above the storage contact hole is formed on the second interlayer insulating film. And resist pattern 2
The second interlayer insulating film 21 and the second conductive film 20 exposed from Step 2 are sequentially etched and removed. Thereby, the first
Lead wires 23a and 23b made of polysilicon are formed on the interlayer insulating film 13.

Next, insulating sidewalls 24a and 24b are formed on both sides of the lead wires 23a and 23b. Thereafter, as shown in FIG. 10, a bit line 25 having a three-layer structure made of titanium (Ti), titanium nitride (TiN) and tungsten (W) is formed on the bit line contact hole 16 in order from the bottom. Bit line 25 is connected to impurity diffusion layer 11 via first conductive film 18 in bit line contact hole 16. The DRAM is manufactured through the above steps and, if necessary, further steps. [Two-Step Etching Step] At present, a sufficient theoretical analysis has been performed on the exact cause or mechanism that provides the advantages and effects of the two-step etching described with reference to FIGS. 7B and 8A. Not. However, the inventor has confirmed that the following phenomena have occurred through subsequent experiments.

FIG. 11 is an enlarged view of a portion around the corner P of the second coating layer 12b of the semiconductor substrate in the manufacturing stage of FIG. 7B. (First-stage etching) First, the first-stage etching process, that is, the interlayer insulating film 13 made of silicon oxide is etched using a C ₄ F ₈ / CO / Ar / O ₂ mixed gas system as an etching gas. When the depth reaches the corner portion P of the second coating layer 12b, in this state, the surface of the second coating layer 12b made of the exposed Si ₃ N ₄ film and the remaining interlayer insulating film 13a are removed. Organic fluoride layer 1 on the surface
7 are formed uniformly, and it is confirmed that the second coating layer 12b is protected from the etching gas. It should be noted that the organic fluoride layer 17 is assumed to be a very thin film of about several nm, but is drawn in an exaggerated manner in the figure.

To confirm that the compound is an organic fluoride, an experimental sample simulating the first-stage etching is prepared, treated under the same conditions as in the first-stage etching process, and the surface thereof is subjected to X-ray photoelectron spectroscopy ( XPS; X-ray photoemission
spectoroscopy) (ESCA electron spectroscopy fo
r Also called chemical analysis. The analysis was performed by using C), and C and F were detected from the surface of the Si ₃ N ₄ film constituting the second coating layer 12b and the surface of the remaining interlayer insulating film 13a. Therefore, the organic fluoride layer 17 is determined to be a polymer.

Next, in the first etching step, Si
₃ N ₄ To confirm the function or action of the organic fluoride layer 17 covering the second coating layer 12b made of film, to create a sample to form a coating layer made of the Si ₃ N ₄ film on a silicon substrate of a flat plate It was subjected to etching by the first stage _{C 4 F 8 / CO / Ar} / O 2 mixed gas system, Si ₃ N ₄ film is etched in the base, Si ₃ organic fluoride layer 17 from an etching gas it was confirmed that protects the N ₄ film.

However, as shown in FIG.
Even at the corners (shoulders) of the Si ₃ N ₄ film covered with 7, if the plasma is irradiated too much, the corners are broken by the plasma. Therefore, the first-stage C ₄ F ₈ / CO / Ar / O ₂ described with reference to FIG.
In the etching process of the interlayer insulating film 13 using the mixed gas system, even if the organic fluoride layer 17 covers the corner portion P of the second covering layer 12b, the contact hole 15.16 is formed.
When the interlayer insulating film 13 in the inside is completely removed, the corner P
Was found to collapse.

(Second Stage Etching) Next, when the remaining interlayer insulating film 13a is etched using the CHF ₃ / Ar / O ₂ mixed gas system in the second stage, the second coating layer 12 is etched.
It has been confirmed through the following experiment that the corner portion P of b is not etched and only the remaining interlayer insulating film 13a is selectively etched.

First, an Si ₃ N ₄ film constituting the second coating layer 12b is formed on a flat silicon substrate sample, and a C ₄ F ₈ / CO / Ar / O ₂ mixed gas of the first stage is formed. Forming a film of organic fluoride by etching with the system,
After that, etching was performed in a second stage using a CHF ₃ / Ar / O ₂ mixed gas system. As a result, it was confirmed that the Si ₃ N ₄ film which was the underlying layer of the organic fluoride film was not etched.

On the other hand, the remaining interlayer insulating film 13a is formed.
SiO_TwoA film is formed and the first stage C_FourF ₈/ CO / Ar / O
_TwoOf organic fluoride by etching with mixed gas system
Create a flat silicon substrate sample with the film formed,
Second stage CHF_Three/ Ar / O_TwoUsing a mixed gas system
After etching, the film of organic fluoride and under it
SiO as the stratum_TwoMake sure the film is etched.
I accepted.

According to this experiment, in the etching using the CHF ₃ / Ar / O ₂ mixed gas system of the second stage described with reference to FIG. 8A, the corner P of the second coating layer 12b is formed.
Was not etched, and only the remaining interlayer insulating film 13a was selectively etched. The inventor of the present invention has described the mechanism for selectively etching only the organic fluoride 17 on the interlayer insulating film 13a without etching the organic fluoride layer 17 on the second coating layer 12b as follows. Make a hypothesis.

First, carbon C is deposited on the surface of the interlayer insulating film 13a.
And F are confirmed by analysis by X-ray photoelectron spectroscopy. At this time, CHF ₃ / Ar /
The carbon C on the surface of the interlayer insulating film 13a exposed to the O ₂ mixed gas system reacts easily with oxygen in the interlayer insulating film 13 of the underlying layer to easily form CO or CO _2. It is presumed that they are separated, thereby weakening or losing the etching inhibition function.

Further, the present inventor has determined that the portion of the second coating layer 12b where the organic fluoride layer 17 is not formed is etched by the second stage CHF ₃ / Ar / O ₂ mixed gas system. I have confirmed. At this time, the portion of the second coating layer 12b facing the side wall 10 is such that the etching gas is anisotropic and the corner P
Is hardly etched because the portion 17a of the organic fluoride layer covering the layer functions as a resist (mask). Even if some damage occurs, the presence of the side wall 10 behind the second covering layer 12b causes a lateral dent or a wiring passing through the adjacent contact holes 15 and 16. No short-circuiting problem occurs. On the other hand, contact holes 15, 1
The etching gas directly acts on the second coating layer 12b at the bottom of the substrate 6, and this portion and the first coating film 12a thereunder are etched to form an opening reaching the impurity diffusion layer 11. Form. (Alternative Example of Etchant) It has been confirmed that the following mixed gas may be used as an alternative example of the etchant C ₄ F ₈ / CO / Ar / O ₂ mixed gas system in the first etching step.

CH ₂ F ₂ gas, O ₂ gas, C ₄ F ₈
A mixed gas of a gas and an Ar gas. The flow rates are
10 ml / min. , 3 ml / min. , 15 m
1 / min. , 500 ml / min. It is. [Other Embodiments] In the two-step etching described above, first, an organic fluoride is deposited on the surface of the coating layer made of Si ₃ N ₄ and the remaining oxide layer in the first step etching, and then the second step etching is performed. In the step etching, the organic fluoride on the coating layer functions as an etching stopper film, and other portions are selectively etched. This method is applicable to dual damascene etching using Si ₃ N ₄ as an etching stopper. The dual damascene structure is
Since the semiconductor device has an insulating layer, a silicon nitride film and an insulating layer, in this etching step, a first etching gas system having at least C _X1 F _Y1 gas is used until the silicon nitride film is partially exposed. The insulating layer may be etched, and the remaining insulating layer may be etched using a second etching gas system having at least CH _X2 F _Y2 gas.

Similarly, the present invention can be applied to a Si ₃ N ₄ film exposed borderlessly during etching of an oxide film. That is, a thin film of a polymer is deposited on the surface of a Si ₃ N ₄ film using an etchant C ₄ F ₈ / CO / Ar / O ₂ mixed gas system, and the etching inhibition function of the polymer thin film is effectively used. It can be applied to all etching processes.

[0060]

According to the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of forming a contact hole by etching a silicon oxide film without damaging a silicon nitride film.

[Brief description of the drawings]

FIGS. 1A and 1B are cross-sectional views (part 1) illustrating a conventional semiconductor device manufacturing method.

FIGS. 2A and 2B are cross-sectional views (part 2) illustrating a conventional method for manufacturing a semiconductor device.

FIGS. 3A and 3B are cross-sectional views (part 3) illustrating a conventional method for manufacturing a semiconductor device.

FIG. 4 is a sectional view (part 4) illustrating the conventional method of manufacturing a semiconductor device;

FIG. 5 is a cross-sectional view related to FIG. 1 and illustrating a problem in a conventional semiconductor device manufacturing method.

FIGS. 6A to 6C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIGS. 7A and 7B are cross-sectional views (part 2) illustrating the method for manufacturing a semiconductor device according to the embodiment of the present invention;

FIGS. 8A and 8B are cross-sectional views (part 3) illustrating the method for manufacturing a semiconductor device according to the embodiment of the present invention;

FIGS. 9A and 9B are cross-sectional views (part 4) illustrating the method for manufacturing a semiconductor device according to the embodiment of the present invention;

FIG. 10 is a sectional view (No. 5) showing the semiconductor device manufacturing method according to the embodiment of the present invention;

FIG. 11 illustrates the advantages and effects of the two-stage etching process of the method for manufacturing a semiconductor device according to the embodiment of the present invention, particularly, with reference to FIGS. 7B and 8A. FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation region, 3 ... Gate oxide film, 4 ... Gate electrode, 5 ... Silicon layer, 6 ... Silicide layer, 7 ... Oxide film, 8 ... Antireflection film, 9 ... Low concentration impurity diffusion layer Reference numeral 10: sidewall, 11: high-concentration impurity diffusion layer, 12a: first coating layer, 12b: second coating layer, 1
3 ... interlayer insulating film, 13a ... remaining interlayer insulating film, 14 ... photoresist, 15 ... storage contact hole,
16: bit line contact hole, 17: organic fluoride, 18: first conductive film (electrode), 19: dielectric film, 2
0: second electrode (electrode), S: element formation region.

Claims (13)

[Claims] A step of forming first and second electrodes above a semiconductor substrate; a step of forming a nitride film covering the first and second electrodes; and a step of forming silicon oxide on the nitride film. Or a step of forming an interlayer insulating film made of a material containing silicon oxide; and forming the silicon nitride film partially by using a first etching gas having at least C _X1 F _Y1 (X1, Y1 is the number of components) gas. A first etching step of etching the interlayer insulating film between the first and second electrodes to form a part of a hole until the first electrode is exposed to at least CH _X2 F _Y2 (where X 2, Y2 is a second etching gas having a (component number) gas and a second etching gas for etching the remaining interlayer insulating film to deepen the hole.
A method of manufacturing a semiconductor device, comprising: 2. The method according to claim 1, further comprising the step of etching the nitride film below the hole using the second etching gas. 3. The method according to claim 1, wherein an impurity diffusion layer is formed in the semiconductor substrate below a region between the first and second wirings. 4. The method according to claim 1, wherein the first etching gas system is C ₂ F.
₆ gas, according to claim 1, characterized in that the C ₃ F ₈ gas and C ₄ F ₈ any one gas, or any combination of two or more gases selected from the group consisting of gas Of manufacturing a semiconductor device. 5. The method of claim 1, wherein the first etching gas system is C_FourF
₈And CO, Ar and O _TwoCharacterized by a mixed gas of
A method for manufacturing a semiconductor device according to claim 4. 6. The second etching gas system comprises CHF.
₃ gas, according to claim 1, characterized in that the CH ₂ F ₂ gas and CH ₃ F from the group consisting of gas any selected one gas, or any combination of two or more gas A method for manufacturing a semiconductor device. 7. The second etching gas system is CHF.
₃ the method of manufacturing the semiconductor device according to claim 6, characterized in that a mixed gas of Ar and O _2. 8. The method according to claim 1, wherein the nitride film is a silicon nitride film or a silicon nitride oxide film. 9. The method according to claim 1, wherein the wiring layer is a polysilicon wiring layer, a polycide wiring layer, or a metal wiring layer. 10. The method according to claim 1, further comprising forming a silicon oxide film between the first and second electrodes and the nitride film. 11. A thin layer of organic fluoride is grown on the surface of the nitride film and the remaining interlayer insulating film by the first etching step, and in the second etching step, the organic fluoride on the nitride film is formed. The thin layer of fluoride functions as an etch stop layer to protect the nitride film, and the thin layer of organic fluoride on the remaining interlayer insulating film can be etched, thus removing the remaining interlayer insulating film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein selective etching is performed. 12. The first electrode is a gate electrode of a first MOS transistor, and the second electrode is a second MOS transistor.
The method according to claim 1, wherein the method is a gate electrode of a transistor. 13. In the etching of a dual damascene structure having an insulating layer, a silicon nitride film and an insulating layer, the silicon nitride film is partially etched using a first etching gas system having at least C _X F _Y gas. A first etching step of etching the insulating layer until it is completely exposed, and a second etching step of etching the remaining insulating layer using a second etching gas system having at least a CH _X F _Y gas.
A semiconductor device manufacturing method, comprising: