JPH06244377A - Integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To allow a sharp reduction of the number of manufacturing processes of memories including a memory cell having a fin structure stacked capacitor while, as a result, improving a manufacturing yield and reliability of this kind of integrated circuits in relation to a manufacturing method of an integrated circuit device. CONSTITUTION:After forming an interlayer insulating film 3 covering an Si semiconductor substrate 1, a laminate consisting of a-C film 11 and a polycrystal Si film is formed, the laminated is etched in a condition able to have a selective ratio to the interlayer film 3 so as to form a part of a storage electrode contact hole, the interlayer insulating film 3 is etched so as to make it to perform drawing penetration of the storage electrode contact hole in order to exhibit a part of the semiconductor substrate for forming the Si film on the surface including the inside of the storage electrode contact hole. Then, after the Si film and the laminate are patterned in the shape of the storage electrode, a-c film 11 is removed in order to finish the storage electrode having fins 12A, 12B, 12C of Si extending in the branched form from an Si body part located in the storage electrode contact hole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
Random access memory (dynamic ran)
The present invention relates to an integrated circuit device having a capacitor such as a dom access memory (DRAM), and a method suitable for manufacturing the same.

Generally, in a DRAM, a memory cell area (a flat area per 1 bit) is small in accordance with an increase in storage capacity, and a capacity capable of accumulating charges sufficient for storage retention / reading. There is a demand for a structure of a storage electrode having a large size.

In order to reduce the memory cell area and increase the capacitance of the capacitor, it is necessary to increase the surface area of the storage electrode. Therefore, the three-dimensional structure such as the trench capacitor and the stacked capacitor is required. In particular, a stacked capacitor having a fin structure (if necessary, "IEDM Tec
h. Dig. (1988), pp592) "or" I
EDM Tecn. Dig. (1991), pp47
7) ”) is effective.

However, this fin structure stacked
Since capacitors have various difficulties in terms of manufacturing, these must be improved successively.

[0005]

2. Description of the Related Art Generally, when forming a fin structure in a fin structure stacked capacitor, a multi-layered structure in which a required number of layers, for example, a SiO ₂ film (gap layer) and a polycrystalline Si film are alternately laminated is used. The processing is performed by alternately using a SiO ₂ etching process having selectivity to crystalline Si and an etching process of polycrystalline Si having selectivity to SiO ₂ .

In this processing, for example, a laminated body in which a SiO ₂ film and a polycrystalline Si film are alternately laminated is patterned into a shape of a storage electrode in a capacitor, and then Si is formed.
A process to remove the O ₂ film is needed.

At this time, in etching each film, each film must be completely etched and removed, and each film has a film thickness distribution, and
It is essential to perform so-called over-etching in order to compensate for the existence of an etching rate distribution.

When patterning the storage electrode, anisotropic etching is used in order to precisely transfer the resist pattern. However, since a residual film is apt to be generated in the step portion existing in the base, this also occurs. Must be removed by over-etching.

For this reason, sufficient selectivity is required in the etching process for the SiO ₂ film and the polycrystalline Si film.

[0010]

By the way, even in a memory cell having a fin-structure stacked capacitor, in order to improve the degree of integration, the memory cell area is reduced, and accordingly, the storage electrode of the capacitor is reduced. It is also necessary to reduce the area of the flat plane.

In such a case, in order to secure the required surface area of the storage electrode, it is necessary to deal with it by increasing the number of fins. At present, for example, in the case of 256 MDRAM, it is necessary to increase the number to five or more. It has become.

However, in the conventional technique, one fin is used.
Hit, two steps to form the electrode contact hole opening,
Two steps of etching are required to form the shape of the storage electrode
However, the opening of the electrode contact hole is formed on the uppermost layer.
Growth of polycrystalline Si film after opening electrode contact holes
This reduces the number of steps by one, and the bottom layer of SiO ₂
The film is SiO between the fins₂Remove simultaneously when removing the film
Since it is sufficient, etching for patterning is unnecessary.
Therefore, the number of steps is also reduced. Therefore, the storage electrode
The number of steps when forming is (number of fins x 5-2) steps
Is.

In practice, with respect to the number of steps described above, chemical vapor deposition (Chemical Vapor Deposition) is used to form a polycrystalline Si film and a SiO ₂ film per fin.
However, the number of steps is (the number of fins × 6−2),
For example, in the case of five fins, it is difficult to manufacture inexpensively because the etching process alone requires nine steps for forming the electrode contact hole opening and nine steps for forming the shape of the storage electrode. Further, as the number of steps increases, defective parts due to particles and the like generated in each step accumulate, which causes a problem that both manufacturing yield and reliability decrease.

In response to such a problem, the wafer is transferred under vacuum, and then the reaction chamber for SiO ₂ etching and the polycrystalline S are successively used.
Although it is possible to solve the problem to some extent by using a so-called multi-chamber type manufacturing apparatus that performs processing in the i-etching reaction chamber, the manufacturing apparatus is enormous and depends on it. In this case, the manufacturing cost is still high.

Further, the explanation was not only the number of problems process, to remove the SiO ₂ film is a gap layer between the fins, a SiO ₂ film, for example, depending on the hydrofluoric acid 2
It is necessary to laterally etch about 00 [nm]. However, in the structure of the integrated circuit device, it is unavoidable that defects occur in the pattern and the film due to particles and the like. If there is such a defect, hydrofluoric acid penetrates into the base from that portion and destroys the insulating structure such as the transfer transistor.

As an example of the above-mentioned defect, the electrode contact hole of the storage electrode is larger than the design, or the electrode contact hole pattern and the contact hole of the storage electrode are located larger than the design. This causes a problem that Si of the trunk portion of the storage electrode cannot be covered with the resist during processing of the storage electrode.

This is a problem that occurs locally due to particles or the like, and may be regarded as a lithographic defect. In such a case, S that constitutes the fin is formed.
When the i ₂ film and the SiO ₂ film between the fins are alternately etched, Si in the core is etched, and the underlying SiO ₂ film is exposed in the electrode contact hole, and hydrofluoric acid penetrates into it. To destroy the underlying structure.

Furthermore, after removing the SiO ₂ film between the fins by using hydrofluoric acid, there is a problem that the Si films forming the fins are bent and come in contact with each other. However, the area where the fin acts as a capacitor is reduced, and the capacity becomes insufficient, resulting in defective bits.

The present invention can significantly reduce the number of manufacturing steps of a memory including a memory cell having a fin structure stacked capacitor, and prevent destruction and bending of the fin due to a chemical solution such as hydrofluoric acid. As a result, an attempt is made to improve the manufacturing yield and reliability of this type of integrated circuit device.

[0020]

According to the present invention, in order to generate a fin gap between storage electrodes in a fin structure stacked capacitor, an amorphous carbon film or the like is used instead of the SiO ₂ film as a gap layer. Basically, it is necessary to use a material that has heat resistance and has a selective ratio with respect to an oxide film.

Therefore, in the method of manufacturing the integrated circuit device according to the present invention, the transfer transistor (for example, the word line W) is formed.
After forming an insulating film (for example, an interlayer insulating film 3 made of SiO ₂ ) covering a surface of a substrate (for example, a Si semiconductor substrate 1) on which a transfer transistor typified by a gate electrode that acts as L) is formed, A step of forming a laminated body composed of an amorphous carbon film (for example, an aC film 11) and a Si film (for example, a polycrystalline Si film 12), and then a laminated body composed of the Si film and the amorphous carbon film A storage electrode contact hole (for example, a storage electrode contact hole) is formed by performing etching (for example, etching by the RIE method using Cl ₂ + O ₂ mixed gas as an etching gas) under the condition that a selection ratio with the insulating film covering the surface of the substrate is obtained. 14), and then the insulating film covering the surface of the substrate is etched to form a storage electrode contact. A step of extending and penetrating the hole to expose a part of the substrate, and then a Si film (for example, polycrystalline S) on the surface including the inside of the storage electrode contact hole.
i film), and then patterning the Si film and the laminated body formed on the surface including the inside of the storage electrode contact hole into a storage electrode shape, and then removing the amorphous carbon film. The trunk of Si in the storage electrode contact hole (eg, polycrystalline Si
And a step of completing a storage electrode (for example, storage electrode 16) having Si fins (for example, fins 12A, 12B, 12C) extending in a dendritic form from the trunk portion 12CX of the above.

Further, the integrated circuit device of the present invention, as shown in FIG. 24, has insulating films 22 and 24 formed on a substrate 21.
And at least a first conductive film 26 that extends over the insulating film, is provided apart from each other, and has a first opening therein.
Through a second conductive film 28 formed along the inner side surface of the first opening and coupling the first conductive films to each other, and a second opening formed in the insulating film. A third conductive film 31 that contacts the substrate and is connected to the second conductive film, and that extends above the first conductive film at a distance from each other; and the first, second and third conductive films The insulating film 24 has a dielectric film 32 covering the film and a fourth conductor film 33 covering the dielectric film, and the surface portion of the insulating film 24 facing the first conductive film contains silicon oxide.

Another integrated circuit device of the present invention is shown in FIG.
As shown in FIG. 35, the insulating films 52 and 53 formed on the substrate 51, and the insulating films 52 and 53 extending on the insulating film and spaced apart from each other and having the first opening therein, at least one first film. A first conductive film 57 and an inner side surface of the first opening, is coupled to the first conductive film, and contacts the substrate through a second opening formed in the insulating film. And a second conductive film 60 that extends above the first conductive film with a space therebetween, a dielectric film 61 that covers the first and second conductive films, and a first conductive film that covers the dielectric film. 3 is a conductive film 62, and the diameter of the second opening is a skirt shape that increases with increasing distance from the substrate, and the second conductive film includes a portion having a substantially V-shaped cross section.

[0024]

According to the present invention, as described above, the SiO ₂ film is used in place of the SiO ₂ film in order to generate the fin gap between the storage electrodes made of a Si film such as a polycrystalline Si film or an amorphous Si film in the fin structure stacked capacitor. Using an amorphous carbon film, the Si film and the amorphous carbon film can be anisotropically etched at a substantially constant rate, and an etching technique capable of obtaining an etching selection ratio with an insulating film such as SiO ₂ or SiN. In the conventional technique, the number of steps required is four times the number of fins minus two, for example, if the number of fins is five, eighteen steps are required. Therefore, the manufacturing yield and reliability of this type of integrated circuit device are greatly improved.

[0025]

1 to 7 are sectional views of an essential part of an integrated circuit device at a process step for explaining a first embodiment of the present invention, which will be described in detail below with reference to these drawings. Explained. See FIG. 1 1- (1) At this stage, the field insulating film 2 on the Si semiconductor substrate 1
In the active region surrounded by, a transfer transistor represented by a gate electrode acting as a word line WL and a bit line B are formed.
In a state where L is formed and the surface is covered with the interlayer insulating film 3 made of SiO ₂ having a thickness of, for example, 300 [Å], after that, the process of forming a capacitor and the subsequent steps are performed. To do.

1- (2) Chemical vapor deposition
(Insulation: CVD) method, an insulating film made of SiO _{2 having} a thickness of, for example, 500 [Å] is formed.
Similarly, it is shown as being integrated with the interlayer insulating film 3 made of SiO ₂ , and is not particularly shown.

1- (3) P-CVD (plasma) using C ₂ H ₂ as a source gas
chemical vapor deposition
n) By applying the method, the thickness is, for example, 300 [Å]
The amorphous carbon (a-C) film 11 is formed.

1- (4) By applying the CVD method, the thickness is, for example, 300.
The polycrystalline SI film 12 of [Å] is formed.

1- (5) The steps 1- (3) and 1- (4) are repeated a required number of times to form a multi-layered structure including the aC film 11 and the polycrystalline Si film 12.

In this embodiment, the number of repetitions is three, and therefore
The number of stacked layers of the aC film 11 and the polycrystalline Si film 12 is three. Here, the uppermost polycrystalline Si film 12 has a thickness of 100 [Å], which means that the polycrystalline Si film formed after forming the storage electrode contact hole has the above-mentioned maximum thickness. It is taken into consideration that it is laminated on the upper polycrystalline Si film 12.

1- (6) By applying a resist process in the lithography technique, a resist film 13 having a thickness of, for example, 1 [μm] having an opening 13A for forming a storage electrode contact hole is formed.

Refer to FIG. 2. 2- (1) Reactive ion etching using a mixed gas of (Cl ₂ + O ₂ ) as an etching gas.
By applying the etching (RIE) method, the polycrystalline Si film 12 and the aC film 11 are anisotropically etched at a substantially constant rate to form the storage electrode contact hole 14. Incidentally, at this stage, the storage electrode contact hole 14 is not yet completed.

When this etching is performed, the resist film 1
Although the etching rate of No. 3 is considerably high, it is possible to fulfill the function as a mask until the etching is completed by keeping the above film thickness. The film thickness of the resist film 13 may be appropriately selected as needed.
At this time, even if some over-etching is performed,
The underlying interlayer insulating film 3 made of SiO ₂ is hardly affected.

See FIG. 3 3- (1) By applying the RIE method using a mixed gas of (CF ₄ + CHF ₃ ) as an etching gas, the interlayer insulating film 3 made of SiO ₂ is etched to contact the storage electrode.・
The hole 14 is extended and penetrated.

See FIG. 4. 4- (1) By applying the plasma ashing method using O ₂ gas, the resist film 13 used as the etching mask in the steps described with reference to FIGS. 2 and 3 is removed. .
At this time, the a-C film 11 is laterally etched by about 500 [Å].
The created void only enters the polycrystalline Si that will be formed later and contacts the fin made of polycrystalline Si.

If it is desired to avoid lateral etching in the aC film 11, the resist film 13 may be anisotropically ashed by applying the RIE method using O ₂ . Also, after removing only a part of the surface of the resist film 13 by ashing, 10% in a 0.5% HF solution is used.
Dip for about 2 seconds (HF-based wet treatment), and remove the remaining resist film 14 with a stripping solution (persulfate boiling treatment) at a temperature of 130 ° C. in which concentrated sulfuric acid and hydrogen peroxide were mixed at a ratio of about 100: 1. Is also good. It has been found that this stripper hardly etches aC. Therefore, by suppressing the ashing amount to be low, the etching amount in the lateral direction can be reduced.

The above-mentioned ashing, HF-based wet treatment, and persulfate boil treatment for avoiding lateral etching in the aC film 11 will be described later.

See FIG. 5 5- (1) By applying the CVD method, the storage electrode contact
A polycrystalline Si film having a thickness of, for example, 300 [Å] is formed on the entire surface including the inside of the hole 14. This polycrystalline Si film is combined with the uppermost polycrystalline Si film formed in the step 1- (5) to become the uppermost polycrystalline Si film.
It is indicated by the symbol 12.

A part of the uppermost polycrystalline Si film 12 extends into the storage electrode contact hole 14 and contacts the Si semiconductor substrate 1, and the lowermost or intermediate polycrystalline Si film 12 is formed. Has a different structure, the portion extending into the storage electrode contact hole 14 will be particularly referred to as a trunk portion 12CX.

5- (2) A resist film 15 having a storage electrode shape is formed by applying a resist process in the lithography technique.

See FIG. 6 6- (1) R using an etching gas as a (Cl ₂ + O ₂ ) mixed gas
By applying the IE method, the polycrystalline Si film 12 and a
By patterning the laminated body of the -C film 11 into the shape of the storage electrode, the fins 12A, 12B, and 12C having a shape that dendriticly extends from the trunk portion 12CX are formed.

Also in this etching, the resist film 1
Although the etching rate of No. 5 is high, it is sufficient to select a film thickness that can function as a mask until the etching is completed.

Further, due to a step existing in the interlayer insulating film 3 made of SiO _{2 as} a base, for example, 1200 [Å]
Even if some over-etching is required, Si
Since the etching rate of O ₂ can be reduced to 1/6 or less, the film loss 3A in the interlayer insulating film 3 in this case is 2
It will be about 00 [Å].

As will be described later, the removal of the resist film 15 may be performed by ashing (preferably downflow ashing), HF-based wet processing, and persulfate boiling.

See FIG. 7 7- (1) O ₂ plasma or O ₂ plasma downflow or UV
(Ultraviolet) / O ₃ is used to make use of oxygen radicals between the interlayer insulating film 3 and the fins 12A, and the fins 1
2A and fin 12B, fin 12B and fin 12C
The aC film 11 existing between and is removed.

By doing so, the three fins 12A for forming the fin structure stacked capacitor are formed.
A storage electrode 16 with ˜12 C is obtained. Note that FIG.
In the conventional technique described later with reference to FIG. 6, the film between the fins is SiO ₂ , and it is immersed in an HF solution to remove it. After this wet treatment, the immersed wafer needs to be dried. At this time, there is a problem that the fins are plastically deformed by the surface tension action of the water remaining between the fins. On the other hand, the above-mentioned processing such as O ₂ plasma downflow is a dry processing, and such a problem does not occur.

After that, the storage electrode 16 may be used to complete a capacitor and a memory by a conventional technique. That is, after growing Si3N4 as a dielectric on the surface of the fin-structured storage electrode by about 100 [Å], a polycrystalline Si film with a thickness of 1000 is formed by the CVD method.
The counter electrode is formed by growing it for about [Å], and the whole is covered with, for example, a PSG film, and Al wiring is performed.

Although the number of fins is three in the above-mentioned embodiment, the advantage according to the present invention is shown to be remarkable. Therefore, when the number of fins is five, for example, in the prior art, the storage electrode contact hole is shown. 9 times to open
It takes nine times to pattern the storage electrode shape, so that a total of 18 etching processes are required. If the steps of the above-mentioned embodiment are adopted, the polycrystalline Si film is subjected to CV etching.
The number of steps for growing by the D method is increased once, and the number of etching times is three, which is a total of four steps.

By the way, as described above,
If the -C film is removed, the fin may be deformed,
In order to avoid this, it is possible to prevent the chemical treatment from being performed after the removal of the aC film until the growth of the capacitor insulating film and the polycrystalline Si film serving as the counter electrode by the CVD method. In the method of directly removing the -C film by O ₂ plasma, the SiO ₂ film tends to grow thick on the surface of the Si film forming the fin during the plasma treatment.

Since this SiO ₂ film does not have sufficient insulating properties, a relatively thick capacitor insulating film is required in total in order to maintain the insulating characteristics of the capacitor, which makes it difficult to secure the capacitor capacitance. When oxygen radicals obtained by O ₂ plasma, O ₂ plasma downflow or UV / O ₃ method are used, the SiO ₂ film can be made thin, and a relatively large capacitor capacitance can be obtained even without chemical treatment. Both can be secured.

If the fin deformation does not matter,
It goes without saying that it is advantageous to remove the SiO ₂ film on the surface of the Si film by performing hydrofluoric acid treatment after removing the aC film, regardless of which removing means is used.

In the first embodiment, the electrode contact
Although a sufficiently thick resist film is used for each patterning of the holes and the storage electrodes, it is generally easier to use a thin resist film for forming fine patterning.

However, as described above, the Si film and a
When etching a laminated film with a -C film, the selection ratio of the resist is low, and therefore some processing is required to perform processing using a thin resist film. This will be explained as a sixth embodiment.

In summary, all of the second to fourth embodiments are related to the opening of the electrode contact hole, and the fifth and sixth embodiments form the storage electrode pattern. Is a technology related to.

Generally, in the opening of the electrode contact hole, the insulating film is always etched after the etching of the laminated film, but in the formation of the storage electrode pattern, it is basically necessary to protect the underlying interlayer insulating film after the etching of the laminated film. There are different configurations that must be dealt with. Therefore, more modifications can be realized by combining them with each other.

8 to 11 are cross-sectional views of the essential part of the integrated circuit device at the process steps for explaining the second embodiment of the present invention, which will be described in detail below with reference to these figures. Explained. The same symbols as those used in FIGS. 1 to 7 represent the same parts or have the same meanings. In addition, the steps up to forming the laminated body including the aC film 11 and the polycrystalline Si film 12 in multiple layers are exactly the same as those in the first embodiment described with reference to FIGS. I will explain it from the next stage.

See FIG. 8. 8- (1) By applying the CVD method, the thickness is, for example, 800.
An insulating film 17 made of SiO _{2 of} [Å] is formed.

By making the thickness of the insulating film 17 approximately the same as the thickness of the interlayer insulating film 3 made of SiO ₂ ,
It can play the role of minimizing the film loss that occurs in the aC film 11 in the subsequent etching of SiO ₂ .

When the SiO ₂ film is grown on the aC film, the temperature may be lowered. The reason is C
Since an oxidizing atmosphere is used to grow the SiO ₂ film by the VD method, when the temperature is high, the aC film is oxidized and becomes thin, and in the worst case, it disappears.

8- (2) By applying a resist process in the lithography technique, a resist film 1 having a thickness of, for example, 3000 [Å] having an opening 13A for forming a storage electrode contact hole is formed.
3 is formed.

See FIG. 9 9- (1) By applying the RIE method in which the etching gas is a mixed gas of (CF ₄ + CHF ₃ ), SiO in the uppermost layer is applied.
_An opening 17A is formed in the insulating film 17 made of ₂ .

See FIG. 10 10- (1) R using etching gas as (Cl ₂ + O ₂ ) mixed gas
By applying the IE method, the polycrystalline Si film 12 and a
The -C film 11 is etched at a substantially constant rate to form the storage electrode contact hole 14 reaching the interlayer insulating film 3.

In the process of performing this etching, the resist film 13 is completely etched, and S
The insulating film 17 made of iO ₂ functions as a mask.

11- (1) By applying the RIE method using a mixed gas of (CF ₄ + CHF ₃ ) as an etching gas, the interlayer insulating film 3 made of SiO ₂ is etched to contact the storage electrode.・
The hole 14 is extended and penetrated, and the insulating film 17 made of SiO ₂ is removed.

As a result, a part of the surface of the Si semiconductor substrate 1 is exposed in the storage electrode contact hole 14.

11- (2) After this, the memory is completed through the same steps as in the first embodiment.

In the case where the number of fins in the storage electrode is five, the etching process is required 9 times in the conventional technique, but in the second embodiment, it is only required to be 3 times.

FIG. 12 is a sectional view of an essential part of an integrated circuit device at a process step for explaining the third embodiment of the present invention, which will be described below in detail with reference to this figure. The same symbols as those used in FIGS. 1 to 11 represent the same parts or have the same meanings. Now, in the second embodiment described above described, after forming the a-C film 11 of the uppermost layer, but with each other to form an insulating film 17 made of SiO _2, in this example, of SiO ₂ By applying the CVD method before the step of forming the insulating film 17
The feature is that a polycrystalline Si film 18 having a thickness of, for example, 100 [Å] is formed.

In this way, when the interlayer insulating film 3 and the insulating film 17 made of SiO ₂ are etched, the uppermost aC film 11 is not reduced, and the storage electrode contact hole 14 is formed. If a polycrystalline Si film to be grown after that, that is, the first embodiment is borrowed, the back surface of the polycrystalline Si film forming the fin 12C and the trunk portion 12CX overlapping with the uppermost a-C film 11 becomes smooth. At the same time, the gap with the fin 12B is kept constant.

In this case, the uppermost polycrystalline Si film 18 is
The portion remaining after the completion of the storage electrode contact hole 14 is the fin 1 of the polycrystalline Si film formed thereafter.
It will overlap with 2C. The method of forming the polycrystalline Si film 18 in the third embodiment can be considered to be the same in the first embodiment.

Now, a fourth embodiment of the present invention will be described.

(1) In the first embodiment, when the storage electrode contact hole 14 is formed, the resist film 13 made of a generally used material is used as the etching master. As a resist film replacing the film 13, a Si-containing resist film having a thickness of, for example, 1500 [Å] having an opening for forming a storage electrode contact hole is formed.

(2) Next, etching gas (Cl
₂ + O ₂ ) mixed gas is used to apply polycrystalline Si film 1 using Si-containing resist film as a mask.
2 and the aC film 11 are etched at substantially the same rate to form the storage electrode contact hole 14 reaching the interlayer insulating film 3.

In this case, the Si-containing resist film is deteriorated at the same time as the film is reduced. Even if a little over-etching is performed, the underlying interlayer insulating film 3 made of SiO ₂ is hardly affected.

(3) Next, etching gas (CF
₄ + CHF ₃ ) mixed gas is used to etch the interlayer insulating film 3 made of SiO ₂ exposed in the storage electrode contact hole 14 to extend the storage electrode contact hole 14. Then, the altered Si-containing resist film is removed.

According to the fourth embodiment, the polycrystalline Si film 1
2 and the aC film 11 are etched, the Si-containing resist film is altered because the CHO which is a resist material is oxidized and volatilized, and the remaining Si is oxidized to become SiO ₂ , and therefore SiO _{2 is changed} from SiO _2. It can be removed simultaneously with the etching of the inter-layer insulating film 3 to be formed.

Although the Si-containing resist film is used in the fourth embodiment, the bi-level (bi-le) method utilizing the selective silylation is used.
vel method 2 A tri-level method using SOG (spin on glass) as an intermediate layer can be applied to obtain similarly good results. That is, in any of 1 and 2, the pattern forming resist film in the lithography technique can be thinned,
In addition, since the lower resist film has an altered layer or an intermediate layer having a property similar to that of SiO _2, it has resistance to etching of the laminated film and is altered in the process of etching the base insulating film to open the electrode contact hole. The layer or the intermediate layer can be removed.

Similarly, a fine pattern can be easily formed by applying a tri-level method and patterning a thin resist film when patterning the storage electrode. In this case, since the SOG film as the intermediate layer needs to be removed with hydrofluoric acid after etching the laminated film, the surface of the underlying interlayer insulating film needs to be SiN. For the patterning of the storage electrode, the Si-containing resist film or the bi-level method based on selective silylation requires the dry etching method in which SiO ₂ and SiN are easily etched when the resist film is removed. , Can not be adopted.

FIG. 13 is a sectional view of an essential part of an integrated circuit device at a process step for explaining the fifth embodiment of the present invention, which will be described in detail below with reference to this figure. The same symbols as those used in FIGS. 1 to 12 represent the same parts or have the same meanings.

In the first embodiment, after the storage electrode contact hole 14 is formed, the uppermost fin 12C and the polycrystalline Si film to be the trunk 12CX are formed, and then the storage electrode-shaped resist film is formed. 15 to form polycrystalline S
The laminate of the i film 12 and the aC film 11 is patterned into the shape of the storage electrode. In this embodiment, the CVD method is applied before the resist film 15 having the shape of the storage electrode is applied. SiN film 19 having a thickness of, for example, 500 [Å]
Is characterized by forming.

After that, a resist film 15 having a storage electrode shape is formed, and then an etching gas (CF ₄ + CH 2) is used.
By applying the plasma etching method using F ₃ ) mixed gas, patterning the SiN film 19, and then applying the RIE method using the etching gas as (Cl ₂ + O ₂ ) mixed gas. , Polycrystalline Si film 12
And a-C film 11 are etched at a substantially constant rate and patterned into a storage electrode shape, thereby forming a trunk portion 12CX.
Fins 12a, 12b, 1 shaped like dendritic branches from the
2c is formed.

In this case, the storage electrode-shaped resist film 15 is formed.
If the thickness is about 0.3 [μm], the resist film 15 is completely removed by etching when the above-mentioned constant rate etching is performed, and the SiN film 19 functions as an etching mask during the etching process. To do.

Thereafter, if necessary, the resist remaining in the storage electrode contact hole 14 is removed, the SiN film 19 is removed by hot phosphoric acid, and further O ₂ plasma or UV / O ₃ is used. By using O ₂ radicals, the aC film 11 existing between the interlayer insulating film 3 and the fin 12A, between the fins 12A and 12B, and between the fins 12B and 12C is removed to form a fin structure stacked capacitor. A storage electrode 16 having three fins 12A to 12C for forming is obtained.

In comparison with the first embodiment, the fifth embodiment can use an ordinary single-layer resist film with a relatively thin thickness.
Therefore, it is needless to say that a fine pattern can be easily formed, and the accuracy of pattern transfer, which is a problem in the tri-level method, is eliminated as compared with the fourth embodiment. However, although the steps of growing and removing the SiN film are increased, there is an advantage in that the increase in the number of steps is smaller than that in the sixth embodiment described below. It is unavoidable that the Si film is slightly etched in the step of removing the SiN film.

FIGS. 14 to 16 are sectional views of an essential part of the integrated circuit device in the process steps for explaining the sixth embodiment of the present invention, which will be described below in detail with reference to these figures. Explained. The same symbols as those used in FIGS. 1 to 13 represent the same parts or have the same meanings, and in the present embodiment, they are surrounded by the field insulating film 2 on the Si semiconductor substrate 1. A transfer transistor typified by a gate electrode acting as a word line WL and a bit line BL are formed in the active region, and the surface has an S thickness of, for example, 200 [Å].
It assumed to be covered with an interlayer insulating film 3 made of iO _2.

See FIG. 14 14- (1) By applying the CVD method, the thickness is, for example, 300.
The SiN film 20 of [Å] is formed.

14- (2) Here, the laminated body composed of the aC film 11 and the polycrystalline Si film 12 is formed in multiple layers. The steps are the same as those described with reference to FIGS. 1 to 7. It is exactly the same as the embodiment. If necessary, similar to the first embodiment, the polycrystalline S is formed on the uppermost layer.
An i film may be formed.

14- (3) By taking the same steps as in the first embodiment, the storage electrode contact
The hole 14 is formed. The difference from the first embodiment is that the SiN film 20 is present in the middle, which is an etching gas for SiO ₂ (C
It goes without saying that the etching is performed by the F ₄ + CHF ₃ pole).

See FIG. 15 15- (1) Using the same steps as in the first embodiment, a polycrystalline Si film having a thickness of 300 [Å] to be the uppermost fins and trunks is formed, and then, By applying the CVD method,
A SiO ₂ film 21 having a thickness of, for example, 500 [Å] is formed.

15- (2) By using the same steps as in the first embodiment, the resist film 15 in the shape of the storage electrode is formed.

15- (3) By applying the plasma etching method in which the etching gas is a (CF ₄ + CHF ₃ ) mixed gas, Si
After patterning the O ₂ film 21, etching /
Polycrystalline Si film 12 and a-C film 11 are patterned into a storage electrode shape by applying a plasma etching method using a gas of (Cl ₂ + O ₂ ) mixed gas. Formed fins 12, 12B, 12C extending in a dendritic form from the trunk portion 12CX.

In this case, the storage electrode-shaped resist film 15 is formed.
If the thickness is about 0.3 [μm], it is completely removed during the etching, and the SiO ₂ film 21
Acts as a mask.

Due to the step of the base, for example, 1200
Even if [Å] of about over-etching is required, since the etching rate of the SiO ₂ film 21 and the SiN film 20 may be 1/6 or less, in this case, the SiO ₂ film 21 is a mask also underlying The SiN film 20 as described above can be reduced by about 200 [Å], and sufficient protection can be performed depending on the residual amount.

See FIG. 16 16- (1) By immersing in a hydrofluoric acid solution, the SiO ₂ film 2 is formed.
1 is removed, and then the same steps as those in the first embodiment are taken, whereby the space between the SiN film 20 and the fin 12A, the fin 12A
And the fin 12B, and between the fins 12B and 12C, the aC film 11 is removed to complete the storage electrode 16. The interlayer insulating film 3 is never damaged in this step due to the presence of the SiN film 20.

In the sixth embodiment, compared with the first embodiment, a normal single layer resist film can be used by making it relatively thin, and therefore, it is easy to form a fine pattern, and
As compared with the fourth embodiment, it goes without saying that the decrease in the accuracy of pattern transfer, which is a problem in the tri-level method, is eliminated.
However, the step of growing the SiN film on the underlying interlayer insulating film,
The number of steps for growing and removing the SiO ₂ film is increased.

The above sectional view corresponds to the sectional view taken along the line CC of FIG. In FIG. 17, WL1-WL4 indicate word lines, and BL1a, BL1b, BL2a indicate bit lines. Further, CBL indicates a contact between the bit line and the diffusion region DR, and CSE indicates a contact between the storage electrode and the diffusion region DR.

Next, a seventh embodiment of the present invention will be described. In the seventh embodiment, in a laminated body of a polycrystalline Si film and an aC film, a sidewall for connecting a plurality of polycrystalline Si films is provided in a hole that is sufficiently smaller than a value determined by a photolithography technique. Characterize. The seventh embodiment will be described below with reference to FIGS. 18 to 25. 18 to 25 correspond to the sectional view taken along the line AA in FIG.

As shown in FIG. 18, Si semiconductor substrate 21
The field insulating film 22 is formed thereon by, for example, the LOCOS method. Next, the gate oxide film 22a is formed by the thermal oxidation method. Then, by ion implantation, diffusion regions serving as a source and a drain are formed.

Next, as shown in FIG. 19, S is formed by the CVD method.
After forming the oxide film 23 of iO _2, a bit line contact hole (not shown) is selectively formed. Then CVD
Then, polycrystalline Si is formed on the entire surface by the method and patterned to form the bit line BL. Then, an oxide film 24 of SiO ₂ is formed on the entire surface by the CVD method.

Next, as shown in FIG. 20, the aC film 25 and the polycrystalline Si film 26 are alternately laminated by the PCVD method and the CVD method as described above a plurality of times, and then the above-mentioned RIE is performed.
The storage electrode contact hole 27 is opened by using the method. However, at this stage, the storage electrode contact hole 27 is not yet completed. As described above, by using a mixed gas of Cl ₂ + O ₂ in this RIE method, the selection ratio with respect to the oxide film 24 can be made sufficiently large. In addition, in FIG. 20, in order to explain the effect of the seventh embodiment, the storage electrode contact hole 27 which is intentionally displaced is shown.

Next, as shown in FIG. 21, a polycrystalline Si film is formed on the entire surface by the CVD method, and RI using HBr / He is formed.
By the E method, the polycrystalline Si film is anisotropically etched (vertical etching) to leave the side wall 28 of polycrystalline Si on the side wall of the storage electrode contact hole 27, and a new opening 27 is formed.
Form A. HBr / He has a sufficiently large selection ratio with respect to the aC film 25. The thickness of the remaining side wall 28 is, for example, about 0.2 μm.

Next, as shown in FIG. 22, SiO ₂ was formed by RIE using CHF3 / He as a reactive gas.
The oxide films 22a, 23, 24 made of are removed to form an opening 29 exposing the diffusion layer. CHF3 / He is
The selection ratio is sufficiently large for both the aC film 25 and the polycrystalline Si film 26.

Next, as shown in FIG. 23, a polycrystalline Si film 31 is formed on the entire surface by a CVD method, and then a resist film as shown in FIG. 5 is formed. In this state, Cl ₂ / O ₂
AC film 25 and polycrystalline Si by the RIE method using
The film 26 is patterned at one time (using one mask). Cl ₂ / O ₂ is used for the aC film 25 and polycrystalline Si.
The selectivity is sufficiently high for any of the membranes 26.

After that, the resist film used in the patterning process is removed. For this treatment, as described later, it is preferable to perform removal of the resist film 15 by ashing (preferably downflow ashing), HF-based wet treatment, and boiling of persulfate.

The subsequent steps are the same as those described in the first embodiment. That is, O ₂ plasma, O ₂ plasma downflow or UV (ultrav)
between the interlayer insulating film (oxide film) 24 and the fin-shaped polycrystalline Si film (fin) 26 using oxygen radicals due to (iolet) / O ₃ between the fin 26 and the fin-shaped polycrystalline Si film (fin) 3
The aC film 25 existing between 1 and 1 is removed. The fin 31 contacts the diffusion region and constitutes the uppermost layer of the storage electrode of the capacitor.

Then, as shown in FIG. 24, the dielectric film 3
2, the formation of the counter electrode 33, the formation of the BPSG film 34, the formation of the word line backing electrode 35, the formation of the oxide film 36, and the formation of the column selection line 37 are performed.

According to the seventh embodiment of the present invention described above, in addition to the effects of the above-described embodiment, fine through holes exceeding the limit of the photolithography technique can be formed with good reproducibility, and the semiconductor memory device Contributes to high integration.

Further, there is no problem even if the opening 27 shown in FIG. 20 is misaligned, and the reliability of the semiconductor memory device is dramatically improved. Here, FIG.
FIG. 24 shows a cross section of the apparatus when the processing described with reference to FIG. As shown in FIG. 25, when the storage electrode pattern is misaligned, the polycrystalline Si film 26 on the right side of the drawing, and the side wall 28 and part of the polycrystalline Si film 31 are removed by etching. However, there are no problems such as the exposure of the diffusion region described later. This is because the fin formation process described with reference to FIG.
This is because the oxide film will not be damaged when the oxide is removed. Moreover, since the RIE method using Cl ₂ / O ₂ has a sufficiently large selection ratio with respect to the oxide film, the oxide film is not damaged when the storage electrode is etched.

Hereinafter, this point will be described in detail in comparison with the problems caused by the conventional manufacturing process.

FIG. 26 is a diagram showing a method of manufacturing a conventional semiconductor device having a fin type capacitor. 26A shows the semiconductor substrate 41, the oxide films 42 and 43, the nitride film 44, the oxide film 46 of SiO ₂ , the polycrystalline Si films 47 and 4.
9 and 50, a step of forming a resist film 51 with the sidewalls 48 formed and etching the polycrystalline Si films 49 and 50 is shown. Here, conventionally, the film interposed between the polycrystalline Si films is an oxide film, and in order to obtain a large selection ratio with respect to the oxide film by the wet etching treatment performed when removing this oxide film, the nitriding is performed. The membrane 44 is used.

As is well known, in order to completely remove the stepped portion such as the bit line, it is necessary to excessively perform overetching. Here, as shown in FIG. 26A, when the resist film 51 is in a state of protruding from the opening, the exposed polycrystalline Si film is removed. And in FIG.
Oxide film etching step (CHF3 / He
RIE method), the nitride film 44 is also etched. When this etching is excessive, the oxide film 43 is also partially or completely etched in the thickness direction, and the surface of the substrate 41 is exposed.

In FIG. 27C, the polycrystalline Si film 47 is further etched. Then, FIG. 27 (D)
As shown in, the oxide film 46 is removed in an HF solution (wet process). At this time, the nitride film 44 is necessary to protect the surface of the substrate 41. In the removal of the oxide film 46, the nitride film 44 and the oxide film 43 are etched in (B) and (C), so that the oxide film 43 is isotropically removed from the exposed portion and the cavity 53 is formed. Will end up. In other words, the structure shown in FIG. 27D in which the film 44 is made of silicon oxide cannot be formed by the conventional manufacturing method.

On the other hand, according to the seventh embodiment, as shown in FIG.
As described with reference to FIG. 1, the laminated film of the aC film and the Si film is simultaneously Cl ₂ / O ₂ , and the polycrystalline Si film alone is HBr.
/ He, SiO ₂ film alone CHF ₃ / He, a-C
Since the isotropic etching of the film is performed by oxygen plasma, it is possible to perform etching with a sufficient selection ratio with respect to each other, and there is no problem as shown in FIG.

Next, an eighth embodiment of the present invention will be described. The eighth embodiment is intended to achieve high integration by forming holes that are sufficiently smaller than the value determined by the photolithography technique in the laminated body of the polycrystalline Si film and the aC film. The eighth embodiment will be described below with reference to FIGS. 28 to 35. 28 to 35 are A- in FIG.
It corresponds to a sectional view taken along line A.

As shown in FIG. 28, a Si semiconductor substrate 51.
A field insulating film 52 is formed on top by, for example, the LOCOS method. Next, the gate oxide film 52a is formed by the thermal oxidation method. Then, by ion implantation, diffusion regions serving as a source and a drain are formed.

Next, as shown in FIG. 29, S is formed by the CVD method.
After forming the oxide film 53 of iO _2, a bit line contact hole (not shown) is selectively formed. Then CVD
Then, polycrystalline Si is formed on the entire surface by the method and patterned to form the bit line BL. Then, an oxide film 54 of SiO ₂ is formed on the entire surface by the CVD method.

Next, as shown in FIG. 30, the aC film 56 and the polycrystalline Si film 57 are alternately laminated by the PCVD method and the CVD method as described above a plurality of times, and then SF ₆ / O _{2 is} added.
In a plasma containing -60 ° C,
The aC film 56 and the polycrystalline Si film 57 are simultaneously etched using one mask. In this step, the substrate 51 is set to −6.
As shown in FIG. 30, the taper-shaped opening 5 whose side surface is narrowed toward the diffusion region is performed at a low temperature (about 0 ° C.).
5 is formed. As a result, the frontage can be reduced by about 0.05 μm from the value determined by the photolithography technique.

Next, as shown in FIG. 31, CHF ₃ / C
By the RIE method using F ₄ / Ar, the oxide films 52a, 53, 54 are removed by using the resist film 58 and the laminated body as a mask to expose the diffusion region. In this case, if the flow rate of Ar is smaller than that of CHF ₃ , the oxide films 52a, 53,
As shown in FIG. 31, 54 is a tapered opening whose side surface is narrowed in the diffusion region direction. As a result, the aperture has an opening
It is further reduced by about 05 μm, and a contact hole in the shape of a pleat is formed which is about 0.1 μm smaller than the value determined by the photolithography technique as a whole.

After that, the resist film 58 is removed with sulfuric acid. An altered layer formed by being exposed by the RIE process is formed on the resist 58. This deteriorated layer has ashing (downflow ashing) described later,
By performing HF wet treatment and boiled persulfate,
It is possible to prevent receding of the aC film 56 exposed in the opening 55 and obtain a better processed shape.

Next, as shown in FIG. 32, after a polycrystalline Si film 60 is formed on the entire surface by the CVD method, a resist film 59 is formed.
To form. The polycrystalline Si film 60 includes a portion having a substantially V-shaped cross section. Note that, in FIG. 32, the pattern of the resist film 59 is displaced. Then, the aC film 5 is formed by the RIE method using Cl ₂ / O ₂ or SF ₆ / O _2.
6 and the polycrystalline Si films 57 and 60 are simultaneously etched. A-C film 56 and polycrystalline Si film 57 for SiO ₂
And the selection ratio with 60 is sufficiently large. In addition, polycrystalline Si
If the film 60 is slightly larger than the contact hole,
The problem as shown in FIG. 26 does not occur.

Next, as shown in FIG. 33, the resist film 59 and the aC film 56 are simultaneously removed by oxygen plasma.

Then, as shown in FIGS. 34 and 35, a nitride film 61 is formed around the storage electrode formed of the patterned polycrystalline Si films 57 and 60, and the polycrystalline S film is formed.
A counter electrode 62 made of i is formed on the entire surface. Then B
A PSG film 63 is formed on the entire surface, and an Al word line 64 is formed as shown in the figure. Incidentally, FIG. 34 shows AA of FIG.
FIG. 35 is a sectional view taken along the line C-C in FIG. 17.

As described above, according to the eighth embodiment of the present invention, there is an advantage that the contact hole has a tapered shape and the size of the bottom portion thereof can be smaller than the limit value of the photolithography technique.

As described above, the removal of the resist film (including the altered layer) used for forming the contact hole of the storage electrode of the capacitor and the removal of the resist film used for patterning the storage electrode are performed by ashing (preferably , Downflow ashing), HF-based wet treatment, and boiled persulfate are preferably performed.

FIG. 36 is a diagram showing a downflow type ashing device. The illustrated ashing device has a light emitting chamber 73, a reaction chamber 74, a shower head member (punching board) 75, and an exhaust pump 78 for exhausting air from a lower portion of the reaction chamber 74. A quartz window 76 is provided above the light emitting chamber 73, and μ waves are applied to the upper portion thereof. The μ wave generator for generating μ waves is not shown.
Plasma 71 is generated in the light emitting chamber 73. And
By the action of the exhaust pump 78, the light emitting chamber 73 is changed to the reaction chamber 7
4, downflow of neutral radicals occurs. At this time, the charged particles are trapped by the punching board 75. This down flow ashes the wafer (resist film) on the stage 77 provided in the reaction chamber 74.

The reaction chamber 74 contains O ₂ gas or CF ₄ gas.
A mixed gas of / O ₂ (for example, containing 8% CF ₄ ) is provided. As an example, the pressure in the reaction chamber 74 is 90
At 0 mTorr, the frequency of the μ wave is 2.45 GHz, and the power is 1 KW. Under this condition, about 12000-150
The resist film can be removed at an ashing rate of 00 [Å / min]. In this process, the etching rate of the aC film exposed to plasma is 30 [Å], and the aC film hardly recedes. For reference, plasma ashing using O ₂ gas produces about 880 [Å /
Minutes].

Most of the resist film can be removed by the downflow ashing, but preferably the resist film can be completely removed by subsequently performing the HF-based wet treatment and the persulfate boil treatment. In the HF-based wet process, the wafer is dipped in a 0.5% HF solution for about 10 seconds. Also, in the persulfate boil treatment, a stripping solution having a temperature of 130 ° C., which is a mixture of concentrated sulfuric acid and hydrogen peroxide at a ratio of 100: 1, is used for about 10 minutes.

Downflow ashing, H described above
The resist film can be removed by the F-based wet process and the process of boiling persulfate without retreating the aC film.

Incidentally, in the patterning of the storage electrode in the prior art, since it is formed in the gap layer of SiO ₂ , the HF-based wet treatment for retreating the gap layer is indispensable, but the dry treatment after the wet treatment is necessary. In this case, the problem that the fin layer is plastically deformed by the surface tension action of the moisture remaining in the gap layer does not occur in the above method.

The downflow ashing can be applied to the method of manufacturing the semiconductor device shown in FIGS. 37 to 40 show a manufacturing process in which the aC film is used as an antireflection film in a photolithography process.

Referring to FIG. 37, an oxide film 82 including a gate oxide film and an element isolation oxide film is formed on a semiconductor substrate 81, and a film to be processed (eg, WSi / polycrystalline Si) is formed on the oxide film 82.
A film) 83 is formed. A on the film to be processed 83
A -C film 84 is formed, and a resist film 85 is formed thereon.

In this state, the resist film 85 is patterned as shown in FIG. Then, it is inspected whether or not the resist pattern 85 is located within an allowable range. If it is determined that the film is located within the allowable range, the film 83 to be processed is patterned by etching, as shown in FIG. Then, as shown in FIG. 40, the resist film 85 and the aC film 84 are removed.

In the above inspection, when it is determined that the patterned resist film 85 is located outside the allowable range, the resist film 85 is removed by the downflow ashing described above. In this process, the aC film 84 is not peeled off. The resist film 85 can be completely removed by subsequently performing the HF-based wet treatment and the persulfate boil treatment. .

Then, as shown in FIG. 37, the resist film 8
After applying 5 to the entire surface again, patterning is performed as shown in FIG.

A batch type ashing device as shown in FIG. 41 may be used. This ashing device 9
5 accommodates a plurality of wafers in a reaction chamber 92 and has an inlet 94.
The reaction gas is introduced from the above and exhausted from the outlet 93. Also,
The μ wave from the μ wave generator 96 is applied to the reaction chamber 92.

The present invention is not limited to the above embodiments,
Many modifications can be made, a few examples are given below.

A (Cl ₂ + O ₂ ) mixed gas was used in anisotropically etching the laminated body of the polycrystalline Si film and the aC film at a constant rate. BC as gas containing gas, for example Cl
l ₃ and SiCL ₄ can be used, and O ₂
N ₂ O, CO ₂ or the like can also be used as the gas containing. If the substrate is cooled during etching,
Anisotropic etching can be performed with F and O, and SF ₆ and NF ₃ can be used as the gas containing F.

Although the CVD method using C ₂ H ₂ as a raw material has been mentioned for forming the aC film, it may be formed by a CVD method using other hydrocarbon as a raw material gas or by sputtering. It is also possible to film.

Even if amorphous Si is used instead of polycrystalline Si, good results can be obtained. In any case, the doping step can be omitted by using P-containing polycrystalline Si or P-containing amorphous Si. Needless to say.

As an etching gas for plasma etching SiO ₂ or SiN, (CF ₄ + CH
F ₃ ) mixed gas has been exemplified, but for example, C ₂ F ₆ , (CF
A gas such as ₄ + CH ₂ F ₂ ) or (C ₄ F ₈ + CH ₂ F ₂ ) can be used.

Although the RIE method has been exemplified as the etching technique, ECR (electron cyclotron) is used.
Good results can also be obtained by applying a magnetic field etching method such as resonance).

For pattern formation, EB (electron)
In the case of using the beam exposure, the photoresist is, of course, PMMA (polymethylmeth).
Acrylate) and PMSS (polymethyl)
An electron beam resist such as silsesquioxane) will be used, but in any case, a thick resist mask can be used by utilizing a multilayer resist method if necessary.

The film thickness and the number of fins in the storage electrode can be designed according to the requirements for the device characteristics of the integrated circuit device, and the combination of the etching conditions should be appropriately selected within the scope of the present disclosure. Is easy.

In the embodiment, the gap layer is a-
Although the C film is used, the present invention is not limited to this, and any material such as polyimide, which has heat resistance and has a selective ratio with the oxide film, may be used.

[0145]

In the method of manufacturing an integrated circuit device according to the present invention, the insulating film covering the surface of the substrate is formed, and then the laminated body including the amorphous carbon film and the Si film is formed, and the laminated body is used as the substrate. A part of the storage electrode contact hole is formed by etching under the condition that a selection ratio with the insulating film covering the surface can be obtained, and the insulating film covering the surface of the substrate is etched to extend and penetrate the storage electrode contact hole to form a substrate. A Si film is formed on the surface including the inside of the storage electrode contact hole, and the Si film formed on the surface including the inside of the storage electrode contact hole and the laminate are patterned into a storage electrode shape. After removing the amorphous carbon film, S in the storage electrode contact hole
Complete a storage electrode with Si fins that dendriticly extend from the trunk of i.

As described above, in the present invention, the SiO ₂ film is used instead of the SiO ₂ film in order to form the inter-fin gap of the storage electrode made of the Si film such as the polycrystalline Si film or the amorphous Si film in the fin structure stacked capacitor. When an amorphous carbon film is used as the Si film and the Si film and the amorphous carbon film are etched at a substantially constant rate, anisotropic etching is performed to obtain SiO ₂ or S.
Taking advantage of the fact that an etching selection ratio with an insulating film such as iN can be taken, the number of steps obtained by subtracting 2 from four times the number of fins in the conventional technique, for example, if the number of fins is five Although eighteen steps are required, basically only three steps can be completed, so that the manufacturing yield and reliability of this type of integrated circuit device are greatly improved.

Further, in order to remove the amorphous carbon film which is the spacer film interposed between the fins, it is not necessary to use a chemical solution such as hydrofluoric acid, and when the amorphous carbon film is slightly removed, When the SiO ₂ film is formed on the Si film that is the fin, it is used only for removing it if necessary, so the etching amount due to it is extremely small, and even if a defect occurs in the structure, Even if hydrofluoric acid or the like enters from there, there is no possibility that a portion that greatly affects the electrical characteristics will be destroyed and a defective portion (defective bit) will be generated, and furthermore, the fin may be curved. In this respect, the manufacturing yield and reliability of the integrated circuit device are greatly improved.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of an integrated circuit device in a process main part for explaining a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of an essential part of the integrated circuit device in a process key point for explaining the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of an essential part of the integrated circuit device in a process main part for explaining the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of an essential part of the integrated circuit device at a process key point for explaining the first embodiment of the present invention.

FIG. 5 is a cross-sectional view of an essential part of the integrated circuit device in a process essential part for explaining the first embodiment of the present invention.

FIG. 6 is a cross-sectional view of an essential part of the integrated circuit device at a process essential part for explaining the first embodiment of the present invention.

FIG. 7 is a cross-sectional view of an essential part of the integrated circuit device in a process main part for explaining the first embodiment of the present invention.

FIG. 8 is a sectional view of an essential part of an integrated circuit device in a process essential part for explaining a second embodiment of the present invention.

FIG. 9 is a cross-sectional view of a main part of an integrated circuit device in a process main part for explaining a second embodiment of the present invention.

FIG. 10 is a cross-sectional view of an essential part of the integrated circuit device in a process essential part for explaining the second embodiment of the present invention.

FIG. 11 is a cross-sectional view of an essential part of the integrated circuit device in a process essential part for explaining the second embodiment of the present invention.

FIG. 12 is a sectional view of an essential part of an integrated circuit device in a process essential part for explaining a third embodiment of the present invention.

FIG. 13 is a fragmentary cross-sectional view of an integrated circuit device at a process essential part for explaining a fifth embodiment of the present invention.

FIG. 14 is a cross-sectional view of an essential part of the integrated circuit device in a process essential part for explaining the sixth embodiment of the present invention.

FIG. 15 is a sectional view of an essential part of an integrated circuit device in a process essential part for explaining a sixth embodiment of the present invention.

FIG. 16 is a fragmentary cross-sectional view of an integrated circuit device in a process essential part for explaining a sixth embodiment of the present invention.

FIG. 17 is a plan view of an integrated circuit device according to each embodiment of the present invention.

FIG. 18 is a cross-sectional view of the essential parts of the integrated circuit device in the process key point for explaining the seventh embodiment of the present invention.

FIG. 19 is a cross-sectional view of essential parts of the integrated circuit device in a process essential part for explaining the seventh embodiment of the present invention.

FIG. 20 is a fragmentary cross-sectional view of the integrated circuit device at a process essential point for explaining the seventh embodiment of the present invention.

FIG. 21 is a fragmentary cross-sectional view of the integrated circuit device at a process essential point for explaining the seventh embodiment of the present invention.

FIG. 22 is a fragmentary cross-sectional view of the integrated circuit device at a process essential point for explaining the seventh embodiment of the present invention.

FIG. 23 is a fragmentary cross-sectional view of an integrated circuit device in a process essential part for explaining a seventh embodiment of the present invention.

FIG. 24 is a fragmentary cross-sectional view of an integrated circuit device manufactured according to a seventh embodiment of the present invention.

FIG. 25 is a fragmentary cross-sectional view of an integrated circuit device for explaining that there is no problem even if the resist film is displaced in the seventh embodiment of the present invention.

FIG. 26 is a fragmentary cross-sectional view showing the conventional method for manufacturing an integrated circuit device, which is related to the seventh embodiment of the present invention.

FIG. 27 is a main-portion cross-sectional view showing the conventional method for manufacturing an integrated circuit device, which is related to the seventh embodiment of the present invention.

FIG. 28 is a fragmentary cross-sectional view of the integrated circuit device at a process essential point for explaining the eighth embodiment of the present invention.

FIG. 29 is a fragmentary cross-sectional view of the integrated circuit device at a process essential point for explaining the eighth embodiment of the present invention.

FIG. 30 is a fragmentary cross-sectional view of an integrated circuit device in a process essential part for explaining an eighth embodiment of the present invention.

FIG. 31 is a fragmentary cross-sectional view of the integrated circuit device at a process essential point for explaining the eighth embodiment of the present invention.

FIG. 32 is a fragmentary cross-sectional view of the integrated circuit device at a process essential point for explaining the eighth embodiment of the present invention.

FIG. 33 is a sectional view of an essential part of an integrated circuit device in a process essential part for explaining an eighth embodiment of the present invention.

FIG. 34 is a fragmentary cross-sectional view of an integrated circuit device manufactured according to an eighth embodiment of the present invention.

FIG. 35 is a fragmentary cross-sectional view of an integrated circuit device manufactured according to an eighth embodiment of the present invention.

FIG. 36 is a view showing a downflow type ashing device used in each embodiment of the present invention.

37 is a fragmentary cross-sectional view showing the pattern forming method using the downflow type ashing device of FIG. 37; FIG.

38 is a fragmentary cross-sectional view showing the pattern forming method using the downflow type ashing device of FIG. 37; FIG.

39 is a sectional view of a key portion showing the pattern forming method using the downflow type ashing device of FIG. 37. FIG.

FIG. 40 is a sectional view of a key portion showing the pattern forming method using the downflow type ashing device of FIG. 37.

FIG. 41 is a view showing a batch type ashing device.

[Explanation of Codes] 1 Si semiconductor substrate 2 Field insulating film 3 Interlayer insulating film 3A Film reduction WL Word line BL Bit line 11 a-C film 12 Polycrystalline Si film 12A Fin 12B Fin 12C Fin 12CX Core part 13 Resist film 13A Opening 14 Storage Electrode Contact Hole 15 Resist Film 16 Storage Electrode 17 Insulating Film 17A Opening 18 Polycrystalline Si Film 19 SiN Film 20 SiN Film 21 SiO ₂ Film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hisashi Miyazawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Kazushi Kawaguchi, 1015, Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture Fujitsu Limited ( 72) Inventor Koichi Hashimoto 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Toshiyuki Otsuka 1015, Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor, Shinfuku Fumihiko Kanagawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki Prefecture, Japan Within Fujitsu Limited

Claims (13)

[Claims] 1. A first method for forming a laminated body including a gap film and a Si film after forming an insulating film covering a surface of a substrate.
And the step of forming an opening which is a part of the storage electrode contact hole in the stacked body including the Si film and the gap film.
And a third step of etching an insulating film covering the surface of the substrate through the opening to form a storage electrode contact hole exposing a part of the substrate, and the storage electrode contact.・ Si on the surface including holes
A fourth step of forming a film; patterning the Si film and the laminated body formed on the surface including the inside of the storage electrode contact hole into a storage electrode shape, and then removing the gap film to form the storage electrode And a fifth step of completing a storage electrode having a Si fin extending in a dendritic form from the Si trunk in the contact hole. 2. Between the second step and the third step,
Si is formed on the inner side surface of the opening formed in the second step.
2. The method of manufacturing an integrated circuit device according to claim 1, further comprising the step of forming a sidewall including the. 3. The second step has an etching condition for forming the opening in a mortar shape, and the third step has an etching condition for forming the insulating film in a mortar shape. Item 1. A method of manufacturing an integrated circuit device according to item 1. 4. The method according to claim 2, wherein the third step includes a step of removing the resist film used for forming the storage electrode contact hole by downflow ashing containing oxygen gas. Manufacturing method of integrated circuit device. 5. The fifth step is a step of removing the resist film used for the patterning by downflow ashing containing oxygen gas, and then at least an HF-based wet treatment or a persulfate boil treatment. The method of manufacturing an integrated circuit device according to claim 1, further comprising a step of performing the step and a step of removing the gap layer. 6. The second and / or the fifth step are C
The method of manufacturing an integrated circuit device according to claim 1, further comprising an anisotropic etching step using a mixed gas of l ₂ and O ₂ . 7. A laminated film is formed in advance before forming a resist film having a storage electrode contact hole forming opening, the Si film being integrated with a Si film formed later on the surface including the inside of the storage electrode contact hole. The method for manufacturing an integrated circuit device according to claim 1, further comprising: 8. The integrated circuit device according to claim 1, further comprising a step of forming an insulating film as a film as an uppermost layer before forming a resist film having an opening for forming a storage electrode contact hole. Production method. 9. The method according to claim 1, wherein the removal of the gap layer after patterning is carried out by using oxygen radicals.
Alternatively, a method of manufacturing an integrated circuit device according to claim 5, 6 or 7, or 8. 10. An insulating film formed on a substrate, and at least one first conductive film extending on the insulating film, spaced apart from each other, and having a first opening therein. A second conductive film formed along the inner side surface of the first opening and coupling the first conductive films to each other; and contacting the substrate through the second opening formed in the insulating film. And a third conductive film which is connected to the second conductive film and extends above the first conductive film with a space therebetween, and a dielectric covering the first, second and third conductive films. An integrated circuit device comprising: a film; and a fourth conductive film covering the dielectric film, wherein a surface portion of the insulating film facing the first conductive film contains silicon oxide. 11. An insulating film formed on a substrate, and at least one first conductive film extending on the insulating film and provided apart from each other and having a first opening therein. The first conductive film is formed along the inner side surface of the first opening, is coupled to the first conductive film, contacts the substrate through the second opening formed in the insulating film, and is electrically connected to the first conductive film. A second conductive film that extends above the film and is separated from the film; a dielectric film that covers the first and second conductive films; and a third conductive film that covers the dielectric film. The integrated circuit device according to claim 1, wherein the diameter of the second opening is in the shape of a skirt that increases with increasing distance from the substrate. 12. A first step of forming a patterned resist film on a gap film provided on a film to be processed, and a second step of removing the resist film by downflow ashing containing oxygen gas. A method of manufacturing an integrated circuit device, comprising: 13. The method of manufacturing an integrated circuit device according to claim 12, further comprising a third step of performing at least an HF-based wet treatment or a persulfate boil treatment after the second step.