KR20070001510A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to omit hard mask deposition and etching processes by using a sacrificial layer as an etching barrier to etch a dielectric. A conductive line is formed on a semiconductor substrate(21). A dielectric buries the conductive line. A sacrificial layer(24) and an anti-reflection layer are laminated on the whole surface of the resultant structure. A photoresist pattern(25) is formed on the anti-reflection layer. The anti-reflection layer and the sacrificial layer are etched by using the photoresist pattern as an etching barrier. An etching target of the sacrificial layer is controlled to remove the remained photoresist pattern. The dielectric is etched by using the sacrificial layer as an etching barrier to form a hole that opens a predetermined region of the semiconductor substrate. The remained sacrificial layer and the anti-reflection layer are removed.

Description

 Semiconductor device manufacturing method {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art;

2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 interlayer insulating film

23 amorphous carbon 24 sacrificial film

25: photoresist pattern 26: landing contact hole

TECHNICAL FIELD The present invention relates to semiconductor manufacturing techniques, and more particularly to a method of forming a landing plug contact.

Argon fluoride (ArF) 193 nm lithography processes for devices below 80 nm Technology add to the existing process concept the requirement to suppress photoresist deformation during etching. Accordingly, the development of process conditions for simultaneously satisfying existing requirements and pattern deformation from an etching point of view has become a major challenge. Due to these problems, patterning technology using hard masks has become commonplace, and the most important problem is how to select an economic hard mask. As a hard mask material, general materials such as polysilicon film and nitride film are recently considered as candidates for new materials such as amorphous carbon.

Meanwhile, in the process of forming a landing plug contact, the nitride film is generally hard masked.

However, since a nitride film hard mask is the most economical material but has a limitation in terms of photoresist margin, the conversion to new hard masks such as amorphous carbon and organic polymer hard masks is being studied in devices of 60 nm or less.

However, in the case of amorphous carbon, deposition of a silicon oxynitride (SiON) hard mask is required on top of the amorphous carbon during the process, and when the thickness of the amorphous carbon increases, a key open is used for subsequent alignment margin. The need for additional process has a big problem in terms of mass production. Silicon oxynitride is a material that acts as a hard mask in amorphous carbon patterning and has a large difference in selectivity when etching amorphous carbon.

Therefore, in order to etch amorphous carbon having a predetermined thickness or more, deposition and patterning of a silicon oxynitride hard mask is essential, and thus, the process is complicated.

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

As shown in FIG. 1A, an interlayer insulating film 12 is deposited on the semiconductor substrate 11. At this time, before the interlayer insulating film 12 is deposited, processes necessary for DRAM isolation such as device isolation and word lines are performed.

Alternatively, chemical mechanical polishing (CMP) is performed to stop on the gate to remove the interlayer insulating film on the gate, and then amorphous carbon is deposited on the exposed gate hard mask nitride film.

Meanwhile, the interlayer insulating film 12 may include a BSG (Boro-Silicate-Glass) film, a BPSG (Boro-Phospho-Silicate-Glass) film, a PSG (Phospho-Silicate-Glass) film, and a TEOS (Tetra-Ethyl-Ortho-Silicate) film. A film, an HDP (High Density Plasma) oxide film, a spin on glass (SOG) film, an advanced planarization layer (APL) film, or the like, or an inorganic or organic low dielectric constant film in addition to the oxide film is used.

Subsequently, 2000 Å to 4000 Å thick amorphous carbon 13 and 300 Å to 400 Å thick silicon oxynitride 14 are laminated on the interlayer insulating film 12.

Subsequently, an organic anti-reflection coating (15) is deposited on the silicon oxynitride 14, and a photoresist pattern 16 is formed on a predetermined region of the organic anti-reflection film 15.

As shown in FIG. 1B, the anti-reflection film 15a and the silicon oxynitride 14a are etched using the photoresist pattern 16 as an etch barrier.

As illustrated in FIG. 1C, a predetermined thickness of the amorphous carbon 13a is etched using the photoresist pattern 16 as an etching barrier. At this time, a portion of the thickness of the photoresist pattern 16a is lost while etching the amorphous carbon 13a.

As shown in FIG. 1D, the anti-reflection film 15a and the photoresist pattern 16a are stripped, and all of the amorphous carbon 13b having a predetermined thickness is etched using the etched silicon oxynitride 14a as an etch barrier. do. At this time, the predetermined thickness of the interlayer insulating film 12a is also etched.

As shown in FIG. 1E, after the amorphous carbon 13b is etched, the silicon oxynitride 14b is removed, and the interlayer insulating film is opened until the surface of the semiconductor substrate 11 is opened using the amorphous carbon 13b as an etch barrier. Etch (12b).

As shown in FIG. 1F, it can be seen that the landing contact hole 17 is formed, and the amorphous carbon 13b is removed to finish the LPC process.

As described above, the LPC mask process is performed after depositing the amorphous carbon, but when the 4000 의 thick amorphous carbon is used as the hard mask, a large problem occurs in the overlay margin, so that a separate key opening process is required when the mask is aligned. have.

The present invention has been proposed to solve the above problems of the prior art, and provides a semiconductor device manufacturing method suitable for forming a landing plug contact without depositing silicon oxynitride when amorphous carbon is applied as a hard mask. There is a purpose.

The semiconductor device manufacturing method of the present invention for achieving the above object is a step of forming a conductive line on a semiconductor substrate, embedding the conductive line with an insulating film, laminating a sacrificial film and an anti-reflection film on the entire surface of the resultant, Forming a photoresist pattern on the anti-reflection film, etching the anti-reflection film and the sacrificial film using the photoresist pattern as an etching barrier, removing the remaining photoresist pattern by adjusting an etch target of the sacrificial film, Etching the insulating layer using the sacrificial layer as an etch barrier to form a hole for opening a predetermined region of the semiconductor substrate, and removing the remaining sacrificial layer and the anti-reflective layer.

As described above, in the present invention, the sacrificial film is formed to a thickness of 500 GPa or less, so that the silicon oxynitride deposition required for sacrificial film patterning can be omitted, and as the thickness of the sacrificial film becomes thinner, a thinner photoresist is used. It also has the effect of improving the mask pattern fine ability.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, an interlayer insulating film 22 is deposited on the semiconductor substrate 21. At this time, before the interlayer insulating film 22 is deposited, processes necessary for DRAM isolation such as device isolation and word lines are performed.

Alternatively, chemical mechanical polishing (CMP) is performed to stop on the gate to remove the interlayer insulating film on the gate, and then, amorphous carbon 23 is deposited on the exposed gate hard mask nitride film.

Meanwhile, the interlayer insulating film 22 may include a BSG (Boro-Silicate-Glass) film, a BPSG (Boro-Phospho-Silicate-Glass) film, a PSG (Phospho-Silicate-Glass) film, and a TEOS (Tetra-Ethyl-Ortho-Silicate) film. A film, an HDP (High Density Plasma) oxide film, a spin on glass (SOG) film, an advanced planarization layer (APL) film, or the like, or an inorganic or organic low dielectric constant film in addition to the oxide film is used.

Subsequently, an organic antireflection film 24 (OBARC) is deposited on the interlayer insulating film 22 on the amorphous carbon 23 having a thickness of 400 kV to 500 kPa, and the photoresist pattern 25 is formed on a predetermined region of the organic antireflection film 24. ).

On the other hand, in the embodiment of the present invention, since the silicon oxynitride hard mask is skipped, etching of the anti-reflection film 24 and etching of the amorphous carbon 23 should be possible as the photoresist barrier. In addition, since the etch rate of the amorphous carbon 23 is generally not largely different from that of the photoresist 25, it is difficult to fine-tune the thick amorphous carbon 23 without the silicon oxynitride mask, so that the thin amorphous carbon 23 is possible. Deposit.

In addition, when using thick amorphous carbon (thickness of 4000Å or more), which has been a problem in the past, a large problem occurs in the overlay margin during the process, and a separate key opening process is required for mask alignment, but when using amorphous carbon of 1000Å or less in thickness Without alignment.

Therefore, the key open mask process can be omitted, and the thickness of the photoresist required for mask patterning is only thin enough to etch thin carbons (200 mm to 1000 mm) of amorphous carbon, which is thinner than the prior art. It is also possible to use a photoresist, which enhances the mask pattern fine ability, enabling fine patterning without pattern collapse, and thus it may be applied to technology of 60 nm or less.

As shown in FIG. 2B, the anti-reflection film 24a and the amorphous carbon 23a are etched using the photoresist pattern 25 as an etching barrier. At this time, the predetermined thickness of the photoresist pattern 25a is lost while etching the antireflection film 24a and the amorphous carbon 23a.

As shown in FIG. 2C, after the photoresist pattern 25a is stripped, the amorphous carbon 23a is overetched to be etched to a predetermined thickness of the interlayer insulating layer 22a.

Meanwhile, the amorphous carbon 23a is etched using a mixed gas of O ₂ / NH ₃ / N ₂ / H ₂ / CH _x F _y / C _x F _y / Ar, and the anti-reflection film 24a is adjusted by adjusting the transient etching target. ) And the amorphous carbon 23a are removed, and the photoresist pattern 25a on the pattern is also removed.

This is because when the photoresist pattern 25a remains, a deformation phenomenon occurs during the subsequent etching of the self-aligned contact between the interlayer dielectric layers 22a, so that the photoresist pattern 25a on the anti-reflection film 24a is preferably removed, and Only the antireflection film 24a is left.

As illustrated in FIG. 2D, the interlayer insulating layer 22b is etched by performing a self-aligned contact etching process using the etched anti-reflection film and the amorphous carbon 23a as an etch barrier.

On the other hand, since the etching of the interlayer insulating layer does not have to consider the influence of the photoresist pattern deformation, a recipe having a characteristic inherent to the self-aligned contact that maximizes the selection ratio and secures the bottom CD is applied.

Self-aligned contact etch chemicals use gases that generate large amounts of CF ₂ radicals, such as C ₄ F ₈ / C ₄ F ₆ / C ₅ F ₈ . At this time, since a hard mask of amorphous carbon 23a having high resistance to self-aligned contact recipe remains on the upper portion of the pattern, the loss of the amorphous carbon 23a when etching the interlayer insulating film 22b may be insignificant.

As illustrated in FIG. 2E, the self-aligned contact etching process of the interlayer dielectric layer 22b is performed to form the landing contact hole 26, and after completion of the process, the amorphous carbon 23a remaining on the upper portion of the pattern is subjected to O ₂ ashing ( ashing) process to remove.

More specifically, the anti-reflection film 24a and the amorphous carbon 23a are simultaneously removed after the self-aligned contact etching of the interlayer insulating film 22b is completed. Since the parts that will be a process problem due to the removal of the amorphous carbon 23a, which is a hard mask, are all removed, no additional process is required on subsequent flows.

Subsequently, although not shown in the drawing, a landing plug contact process is performed to form a landing plug.

As described above, amorphous carbon is used as the interlayer insulating film hard mask, but the deposition of silicon oxynitride may be omitted by thinner deposition, and the key open mask process may be omitted because the deposition of amorphous carbon is thin. Can be.

In addition, since a thin photoresist pattern is formed by using a thin amorphous carbon, fine patterning is possible without pattern collapse by improving the mask pattern fine ability, and thus it is applicable to a technology of 60 nm or less.

The present invention is sufficiently applicable to other process steps as long as the structure requires a self-aligned contact process. The present invention may be applied to a hole-type self-aligned contact based on a line type, and may be applied to the storage node contact process in the same concept.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above can obtain the effect of skipping the key open process required additionally to the amorphous carbon process.

In addition, the present invention can omit the deposition and etching of the silicon oxynitride hard mask which is essential for the hard mask process using amorphous carbon can be a competitive process.

In addition, the present invention allows the hard mask to be removed without affecting the subsequent process through the photoresist strip process.

In addition, the present invention has the advantage of inheriting the advantages of the existing amorphous carbon hard mask as it is.

Claims (6)

Forming a conductive line on the semiconductor substrate, and filling the conductive line with an insulating film; Stacking a sacrificial film and an antireflection film on the entire surface of the resultant product; Forming a photoresist pattern on the anti-reflection film; Etching the anti-reflection film and the sacrificial film using the photoresist pattern as an etching barrier; Adjusting the etching target of the sacrificial layer to remove the remaining photoresist pattern; Forming a hole for opening a predetermined region of the semiconductor substrate by etching the insulating layer using the sacrificial layer as an etching barrier; And Removing the remaining sacrificial film and the anti-reflection film Semiconductor device manufacturing method comprising a. The method of claim 1, The sacrificial film is a semiconductor device manufacturing method formed of amorphous carbon. The method according to claim 1 or 2, The sacrificial film is a semiconductor device manufacturing method formed to a thickness of 400 ~ 500Å. The method of claim 1, The etching of the anti-reflection film and the sacrificial layer by using the photoresist pattern as an etching barrier, A semiconductor device manufacturing method proceeding in-situ or ex-situ. The method of claim 1, Forming a hole to open a predetermined region of the semiconductor substrate by etching the insulating layer using the sacrificial layer as an etching barrier; The selectivity ratio between the insulating layer and the sacrificial layer is 10: 1, and the etching gas is etched using an etching gas including a chemistry such as aC _x F _y , bO ₂ , cAr, dCH _x F _y , eCO and fN _2. Semiconductor device manufacturing method. The method of claim 5, The etching gas is a semiconductor device manufacturing method using a gas for generating a large amount of C ₄ F ₈ , C ₄ F ₆ , C ₅ F ₈ and CF ₂ radicals.

Images