JPH0614347A - Data transmission circuit - Google Patents

Abstract

PURPOSE:To make it possible to independently transmit a sound signal even when a video signal is interrupted in the transmission of a composite signal of video and sound signals. CONSTITUTION:When a video signal from a transmitter is interrupted in a multiplexer for converting a digital sound signal to be transmitted to a block signal, a synchronizing signal monitoring circuit 21 outputs a level synchronism detecting signal to the 1st and 2nd selectors 23, 24. Then, horizontal and vertical synchronizing timing signals outputted from a synchronizing timing circuit 22 are respectively outputted to a PLL circuit 7 and a vertical synchronism protecting circuit 9 through the selectors 23, 24. Thereby, a window signal is outputted from a multiplex control circuit 6 and a clock is outputted from a PLL circuit 11. Thereby, even when a video signal does not exist, digital sound data are stored in an FIFO memory 4, read out and converted into block data. Thus, sound data are stably transmitted from the transmitter to a receiver.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission circuit for converting a video signal, an audio signal or the like into a composite digital signal and transmitting the composite digital signal to a remote place.

[0002]

2. Description of the Related Art As a method of transmitting an audio signal with high quality in accordance with a pulsed video signal, there is a method of converting the audio signal into a PCM and transmitting the digital signal in combination with a synchronizing blanking period of the video signal. In this case, the combined composite digital signal is transmitted to a remote place via an optical fiber or the like.

A conventional data transmission circuit used in such a multiplex transmission system of video and audio signals will be described. FIG. 2 is a block diagram showing a configuration of a data transmission circuit that transmits and receives a video signal of a high definition television (HDTV) or the like and an audio signal of PCM. In the figure, an A / D converter 1 is a circuit which inputs an analog four-channel audio signal transmitted at the same time as a video signal, performs sampling, quantization and encoding, and converts it into digital audio data. The PCM encoder 2 synthesizes the other data input from the outside with the 4-channel audio data output from the A / D converter 1, adds an error correction code and the like, and adds the data in frame units (F). Is a circuit to create.

FIG. 3 shows a 1 generated by the PCM encoder 2.
It is explanatory drawing which shows the structure of frame data. As shown in the figure, one frame data includes an area A of the synchronization code and an area B of other data, areas C to F of audio data # 1 to # 4,
It is composed of an area G of the error correction code. Here, one frame has an array of 75 bits in the horizontal direction and 32 bits in the vertical direction, and the sync code is recorded in an area of 1 bit in the horizontal direction and 16 bits in the vertical direction. Further, other data is recorded in an area of 3 bits in width and 32 bits in length, and the audio data # 1 to # 4 is recorded in an area of 16 bits in width and 32 bits in length. Further, the error correction code is recorded in an area having a width of 7 bits and a length of 32 bits. Therefore, one frame has a signal of 75 × 32 = 2400 bits.

Next, the PCM encoder 2 performs interleave processing to avoid the burst error of this 1-frame data, converts it into serial data by a clock (CL) output from a multiplexer (MPX) 3 described later, and outputs a signal. . Multiplexer (MPX) 3 is PCM
This is a circuit for dividing the frame data into blocks so as to multiplex the frame data output from the encoder 2 in the blanking period of the video signal. That is, the multiplexer 3 divides the frame data into blocks in synchronization with the horizontal synchronizing period of the video signal, and outputs a plurality of block data together with the window signal in synchronization with the blanking period.

FIG. 4 is a block diagram showing the structure of the conventional multiplexer 3. In FIG. 4, the PCM encoder 2
The frame data output by the
Out) Input to the memory 4. The FIFO memory 4 is a first-in first-out buffer memory, which stores 4-channel audio data and other data, and reads the data in the order of input during the blanking period of the video signal.
The read data of the FIFO memory 4 is given to the header adding circuit 5. The header adding circuit 5 is a circuit that divides the input data into blocks and adds header data to the tip of the divided data.

On the other hand, the multiplexing control circuit 6 is a circuit for creating a window signal (W) indicating the multiplexing timing of frame data based on the horizontal and vertical synchronizing signals of the video signal. Further, the multiplexing control circuit 6 outputs a read clock to the FIFO memory 4 for reading the accumulated frame data and outputs a header data addition timing signal to the header addition circuit 5. Next, the PLL circuit 7 has an internal oscillating circuit, and a horizontal synchronizing signal (H) separated from the video signal.
It is a circuit that generates a high-frequency clock signal having the same phase as. The horizontal synchronization counter 8 is a circuit that divides the clock output from the PLL circuit 7 to generate a horizontal synchronization clock having a predetermined cycle and phase. This horizontal synchronizing clock is given to the multiplexing control circuit 6.

The vertical sync protection circuit 9 checks whether or not the vertical sync signal (V) separated from the video signal has a regular cycle, and if the timing is a plurality of times, the vertical sync signal is regarded as a regular vertical sync signal. , A circuit that outputs the signal as it is. This signal is given to the vertical synchronization counter 10 as a reset signal. The vertical synchronization counter 10 is a circuit that counts the output pulses of the horizontal synchronization counter 8 and uses the reset signal output from the vertical synchronization protection circuit 9 to output frequency-divided pulses of a constant cycle. This signal is output to the multiplex control circuit 6 and the PLL circuit 11 as a normal vertical synchronizing clock. The PLL circuit 11 is a circuit that has an internal oscillation circuit and that generates a read clock signal of the FIFO memory 4 in synchronization with the vertical synchronization clock output from the vertical synchronization counter 10. This signal is also the PCM shown in FIG.
It is used as a clock (CL) for the encoder 2.

The block data (B) and the window signal (W) are supplied from the multiplexer 3 configured as described above to the transmitter 12 shown in FIG. The transmitter 12 pulse-modulates an analog video signal input from the outside,
It is a circuit that generates a pulse signal that is frequency-modulated based on the amplitude of a video signal. The transmitter 12 includes a sync separation circuit, separates the horizontal sync signal H and the vertical sync signal V included in the video signal, and outputs them to the PLL circuit 7 and the vertical sync protection circuit 9 in the multiplexer 3, respectively. Furthermore, the transmitter 1
Reference numeral 2 is for multiplexing the block data output from the multiplexer 3 into a video signal using a window signal, converting the multiplexed signal into an optical signal, and outputting the optical signal to the optical fiber 13.

A receiver is connected to the other end of the optical fiber 13. The receiver 14 in the receiver converts a digital optical signal transmitted via the optical fiber 13 into an electric signal,
This circuit demodulates the pulse-modulated video signal into the original analog video signal. Further, the receiving unit 14 separates the serial audio data and other data multiplexed during the blanking period into block data by using the window signal. Further, the receiver 14 has a sync separation circuit that separates a horizontal sync signal and a vertical sync signal from the demodulated video signal.

Next, the demultiplexer (DMPX) 15
Has a configuration similar to that of the multiplexer 3 of the transmitter, generates a window signal based on the horizontal synchronizing signal and the vertical synchronizing signal output from the receiving unit 14, and supplies the window signal to the receiving unit 14.
The demultiplexer 15 converts the block data output from the receiving unit 14 into two-dimensional frame data as shown in FIG.

Next, the PCM decoder 16 performs a de-interleave process on the input frame data by the clock output from the demultiplexer 15 and after error correction, demodulates the 4-channel audio data and other data. Is. The D / A converter 17 is the PCM decoder 1
The 4-channel audio data output from 6 is converted into an analog audio signal.

The operation of the data transmission circuit configured as described above will be described with reference to the signal waveform diagrams of FIGS. FIG. 5 is a signal waveform diagram showing the modulation and demodulation of the video signal in the transmitter 12 and the receiver 14. FIG. 6 is a signal waveform diagram showing the synchronizing signal before and after the blanking period of the video signal.

Now, when the video and audio signals are outputted from the source, the video signal is given to the transmitting section 12, and the audio signal is given to the A / D converter 1. As shown in FIGS. 5 (a) and 5 (b), a pulse having a fixed width, which is pulse frequency modulated, is generated in the analog video signal according to its amplitude. On the other hand, the analog voice signal is sampled, quantized and coded for each channel by the A / D converter 1, and converted into 4-channel voice data. These audio data are combined with other data input from the outside by the PCM encoder 2, and as shown in FIG. 3, a synchronization code and an error correction code are added and converted into two-dimensional frame data. Further, in the PCM encoder 2, in order to prevent a burst error during transmission, interleave processing for changing the transmission order of bit signals is performed. Next, the PCM encoder 2 outputs the frame data to the FIFO memory 4 of FIG. 4 according to the clock signal of the PLL circuit 11 in the multiplexer 3.

On the other hand, the transmitting unit 12 has an arrow V in FIG.
The video signal including the luminance signal and the color signal shown in is input. A periodic ternary signal having a negative polarity pulse and a positive polarity pulse is inserted as a horizontal synchronization signal in this signal, as in the HDTV, for example, a high-definition synchronization signal. Further, assuming that the number of horizontal scanning lines is 1125, FIG.
As shown in the period T1 in (a), DC is applied from 1H to 5H.
The vertical sync pulse whose level is set to the-side is superimposed. This signal is separated as a vertical synchronizing signal, and is shown in FIG.
The vertical sync signal as shown in (3) is applied to the vertical sync protection circuit 9 in the multiplexer 3. Similarly, the transmitter 12 is shown in FIG.
A negative horizontal synchronizing signal as shown in FIG. 6B is separated from the ternary waveform included in the signal of FIG. 6A and output to the PLL circuit 7 in the multiplexer 3.

When the vertical sync protection circuit 9 of FIG. 4 detects a normal vertical sync signal, it outputs this signal to the vertical sync counter 10. Then, the vertical synchronization counter 10 uses this vertical synchronization signal as a reset signal, divides the output signal of the horizontal synchronization counter 8 and supplies the vertical synchronization clock to the PLL circuit 11. Then, the PLL circuit 11 matches the signal phase of the built-in oscillation circuit with this vertical synchronizing clock and outputs the clock for reading. This clock is the PC of Figure 2
The frame data given to the M encoder 2 are sequentially shown in FIG.
Stored in the FIFO memory 4.

The frame data once stored in the FIFO memory 4 is read according to the read clock output from the multiplexing control circuit 6 at a timing such that the frame data can be multiplexed during the blanking period of the video signal. That is, this data is shown in FIG.
As shown in (e), a plurality of horizontal scanning periods Ta, Tb, Tc ... Tp, Tq, which are positioned before and after the vertical synchronization period.
A signal is read with Tr ... Each block. Head data from the header adding circuit 5 is added to the head of each block to this signal.

On the other hand, the multiplexing control circuit 6 generates a window signal as shown in FIG. 6 (d) and outputs it to the transmission section 12. The transmitter 12 uses this window signal to insert the block data into the blanking period of the video signal. The signal multiplexed in this way is converted into an optical signal by the transmitter 12 and output to the receiver via the optical fiber 13.

Next, the composite video and audio digital signal transmitted through the optical fiber 13 is converted into an electric signal by the receiver 14. That is, the signal whose pulse frequency is modulated as shown in FIG.
As shown in (d), it is demodulated into an analog video signal.
Further, the demultiplexer 15 outputs the window signal shown in FIG. 6D from the video signal to the receiving unit 14. Receiver 1
4 uses this window signal to extract voice and other data from the received multiplexed signal in block units.
These block data are temporarily stored in the memory provided in the demultiplexer 15, and are sequentially converted into two-dimensional frame data by the internal clock as in the case of the multiplexer 3.

The frame data and the clock output from the demultiplexer 15 are given to the PCM decoder 16 and subjected to de-interleaving processing of restoring the transmission order of the bit signals. Further, error correction processing is performed and the 4-channel audio data and other data are demodulated. These audio data are converted into analog signals by the D / A converter 17, and the original audio signals are output.

[0021]

However, such a conventional configuration causes a problem when the video signal is interrupted when the analog video signal and audio signal are applied to the transmitter. That is, if the video signal is interrupted for some reason, the transmitter 12 cannot output the horizontal and vertical sync signals, and the multiplexer 3 outputs the necessary clock even if the audio signal or other data is input. It will not be possible. For this reason, the PCM encoder 2 and the multiplexer 3 do not operate normally, causing a problem that the audio signal being input is not transmitted to the receiver.

In the transmitter, the source video signal is often output or switched independently of the audio signal. Therefore, if the video signal is interrupted even for an instant,
There is a drawback that the voice signal and other data are not transmitted each time.

The present invention has been made in view of the above-mentioned problems of the related art, and when transmitting the video signal and the audio signal and the other data independently, even if the video signal is interrupted, the audio signal is interrupted. An object of the present invention is to realize a data transmission circuit that can transmit a signal and other data to a receiver without interruption.

[0024]

According to the present invention, audio data is divided into blocks in synchronization with a horizontal synchronizing signal and a vertical synchronizing signal of a video signal to be transmitted, and the block data is output, and the time axis of the block is A data transmission circuit comprising: a multiplexer that outputs a window signal indicating an area; a transmission unit that pulse-modulates and multiplexes the block data and the video signal output by the multiplexer, and transmits a composite digital signal. Sync signal monitoring circuit that outputs a sync detection signal according to the presence / absence of a vertical sync signal separated from the video signal, a horizontal sync signal and a vertical sync signal included in the video signal, a horizontal sync timing signal and a vertical sync signal having the same period. Sync detection signal is output from sync timing generation circuit that generates sync timing signal and sync signal monitoring circuit The horizontal synchronizing signal of the video signal when selected, and the horizontal synchronizing timing signal of the synchronizing timing generating circuit when not outputting, and the clock signal whose phase matches the output signal of the first selector. , A horizontal synchronizing counter that counts the clock signal output from the PLL circuit and generates a horizontal synchronizing clock, and a vertical sync signal of the video signal when the synchronous detection signal is output from the synchronous signal monitoring circuit. A second selector for selecting the vertical synchronization timing signal of the synchronization timing generation circuit when selected and not output;
A vertical sync protection circuit that outputs the output signal of the second selector when the output signal of the second selector is input and it is confirmed for a plurality of cycles that it has a specified vertical sync cycle. It is reset by the output of the circuit, counts the output of the horizontal sync counter, generates the vertical sync clock, and multiplexes the data within the blanking period based on the output of the horizontal sync counter and the output of the vertical sync counter. And a multiplex control circuit for outputting a window signal for performing the operation.

[0025]

According to the present invention having such characteristics, the audio data is divided into blocks in synchronization with the blanking period of the video signal to be transmitted, and the block data is given to the multiplexer. The transmitting unit also separates the horizontal synchronizing signal and the vertical synchronizing signal from the video signal and gives them to the multiplexer. In the multiplexer, the sync signal monitoring circuit outputs a sync detection signal if the video signal includes a vertical sync signal. On the other hand, the sync timing generation circuit generates a horizontal sync signal and a vertical sync signal of the video signal, and a horizontal sync timing signal and a vertical sync timing signal of the same cycle, respectively. Next, the first selector selects the horizontal sync signal of the video signal when the sync detection signal is input, and selects the horizontal sync timing signal of the sync timing generation circuit when the sync detection signal is not input. The second selector selects the vertical synchronization signal of the video signal when the synchronization detection signal is input, and selects the vertical synchronization timing signal of the synchronization timing generation circuit when the synchronization detection signal is not input. Then, the PLL circuit generates a clock signal whose phase matches the output signal of the first selector and outputs the clock signal to the horizontal synchronization counter. The vertical sync protection circuit inputs the signal of the second selector and outputs the output signal of the second selector to the vertical sync counter when it is confirmed for a plurality of cycles that the signal has the specified vertical sync cycle. Then the vertical sync counter
The output of the horizontal sync counter is divided to generate a vertical sync clock. With this configuration, even if the video signal is interrupted by the transmitter, the block data of the audio can be output to the transmitter based on the outputs of the horizontal synchronization counter and the vertical synchronization counter. Therefore, the voice data is stably transmitted to the receiver side.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A data transmission circuit according to an embodiment of the present invention will be described. In the data transmission circuit of FIG. 2 showing a conventional example, the parts other than the multiplexer 3 are the same, so only the multiplexer of this embodiment will be described. FIG. 1 is a block diagram showing the configuration of a multiplexer 20 used in the data transmission circuit of this embodiment. In the figure, a FIFO memory 4, a header addition circuit 5, a multiplexing control circuit 6, a PLL circuit 7, a horizontal synchronization counter 8, a vertical synchronization protection circuit 9, a vertical synchronization counter 10, and a PLL circuit 11
Since it is the same as the conventional example, the detailed description thereof will be omitted.

In FIG. 1, the sync signal monitoring circuit 21 checks whether or not the vertical sync signal is output from the transmission section 12 of FIG. 2, and while the vertical sync signal is being detected, for example, the H level sync detection is performed. It outputs a signal. On the other hand, the synchronization timing generation circuit 28 is a circuit which has an internal clock and independently generates a horizontal synchronization timing signal and a vertical synchronization timing signal like a synchronization signal of the HDTV standard.

The sync detection signals of the sync signal monitoring circuit 21 are input to the control terminals of the first and second selectors 23 and 24, respectively. Further, the horizontal synchronizing signal and the vertical synchronizing signal output from the transmitting unit 12 are given to one input ends of the first and second selectors. The first selector 23 is a circuit that selects one of the input signals according to the H or L level of the synchronization detection signal input to the control terminal. The second selector 24 is also the same circuit as the first selector 23. The horizontal synchronization timing signal output from the synchronization timing generation circuit 22 is applied to the other input end of the first selector 23,
The vertical synchronization timing signal is given to the other input terminal of the second selector 24.

Next, the output of the first selector 23 is given to the same PLL circuit 7 as in the conventional example, and the output of the second selector 24 is also given to the same vertical synchronization protection circuit 9 as in the conventional example. The clock signal output from the PLL circuit 7 is given to the horizontal synchronizing counter 8.

The operation of the data transmission circuit of this embodiment having the above configuration will be described. When both the video signal and the audio signal are input to the transmitter, the transmitter 12 of FIG.
Separates the horizontal sync signal and the vertical sync signal from the video signal, respectively. Both of these signals are given to the first and second selectors 23 and 24 of the multiplexer 20, and the vertical synchronizing signal is given to the synchronizing signal monitoring circuit 21. In this case, the sync signal monitoring circuit 21 detects the sync signal and outputs the H level sync detection signal. Therefore, the first and second selectors 23 and 24 respectively pass the horizontal synchronizing signal and the vertical synchronizing signal generated by the transmitting unit 12. That is, the horizontal synchronizing signal of the video signal is input to the PLL circuit 7, and the vertical synchronizing signal is input to the vertical synchronizing protection circuit 9. Since the operation of the data transmission circuit including the multiplexer 20 in this case is the same as the operation described in the conventional example, the description thereof will be omitted.

Next, the case where the video signal is interrupted during the transmission of the video signal and the audio signal will be described. At this time, the transmitter 12 cannot detect the horizontal synchronizing signal and the vertical synchronizing signal, and those signals are not output to the multiplexer 20. Therefore, the vertical synchronizing signal is not given to the synchronizing signal monitoring circuit 21, and the L-level synchronizing detection signal is sent to the selector 2
Output to 3, 24. Therefore, the selectors 23 and 24 are
The signal at the input end is switched to select the horizontal sync timing signal and the vertical sync timing signal output from the sync timing generation circuit 22. These signals are output to the PLL circuit 7 and the vertical synchronization protection circuit 9, respectively, and the horizontal synchronization counter 8
And the vertical synchronization counter 10 operates. Therefore, the PLL
The circuit 11 outputs a clock to the PCM encoder 2, and the multiplexing control circuit 6 outputs a window signal to the transmitter 12. On the other hand, the audio signal input to the A / D converter 1 is digitally converted and converted into frame data by the PCM encoder 2. In this case as well, the operation of each circuit section after the multiplexer 20 is the same as that of the conventional example, and therefore its explanation is omitted.

When the input of the video signal to the transmitter is interrupted as described above, the multiplexer 20 uses the signal of the synchronization timing generation circuit 22 to generate a clock and a window signal, and inputs the clock and window signal to the A / D converter 1. Each of the generated audio signals is transmitted to the receiver. Therefore, each audio signal and other data can be stably transmitted to the transmitter regardless of the interruption of the video signal.

[0033]

As described above in detail, according to the present invention, the multiplexer is provided with the synchronous timing generating circuit, so that the PCM encoder and the transmitting section are stable even if the video signal input to the transmitter is interrupted. The clock and window signals can be output. Therefore, the voice output and other data can be transmitted independently, and the effect of increasing the reliability of the data transmission circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a multiplexer used in a data transmission circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a data transmission circuit.

FIG. 3 is an explanatory diagram showing a structure of frame data.

FIG. 4 is a block diagram of a multiplexer used in a conventional data transmission circuit.

FIG. 5 is a signal waveform diagram showing modulation and demodulation of a video signal.

FIG. 6 is a signal waveform diagram showing horizontal and vertical synchronization signals included in a video signal.

[Explanation of symbols]

 1 A / D converter 2 PCM encoder 4 FIFO memory 5 Header addition circuit 6 Multiplexing control circuit 7, 11 PLL circuit 8 Horizontal sync counter 9 Vertical sync protection circuit 10 Vertical sync counter 12 Transmitter 14 Receiver 15 Demultiplexer 16 PCM decoder 17 D / A converter 20 Multiplexer 21 Synchronous signal monitoring circuit 22 Synchronous timing generation circuit 23 First selector 24 Second selector

Claims (1)

[Claims] 1. The audio data is divided into blocks in synchronization with a horizontal synchronizing signal and a vertical synchronizing signal of a video signal to be transmitted, the block data is output, and a window signal indicating a time axis region of the block is output. A multiplexer, a block data output from the multiplexer and a transmitter that pulse-modulates and multiplexes the video signal to transmit a composite digital signal, wherein the multiplexer is the transmitter. A sync signal monitoring circuit that outputs a sync detection signal according to the presence or absence of a vertical sync signal separated from the video signal, a horizontal sync signal and a vertical sync signal included in the video signal, a horizontal sync timing signal and a vertical sync of the same cycle A synchronization timing generation circuit for generating timing signals, and the synchronization signal monitoring circuit for detecting the synchronization timing. A first selector for selecting a horizontal synchronizing signal of the video signal when the signal is output, and a horizontal synchronizing timing signal of the synchronizing timing generating circuit when the signal is not output; and an output signal of the first selector. A PLL circuit that generates a clock signal having a matched phase, a horizontal synchronization counter that counts clock signals output from the PLL circuit, and generates a horizontal synchronization clock, and the synchronization detection signal is output from the synchronization signal monitoring circuit. The vertical sync signal of the video signal is selected when the output signal is output, and when the vertical sync signal of the video signal is not output, the second selector that selects the vertical sync timing signal of the sync timing generation circuit; If it is confirmed for a plurality of cycles that it has a vertical synchronization cycle of, the output signal of the second selector is output. A direct synchronization protection circuit, a vertical synchronization counter which is reset by the output of the vertical synchronization protection circuit, counts the output of the horizontal synchronization counter, and generates a vertical synchronization clock, and the output of the horizontal synchronization counter and the vertical synchronization counter. And a multiplexing control circuit for outputting a window signal for multiplexing the data within the blanking period based on the output, the data transmission circuit.