RU2121235C1 - Device for formatting packetized digital data streams to transmit television information - Google Patents

Abstract

FIELD: television engineering. SUBSTANCE: packetized data stream that incorporates data byte packet including video information encoded according to standard developed by group of experts on moving images arrives at input of transmitting processor unit. The latter yields stream of data characters in the form of sequence of data fields incorporating groups of data segments together with field synchronizing segment coupled with them. Transmitting processor enters service information, such as that about encoding direct error correction, in each data segment and also introduces longer field-synchronization service segment between groups of data-field segments. Clock pulse frequency of bytes at transmitting processor input (twice as low frequency of clock pulses of characters SC/2) is integer-valued subharmonic of clock pulse frequency of characters at output (SC). Input data stream has constant and uniform spaces between data packets and is characterized by constant uniform data repetition rate. Same procedure takes place in receiver but in reverse sequence. EFFECT: provision for seamless point of insertion of field-synchronization service segment into data stream without interrupting data stream. 24 cl, 18 dwg

Description

 The invention relates to the field of digital signal processing and, in particular, to a system for formatting a sequence of packets in a packetized data stream used in a high-resolution television system.

 Recent developments in the field of video signal processing have led to the emergence of systems for processing and transmitting digital television signals of high resolution. One such system is described in US Pat. No. 5,168,356 to Acampor et al. In this system, a codeword data stream including codewords entered as is customary in accordance with a data compression standard developed by the Moving Image Experts Group (MPEG) arrives at the transport processor. The main function of the transport processor is to pack data from codewords of variable length into words from packed data. The accumulation of words from packed data called a data packet or data element is preceded by a header containing, among other information, information to identify the corresponding information words. Thus, the output of the transport processor is a packetized data stream containing a sequence of transport packets. The format of the transport packet increases the likelihood of resynchronization and restoration of the signal in the receiver, for example, after a signal is broken, which can be caused by a malfunction of the transmission channel, from the header data, from which the receiver can determine the points of re-entry into the data stream in the conditions of loss or damage of the transmitted data.

 The high-definition terrestrial television broadcasting system, proposed in the United States under the name Grand Alliance HRCTV systems, uses a partially suppressed sideband digital transmission (VSB) format for transmitting a packetized data stream. The Grand Alliance system is a proposed broadcast standard that is being considered by the Federal Commission on the Advisory Committee of the Advanced Television Service. In this system, data is arranged as a sequence of data fields. Each field structure contains 313 segments: a field synchronization segment (which does not contain actual data), followed by 312 data segments. Each data segment contains an information component and a direct error correction component. A synchronization component is associated with each data segment. The transport processor sends 188-byte fixed-length data packets to the transmit processor, which performs various coding operations on each data packet, producing character segments sent to the output transmit channel. Each byte contains a certain number of characters, for example, 4 characters. A description of the Grand Alliance system as presented to the technical subgroup of the Advisory Committee of the Advanced Television Service on February 22, 1994 (preliminary document) can be found in Sat. "Successes for 1994 of the National Association of Broadcasting Companies", "Successes of the 4th Annual Conference on Broadcasting Techniques", March 20-24, 1994

 Data packets contain data that complies with the ISO-MPEG (International Organization for Standardization, Group of Experts on Moving Images) MPEG -2 standard for data compression. The transport processor only sends data packets to the transmitting processor, which adds an overhead component for detection and direct error correction to each segment at the beginning of each data field, i.e. between each group of data field segments, adds a service field synchronization segment. The data flow is regulated in such a way that these operations are carried out, since, as indicated below, the direct error correction components and the field synchronization segment appear at different points in time and are characterized by different durations. There are several ways to control the flow of data to meet the requirements for transmitting output symbols in relation to this data field structure. One such method boils down to calculating the useful bandwidth by the clock frequency of transmitting the output symbols and the entered service information. In this case, it is required that the frequency of the clock pulses used to transmit data from the transport processor to the transmitting processor exactly matches the speed of data output from the transmitting processor. This frequency does not have to be in integer ratio with the clock frequency of the characters. When the ratio is not integer, a phase locked loop can be used to maintain the required phase to frequency ratios at the input and output. However, the use of a phase-locked loop is undesirable since the cost and complexity of the system are significant.

 Another way is to modulate the data stream following from the transport processor to the transmitting processor, as it were, in a packet-monopoly manner using clock pulses derived from symbol clock pulses. In this case, packets that meet the data compression standard (MPEG-2) and contain 188 bytes of data are introduced into the transmitting processor in the form of a continuously next burst, the packets being divided intervals into which overhead information about direct error correction is entered for each data segment introduced into the data stream by the transmitting processor. However, the packet data stream must be interrupted and delayed for a period equal to the interval of the segment and occurring at the time when a longer segment of the field synchronization should be inserted into the data stream, which does not contain actual data like other packets. The inventors came to the conclusion that such an interrupted data stream not only undesirably reduces the data transfer rate, but also leads to the appearance of uneven intervals between data packets. Such non-uniform inter-packet intervals significantly complicate the requirements for signal processing, which will be noted later when considering FIG. 5.

 In particular, the inventors came to the conclusion that such an interrupted data stream undesirably complicates the requirements for the transport processor to interface with the transmitting processor, especially with regard to data synchronization, and with any system that records a packetized data stream. It is possible that the high-definition television data stream will be recorded on either studio or user equipment. In order to satisfy the requirements for synchronization of the MPEG standard, any recording system must accurately reproduce the temporal sequence of packets, including following any uneven gaps between packets that should remain between packets, if such gaps exist. This requirement greatly increases the complexity of the circuits needed to enable connectivity to a recording system. In addition, any such gaps produced by the transmitting processor must be stored in the receiver demodulator.

 The interface between the transport processor and the transmit processor is important in many applications, for example, in television broadcasting. In this case, the transmitting processor has to generate and issue data fields without interrupting them, since the transfer has already begun. Television receivers operate based on this uninterrupted stream of data fields, including field synchronization segments providing synchronization. Any change in the speed or structure of the data fields during broadcasting will result in loss of synchronization at the receiver. A broadcast studio usually has several groups of VCRs programmed to automatically include the proper source material at a set point in time. These tape recorders issue transport packets containing information embedded in traffic streams. Each tape recorder synchronizes its output, forming a stream of data entering the transmitting processor, which is not allowed to change the field speed or field structure. Uneven gaps in the stream of packets following from the transport processor to the transmitting processor lead to the transformation of the structure of the transmitted data fields into some kind of artificial formation in the data stream coming to the interface device, which will deal with both the packet and the structure of the data fields. Each studio recorder will inevitably require unwanted sophisticated interface devices that synchronize tape feed at both the packet and field boundaries. Certainly additional information will be required to pass the stream through the interface device, or it should be obtained by controlling the data flow in the interface device itself. The tape interface must definitely be able to detect packet synchronization conditions, detect the field, and have enough memory to buffer the structure of the data fields. Additional complications appear when you turn on pre-made tape recordings and when you insert local broadcasting programs and advertising messages. These difficulties and other difficulties are successfully predetermined in a system that meets the principles of the present invention.

 The present invention is advantageously applied in terms of using a system designed to process a packetized data stream, which is a structure of data fields of the type described above, containing information arriving at an uneven speed due to, for example, the introduction of various types of overhead information of different durations. In particular, the proposed system makes the configuration of the data stream such that the structure of the data fields is acceptable for passing through the data processors in the encoder and decoder, as a result of which the data stream is processed without seams and without interruption.

 In the proposed system, for example, in a transmitter / encoder, a packetized data stream is processed to obtain an output data stream, which is a sequential structure of data fields, each of which contains data and service information. The input circuit enters a data stream containing data packets separated by inter-packet gaps. The service chain introduces a field service information segment having a duration different from the duration of the inter-packet gaps within the data field. The transmission chain receives the data stream and the service field segment, forming an output data stream, which is a sequence of structural formations of data fields, each of which includes a service field segment and a data field containing a group of data segments. The input data stream is characterized by invariable equal inter-packet gaps and a constant uniform speed of data following the totality of structures from data fields. Equal inter-packet gaps provide the ability to seamlessly insert service information without interrupting the data stream.

 In accordance with a feature of the invention, as applied to a transmitter / encoder assembly, data packets are read in a transmitting processor under the influence of input (byte) clock pulses following with a frequency that is in integer relation with the output frequency (symbol clock pulses).

 In a preferred embodiment, the output data symbol stream resulting from the transmitting processor is a sequence of data fields, each of which contains a plurality of data segments that comply with the MPEG standard, in combination with overhead for error correction. Each data field is preceded by a field synchronization segment that carries overhead information of a different duration. The input byte clock is an even integer subharmonic of the output symbol clock. A fixed-length input data packet captures a fixed number of input clock pulses, and each packet is separated by a fixed, equal inter-packet interval capturing a prescribed number of input clock pulses. The number of clock pulses per packet gap is a function of factors such as the number of segments of the data field, the number of characters of the data segment, the duration of each data segment, and the duration of the field synchronization segment.

FIG. 1 illustrates a certain known sequence of data field structures containing synchronization and data segments; FIG. 2 is a block diagram of an apparatus for processing a packetized data stream;
FIG. 3 and 4 illustrate processing alternative forms of data field segments shown in FIG. 1;
FIG. 5 shows a packetized data stream having non-uniform intervals between data packets;
FIG. 6 to 11 illustrate packetized data streams having uniform intervals between data packets, in accordance with the principles of the present invention;
FIG. 12 is a block diagram of a transmitter encoder comprising a transmit processor receiving packetized input data necessary for supplying output symbols to an output processor for transmission;
FIG. 13 illustrates a spectrum of a television channel that can be used to pass the output provided by the system of FIG. 12, regarding the conventional spectrum of the television channel of the National Committee for Television Systems (NTSC) system;
FIG. 13a depicts a general arrangement of a receiving device;
FIG. 14 is a block diagram of a receiving analog of a transmission coding system shown in FIG. 12;
FIG. 15 and 16 depict data streams arising from the processing of packet data by the system shown in FIG. 12;
FIG. 17 and 18 depict data flows arising from other possible processing of packet data by the system shown in FIG. 12.

 In FIG. Figure 1 shows the structure of the data field proposed for use in the United States, the Grand Allrance HDTV system in the United States, which is used in a packet data processing system. An output data symbol stream representing the structure of the data field is provided by the transmitting processor 16 (FIG. 2) in response to the input data packets coming from the previous transport processor 14. In detail, the transmitting processor will be shown and described in FIG. 12. Each data field structure contains a field synchronization segment (which does not contain actual data) preceding a group of data field segments (X). Each segment of the data field contains a packet component containing 188 bytes, with each segment of data preceded by a synchronization component of the segment and the data is accompanied by a component of direct error correction. The parameter "Y" indicates the interval inaccessible to the data available between each data packet, as will be shown in the following figures. The transport processor transmits 188 byte input packets to the transmit processor, which creates the output segments in symbolic form, which must arrive at the input transmit channel.

 The data segment synchronization component and the field synchronization component provide the possibility of clocked capture and tracking of packets and symbols and phase automatic frequency in the receiver under the most severe conditions of noise and interference. The four-character data segment synchronization component is binary (two-level) so that mandatory packet and clock recovery occurs. It is characterized by a structure that is regularly repeated at a strictly defined speed, which provides the possibility of reliable detection in the receiver under the influence of noise and interference. The data segment synchronization symbols are not encoded according to Reed-Solomon or trellised encoding or interleaved encoding. The field synchronization component may contain pseudo-random sequences, and it serves several purposes. It is a means of determining the beginning of each data field and can also be used by the corrector in the receiver as a training comparison signal to remove intersymbol and other types of interference. It also serves as a means by which the receiver can determine whether or not to use a notch suppression filter, and it can be used for diagnostic purposes, such as measuring the characteristics of the signal-to-noise ratio and the magnitude of the channel throughput. The field synchronization component can also be used by phase-tracking circuits in the receiver to determine the parameters of the phase-locked loop. Like the segment synchronization component, the field synchronization component is not encoded with respect to error correction, nor is lattice encoded or interleaved encoded. In this example, the data fields do not necessarily correspond to the interlaced image fields that form the image frame of the television signal in the system of the National Committee for Television Systems (NTSC).

 In FIG. 2 shows a general arrangement of signal processing units with respect to processing the described data stream. The data source 12 sends the data compression standard (MPEG-2) byte data to the transport processor 14, which packs these bytes into fixed-length data words that ultimately turn into fixed-length data packets (188 bytes). Each package is preceded by a heading that contains information characterizing the source of the program, the type of broadcast and other information describing and relating to data contained, for example, in the actual data of the package associated with it. The transmit processor 16, which will be discussed in detail in connection with FIG. 12 performs operations, including forward error correction / correction coding, insertion of field synchronization data, trellis coding to improve the carrier-to-noise ratio, interleaving to reduce the occurrence of data errors due to pulsed interference, and character matching. The transmit processor 16 receives the incoming clock pulses of the SC / 2 bits, which are derived from the output clock pulses of the SC symbols, which in both cases are generated here by the block 16. The transport processor 14 also responds to the clock pulses of the SC / 2. The ENABLE signal from the transmitting processor 16 allows the processor 14 to send a data packet of 188 bytes to the processor 16 at allowed time intervals and prohibits sending data packets at unauthorized intervals. The data symbol stream exiting from block 16 is processed by output block 18 before entering the output channel. The output processor 18 comprises a pilot signal insertion circuit, a modulator with a partially suppressed sideband, and a boost radio frequency converter.

 In FIG. 3 shows a general view of processing one type of data field segment 20a in blocks 16 and 18 of FIG. 2. The segment contains an 188-byte transport packet compressed according to the MPEG-2 standard and containing a single-byte synchronization component according to MPEG, it is preceded by a synchronization component of a single-byte segment, and it is accompanied by a direct error correction component containing 20 bytes of Reed parity Solomon. Each transport packet, as used in the Grand Alliance high-definition television system, contains a 4-byte connecting header, the first byte of which is a synchronization byte, which provides packet synchronization. It may be followed by an optional adaptation header, with the remainder of the package being the actual data that meets the MPEG standard. This example is a proposed data field structure having 312 segments of data fields (X), characters (S) per segment, and a segment synchronization component in addition to the synchronization component according to the data compression standard (MPEG-2). Single-byte synchronization is matched with four characters before it is 2-VSB modulated. The 188-byte MPEG packet segment with direct error coding is (2/3) lattice encoded and matched up to 832 characters before being subjected to type 8 VSB modulation. Methods for implementing such modulation of the 2-VSB and 8-VSB types are well known. The resulting field segment 20b entering the output channel contains a 4-character segment synchronization component, followed by an 832-character data field component containing a standard synchronization component and a direct error correction component.

 The device shown in FIG. 4, similarly to the device in FIG. 3 except that the structure of the input segment 20c is different. In FIG. 4, the segment synchronization component is replaced by the MPEG synchronization component, i.e. only one synchronization component is used. This allows one byte to be excluded to form an 187-byte MPEG data packet. After processing the data / direct error correction component, the output segment 20d contains four less characters (828) in the segment compared to the example illustrated in FIG. 3 because only one synchronization component is used here. This system has one byte (8 bits) corresponding to four characters (2 bits per character).

 In FIG. 5 shows the proposed packetized data stream in accordance with the structure of the data fields, each data field having the characteristics shown in FIG. 3, i.e. a field has 312 field segments and one field synchronization segment. In particular, each segment of the data field contains 188 bytes of data ("packet bytes") and 20 bytes of direct error correction. 188 bytes of data for each segment are followed by 188 clock pulses, and 20 bytes of direct error correction for each segment are followed by 21 clock pulses. The twenty-first clock pulse introduces an insertion from the segment synchronization component. When the time comes for introducing a field synchronization segment, the transmission of data segments / direct error correction should be prohibited for an interval of 230 clock pulses, which corresponds to a segment clock interval (i.e. 21 + 188 + 21 clock pulses). The field synchronization segment does not contain actual data, as is the case for each packet data segment. This interruption of the data stream leads to the appearance of unwanted odd gaps or gaps between packets, as shown. Such an intermittent data stream and odd inter-packet gaps complicate the signal management and requirements for the interface equipment introduced between the transport and transmit processors (blocks 14 and 16 in Fig. 2) and also reduce the data transfer rate. In addition, as noted earlier, it is difficult to synchronize the structure of the data field when the previously recorded material is played back. Uneven gaps between packets greatly complicate the task of recording a packetized data stream on studio and user recording equipment, since odd inter-packet gaps must be preserved when they appear, i.e., recording equipment must correctly reproduce the time course of packets that comply with the MPEG standard. Odd gaps must be maintained in the output signal generated by the demodulator in the receiver.

 The described problem due to the presence of odd packet gaps is taken into account and solved by the system according to the present invention. The inventors came to the conclusion that in the packet data transmission system, the problems mentioned above can be circumvented by using uniform inter-packet gaps, which are functions of factors including the number of segments per data field and the length of the service segment to be inserted, such for example, as a field synchronization segment.

 The inventors came to the conclusion that the data stream from packets separated by uniform gaps is favorably affected by the use of the input clock bit rate, which is an integer subharmonic of the symbol clock frequency, as a result of which there is no need to use phase-locked loops. The proposed data stream can be implemented in several (rather than in one specific) data field structures, based on the number of segments per field. The advantage is that when using the proposed system, many parameters are not affected, such as the control frequency of a signal transmitted with a partially suppressed sideband, symbol rate, segment interleaving, Reed-Solomon error coding, and synchronization components. In accordance with the requirements of a particular system, it is necessary to control the number of segments per data field and the input clock frequency of the transmitting system.

из которого следует

и
Y + S/N•X + [(S/N) - 188]
Существует лишь несколько единственно возможных решений, у которых и X и Y являются целыми числами при данном количестве символов S, приходящихся на сегмент. На фиг. 6-7 проиллюстрированы два примера, для которых S = 836 символам и N = 2, т.е. частота тактовых импульсов на входе является половинной гармоникой частоты тактовых импульсов следования символов на выходе. В этих примерах получаются четные величины для целого числа N, поскольку четным является количество символов S. Но в соответствии с требованиями данной системы могут быть также использованы для N и нечетные величины. Примеры, проиллюстрированные на фиг. 6 и 7, относятся к сегменту с удвоенным тактированием, проиллюстрированному на фиг. 3.The byte clock frequency at the input of the transmitting processor can be defined as the symbol clock frequency at the input (SC) divided by an even integer when the number of characters per segment is even. However, an odd number can also be used. The output clock frequency of the characters is a function of the number of output characters per data field. The number of symbol clocks per field (SC / frield) is determined by multiplying the number of characters per segment (S) by the number of segments per field (X + 1) according to the following expression:
SC / field = S (X + 1)
In this expression, the number "1" is explained by the introduction of a field synchronization segment associated with each field. The number of input clock pulses per field (input clock / field) is equal to the number of data segments per field (X) multiplied by the sum of 188 bytes of data / clock pulses per packet segment and the number of clock pulses (Y) contained in the interval between packets. In this way:
input clock / field = X (188 + Y)
By dividing the clock pulse repetition rate by an integer N, the required frequency ratio is obtained for the input clock repetition rate, which ensures a uniform interval, as discussed above. In this way,

which implies

and
Y + S / N • X + [(S / N) - 188]
There are only a few unique solutions in which X and Y are integers for a given number of S characters per segment. In FIG. 6-7 illustrate two examples for which S = 836 characters and N = 2, i.e. the clock frequency at the input is half the harmonic of the clock frequency of the symbols following the output. In these examples, even values for an integer N are obtained, since the number of S characters is even. But, in accordance with the requirements of this system, odd values can also be used for N. The examples illustrated in FIG. 6 and 7 relate to the double-clocked segment illustrated in FIG. 3.

 It should be noted that the value of the interval Y between the segments of the data packets is large enough to form the interval required by the transmitting processor 16 for subsequent insertion of the required number of service bytes of coding for direct error correction per segment and service segment of field synchronization per field without interrupting the data stream . In the example of FIG. 6, 418 data segments are located between each field synchronization segment. With an N value of two, the input clock frequency is SC / 2, i.e. half the symbol clock frequency at the SC output. Each segment interval contains the equivalent of one additional symbol clock, i.e. at the input there are two additional clock pulses with a frequency of SC / 2. For this reason, each segment interval contains 418 + 1 = 419 pulses of the input clock frequency SC / 2. Since each segment contains a fixed number of data bytes equal to 188, and SC / 2 clocks associated with 188 data bytes, the rest of each segment contains 419 - 188 = 231 SC / 2 input clock pulses. In particular, each inter-packet interval of the prohibition of actual data at 231 clock pulses corresponds to the time required to insert service information on the direct correction of errors per segment and service segment of the field synchronization between data fields. After processing all 418 data segments belonging to the field, 418 excess SC / 2 clocks are accumulated. The aforesaid corresponds to 836 pulses of the output clock speed of the SC symbols, which exactly correspond to the seamless insertion time of the field synchronization segment between adjacent groups of data segments that make up the neighboring data fields. This insertion is performed without interrupting the data stream, as will be described in detail below for FIG. 12, taken in conjunction with FIG. 15. In addition, some features of FIG. 6 to 11 will be shown and discussed in detail with reference to FIGS. 12 and 14.

 Acceptable found clock frequency of characters of magnitude 10, 762237 MHz. The structure of the input clock frequency in FIG. 6 corresponds to the case where each data field contains both a segment synchronization component and an MPEG synchronization component (as shown in FIG. 3) - 836 characters per segment and 418 segments (data and information on direct error correction) between each field synchronization segment. In this example, the ratio of N of the output clock of the transmit processor to the input clock is two. The input clock frequency is characterized by the passage of 188 constant and homogeneous clock pulses during each interval of packet data bytes and is characterized by the passage of 231 constant and uniform clock pulses during each inter-packet (inaccessible to actual data) interval. A group of 231 clock pulses provides sufficient time so that the transmitting processor can insert the service component of direct error correction coding for each segment and the service segment of the field synchronization between data fields without interrupting the data stream.

 In FIG. Figure 7 shows a similar unchanged and homogeneous data transmission / non-transmission structure, except that there are 232 clock pulses between the intervals with packet data, in this case there are 209 data segments between each synchronization segment, which are half the number of segments in the example ( Fig. 6). A reduced number of 209 data segments can be used, for example, where a gain in dynamic characteristics can be obtained by more frequent occurrence of the field synchronization component.

 The service area for each data segment can be reduced using only one synchronization component, namely, the synchronization component that complies with the data compression standard (MPEG-2), since the MPEG-2 standard establishes that each MPEG packet starts with a synchronization byte. This segment structure with 832 characters per segment is shown in FIG. 4.

 In FIG. Figures 8 and 9 show the structures of the input byte clock with a uniform arrangement of data transmission / non-transmission intervals, providing an uninterrupted data stream for a data field with a segmented structure, such as shown in FIG. 4. In FIG. 8 shows a preferred input byte clock structure for a data field with 416 data segment intervals (data and forward error correction information) between each field synchronization interval. In this case, 188 bytes of input bytes are associated with each data packet of 188 bytes, and 229 input clocks are associated with each inter-packet interval inaccessible to the data, as a result of which enough time is accumulated at the end of each data field so that the transmitting processor could insert a field synchronization segment without interrupting the data stream. This structure compares favorably with an increased data transmission rate due to the use of only one synchronization component.

 The clock structure shown in FIG. 9 is similar, except that each data field contains half the number of data segments.

 The condition under which the output symbol clock and the input byte clock are characterized by an integer ratio of four is illustrated in FIG. 10 and 11. FIG. 10, the data field contains both a segment synchronization component and an MPEG standard synchronization component (for example, as shown in FIG. 3), 209 data segments between each field synchronization segment and 836 characters per segment. In FIG. 11 shows a data field structure using only one synchronization component (for example, as shown in FIG. 4), 208 data segments between each field synchronization segment and 832 symbols per segment. In both cases, there is a homogeneous structure of the passage / passage of data with constant and uniform gaps between the data packets and a continuous, uninterrupted data stream.

 In FIG. 12 shows additional transmission elements of the processor / encoder 16 (FIG. 2), which operates at the input clock frequency when the data field structure includes both the segment synchronization component and the synchronization component according to the MPEG standard.

 In this example, the output symbol clock (SC) is twice the input byte (N = 2), and there are 418 data segments between each field synchronization segment. Hereinafter, the block diagram of FIG. 12 will be discussed in conjunction with the data signal diagrams A-F shown in FIG. 15, which depict a portion of a packetized data stream in some processing steps.

 Packed data that meets the MPEG-2 data compression standard is received from transport processor 14 (FIG. 2) to block 22, which is known to perform forward error correction (FEC). The MPEG compliant input contains 188 bytes per segment, including the preceding MPEG sync byte, as indicated by signal A in FIG. 15. The input data is clocked using the byte input clock rate (SC / 2), which is half the output clock frequency of the characters (SC). Each segment interval of 188 data is followed by an inter-packet interval that is inaccessible to the data and covers 231 input clock pulses following with an SC / 2 frequency. Each segment spans 419 (i.e., 188 + 231) slots per SC / 2 input clock (corresponding to the time taken by 838 pulses following the SC symbol clock), and 418 data segments are located between the field synchronization segments. Thus, in each data segment, one SC / 2 input clock pulse is larger than the data segments located between the field synchronization segments (419 versus 418). Thus, 418 additional pulses with an input clock frequency of SC / 2 will be accumulated after passing through a data field consisting of 418 segments. Additional input clock pulses in the amount of 418 pulses, following with the frequency SC / 2, correspond to 836 additional pulse clocks of the pulse repetition rate of the output symbols (SC). These additional 836 SC clocks correspond exactly to the time required for the subsequent timing of the field synchronization segment in the data stream at the clock frequency of the output symbols without interrupting or otherwise disrupting the data stream.

 The clock generator 24 generates the clock signals (SC, SC / 2, SC / 4) necessary for the system, including the SC / 2 clock frequency for the transport processor 14 (Fig. 2), necessary to maintain synchronization between the transport processor 14 and the transmit processor 16 The connections of these clock paths to the blocks they clock are not shown to simplify the drawing. The control unit 30 (for example, a microprocessor) generates the signals necessary for the formation of the transmitted data fields with the data field structure described above and such that is obtained in the form of output symbolic data (signal F). The control unit 30 additionally generates an “SOLVE” signal, which is appropriately related to the structure of the data field. MPEG input byte data for one data field must be entered into memory before switching the memory operation mode from writing to reading at a given field speed. The "ALLOW" signal allows a single data packet to follow from the transport processor to the transmit processor. The DATA VALID signal generated by the transport processor in response to the ENABLE signal allows the transport system to delay a fixed number of clock pulses until the ENABLE signal is executed.

 The “DATA AVAILABILITY” signal coming from the transport processor 14 to the direct error correction unit 22 allows the unit 22 to read and process the input data coming from the transport processor 14. This is facilitated by the “RESOLVE” signal coming from the control unit 30, which informs the transport processor that the transmitting processor is in a ready state to compile a data packet for the purpose of processing them. The format of the input signal A (Fig. 15) for each input segment, composed of a data interval of 188 bytes in the subsequent interval without data, is determined by the format of the signal "ALLOW". The "ALLOW" signal allows the output register of the transport processor to skip the packet during the "DATA AVAILABILITY" interval. If there is no data in the output register of the transport processor, an empty packet is sent, which ensures the uniformity of the structure of the data stream. The "DATA AVAILABILITY" signal is given in response to the "ALLOW" signal and the buffer full signal issued by the output register and indicating that the buffer contains a certain number of data bytes.

 Forward error correction unit 22 adds 20 bytes of forward error correction data, as shown by signal "B" in FIG. 15, leaving 211 SC / 2 clocks in an interval inaccessible to data transmission. Signal “B” is sent in parallel to 65 kbyte segment storage devices 26 and 28, each of which stores data segments / direct error correction corresponding to completely filled neighboring data fields. These blocks alternately write and read data, as it were back and forth, doing so with the speed of the data fields in response to a control signal coming from block 30, as a result of which one memory records data segments / direct error correction for any one field data, while the other memory reads data segments / direct error correction for the previous adjacent field and vice versa. Both blocks 26 and 28 write in response to the input clock pulses of the SC / 2 frequency, read in response to the clock frequency of SC / 4, and output 8-bit words (one byte) at the output. Signal "B" illustrates data recording at SC / 2, and signal "C" reads at SC / 4, which is half the recording speed.

 Under the influence of the control signal coming from block 30, the output data / direct error correction segments following from the storage devices 26 and 28 are multiplexed in the time scale of the fields following by the block 34 into a single data stream of words of 8 bits (1 byte). This data stream contains a sequence of groups of segments of sequentially following data fields, and it enters the parallel-serial data converter 38. Block 38 converts each parallel 8-bit byte into a group of 4 words of 2 bits, which are output sequentially. Data from block 38 is (2/3) lattice-encoded (as is customary) block 40, which outputs 3 bits (two information bits and a derivative redundant bit) for every 2 input bits to improve signal-to-noise ratio characteristics. These bits appear according to a specific algorithm, examples of which are known in the art. Encoder 40 operates under the influence of the SC symbol clock rate together with block 42, which provides a third bit in accordance with a specific algorithm.

 The output of trellis encoder 40 (signal "D" in FIG. 15) contains a sequence of 3-bit trellis-encoded words with four 3-bit words forming a byte. Each data segment contains 832 characters, due to the action of the encoder 40 under the influence of four times the clock speed of the SC symbols. The output block 50, a clocked clock frequency of the SC symbols, correlates each 3-bit input word coming from the encoder 40 with one output symbol and multiplexes these symbols in time with a field synchronization component of a certain value coming from block 48 and with a segment synchronization component of four characters (signal "E") coming from block 45, forming the output stream of symbolic data. When block 50 performs the correlation function, eight progressively increasing numerical binary output values from 000, 001, 010 ... to 111, coming from block 40, are converted into eight symbolic levels -7, -5, -3, -1, +1, +3, +5 and +7. Block 45 typically provides a segment synchronization component of a certain value, which corresponds to a certain symbolic value, by block 50. If desired, an MPEG synchronization component can be used instead of a segment synchronization component. In this case, the generation of the segment synchronization component by block 45 will not occur, and the synchronization component corresponding to the MPEG standard will be extracted from the output signal of the direct error correction block 22 and transmitted to block 50 through block 45, i.e. it will enter block 50, bypassing the main data processing path.

 The control signals of the storage devices 26 and 28, the field multiplexer 34, the converter 38, the field synchronization generator 48 and the correlator / multiplexer 50 are supplied by the control unit 30, for example, a microprocessor. The control unit 30 provides enable and disable signals for reading / writing packets, timing signals for controlling the cross-operation operation of the memory devices 26 and 28, and field speed switching signals for, for example, multiplexer 34. In particular, the unit 30 controls the operation of the field synchronization generator 48 performing the function of cross-switching the field following speeds between the storage devices 26 and 28, so that the unit 48 is able to pass the information of the field synchronization segment to about the duration of the intervals of a certain duration created between adjacent data fields. This interval of a certain duration appears during the processing, which is described and illustrated for FIG. 15 to 18, whereby each field synchronization segment is predictably multiplexed by block 50, entering the data stream between groups of field data segments without interrupting the data stream.

 The output symbolic data stream coming from the multiplexer 50 is illustrated by the signal "F" in FIG. 15. Each segment of this data stream includes a uniform 836-character sequence starting with four segment synchronization characters, followed by four synchronization characters according to the MPEG-2 standard and a data packet according to the MPEG standard (including forward error correction bytes). Each segment of signal “F” for the output data stream is clocked 836 symbol clocks. These are two symbol clocks less than 838 symbol clocks, which are equivalent to 419 SC / 2 input clock pulses for data stream input signal “A”. Thus, each output segment requires two symbolic clock pulses less (836 versus 838) compared with the corresponding input segment. These two symbolic clock pulses, when 418 data segments are accumulated that make up the data field between the field synchronization segments, accurately give the additional time needed by block 50 to clock the field synchronization segment in the data stream at the output symbol clock rate. In particular, 836 symbol clock pulses (418 • 2), i.e. the same number of clock pulses as used for clocking each data segment of 836 characters is available for seamless insertion of each field synchronization segment into the data stream without stopping the data stream.

 As can be seen from the “F” signal, the output symbolic data stream is a continuous stream of adjacent 836 symbol segments, of which only three are shown to simplify the drawing. The time interval T1 denotes an “overlap” of two clock frequencies of the characters considered relative to the input data signal “A”. In particular, the second segment of the “F” signal begins immediately at the end of the first segment, but in this case, two symbol clock pulses follow the second segment of the “A” signal of the input data stream. Similarly, the time interval T1 + T2 denotes the overlap of four symbol clock pulses relative to the signal "A". This interval includes the accumulated interval T1 with the added interval T2 corresponding to two clock pulses. The interval T2 originates from the third segment of the signal "F", which begins immediately at the end of the second segment, but in this case, two symbol clocks go before the corresponding third segment of the input signal of the data stream "A". Additional SC clock intervals T3, T4, T5, etc. accumulate during the passage of subsequent segments, which occurs until 836 additional symbol clock pulses accumulate at the end of the data field from 418 segments, at this moment block 50 inserts the field synchronization segment in response to the influence of the symbol clock frequency.

 In FIG. 16 shows data signals A to F, which are similar to the signals shown in FIG. 15, except that in FIG. 16, only one synchronization component is used. This alternative for the embodiment of FIG. 6. This example does not use the single-byte, four-character segment synchronization component. Instead, MPEG-2 synchronization is carried out through block 45 outside the main data processing path, and the synchronization segment is multiplexed into the output data stream instead of block synchronization by block 50. When comparing the “F” signals in Fig. 15 and 16, each segment is sequentially two additional clock pulses are saved, which occurs during the intervals T1, T1 + T2, etc., resulting in the time required to insert the field synchronization segment at the end of 416 frame segments without interrupting the data stream. In this example, the control unit 30 outputs segments that contain 832 symbols (ie 416 segments • 2 symbols / segment) and 832 symbol clocks, i.e., two less than in the case of the example illustrated in Fig. 15 Thus, the use of only one synchronization component advantageously increases the data transmission rate.

 The examples illustrated in FIG. 17 and 18 are similar to the examples depicted in FIG. 15 and 16, except that the integer N, related to the clock frequency of the bytes at the input and the clock frequency of the characters at the output, is "4", not 2. In particular, the symbol clock frequency (SC) is four times the clock input frequencies, as a result of which the signals "A", "B" and "C" are clocked at the frequency SC / 4, rather than SC / 2, as is the case in FIG. 15 and 16, and 209 segments follow between each component of the field synchronization. The example shown in FIG. 17 relates to the use of both segment synchronization components and MPEG synchronization components, and the example in FIG. 18 relates to the case of using the MPEG timing component as a segment timing component.

 The 8-level symbolic data signal (FIG. 12) arrives at a repetition rate of 10.76 million characters per second from block 50 to the output processor 18 shown in FIG. 2, where a small pilot signal is added to the suppressed RF carrier, thereby providing error-resistant carrier recovery in the receiver under some difficult reception conditions. The addition of a pilot signal is accompanied by the addition of a small (discrete) constant level signal to each data symbol and video signal synchronization. Using known signal processing methods, it is achieved that an 8-VSB type modulator (8-level signal modulator transmitted with a partially suppressed sideband) located in the output processor 18 receives a lattice-encoded composite data signal (with a pilot signal), filters and spectrally generates a signal suitable for transmission through a standard 6 MHz television channel, modulates (converts with increasing frequency) a data signal to an intermediate frequency carrier and transmits the resulting signal to a radio astotnoy carrier. In FIG. 13 shows (upper diagram) the spectrum of a video signal modulated with a partially suppressed sideband, in comparison with the standard 6 MHz channel spectrum of the National Committee for Television Systems (NTSC) system, as shown in the lower diagram.

 In the signal receiver with a partially suppressed sideband, the received signal is processed by the radio frequency tuning element 110 (Fig. 13a), which includes channel selection circuits and a mixer for generating a lower frequency signal. This signal is filtered at an intermediate frequency and synchronously detected to obtain a video signal according to signal processing methods. The video signal is corrected by block 114 to compensate for the amplitude and phase disturbances that occurred in the transmitting channel, and then undergoes trellis decoding, direct error detection / correction, and other processing of the signal by the video packet data processor 116 in the same way, which is the reverse of the processing carried out in transmitter (FIG. 12).

 In detail, block 116 is shown in FIG. 14. The decoded packetized video signal from the byte data coming out of block 116 is processed by the transport packet decoder 85, which performs the inverse operations performed by the transport processor 14 (FIG. 2) in the transmitter. The data of the video signal and the audio signal extracted by the transport decoder 85 are respectively processed by the video and audio circuits in block 122 to obtain an image and sound information suitable for reproduction.

 The data processing receiver shown in FIG. 14, performs the same operations as the transmitting data processing device (Fig. 12), but everything happens in the reverse order. The output data stream of the receiving system (output of byte data according to the MPEG standard) corresponds to the input data stream of the transmitter (Fig. 12) (input of byte data according to the MPEG standard).

 In FIG. 14, the input symbolic data stream (input of symbol data) corresponds to the symbolic data output data stream generated by the device of FIG. 12. This input symbolic data stream contains a relatively long field synchronization component located between groups of data packets of shorter duration, which respectively define adjacent data fields. Thus, the input signal of the receiver is characterized by an uneven data rate. This input stream of symbolic data of uneven speed is converted into a signal output byte data according to the MPEG standard, containing data packets arriving at a constant and uniform speed and separated by uniform inter-packet gaps. Such an output data stream contributes to successful data processing and data demultiplexing by the transport decoder 85. As in the case of the transmitter encoder, the output stream of byte data of uniform speed is seamless and the next without interrupting the data stream, which is achieved by data processing, which is the reverse processing in the transmitter / system the encoder described for FIG. 12.

 The stream of symbolic video data with an uneven speed, obtained after demodulation and correction, is fed to block 60, which, under the influence of the symbol clock frequency SC, performs the opposite operations performed by block 50 (Fig. 12). The symbol clock frequency SC is identical to the symbol clock frequency SC operating in the transmitter. The output symbolic data stream generated by block 60 is controlled by block 78, which detects the occurrence of control information passing during the synchronization intervals of the field, for example, information about the presence of the so-called “training” signal used by the previous corrector block 114 (Fig. 13a), and information on mode selection, among other information. This information is retrieved by block 78 and transmitted to the previous circuit according to the requirement of a particular system. Block 78 also provides a field marker signal, which is necessary for control unit 80 to chronize the field velocity, as will be described below.

 Block 60 correlates each 3-bit symbol with a 3-bit word, which is a trellis decoded into a 2-bit word decoder 62, acting together with block 64. Groups of four 2-bit information owls are converted from serial form to parallel form of 8 bits (1 byte) in series-parallel converter 68. Sequential words from the converter 68 are supplied to alternately acting segment memory devices 70 and 72. These storage devices are basically the same as the segment storage devices 26 (FIG. 12) and 28, except that the read and write are clocked in the reverse order, i.e. the read and write clocks of the storage devices 70 and 72 correspond to the write and read clocks of the storage devices 26 and 28. The data field segments stored in the storage devices 70 and 72 undergo temporary multiplexing at the field speed by the temporary multiplexer 74. The marker field signal generated by the generator unit 78 a torus 80 of the signal, chronizes the field velocity for the read / write control signals sent by block 80 to the storage devices 70 and 72, and chronically acts on the multiplexer 74. The marker field signal also causes the controller 80 to not write the field synchronization segment to the storage devices 70 and 72, as a result, the resulting output data stream is free from the field synchronization component.

 Block 74 multiplexes the output data packets from the storage devices 70 and 72 into a signal data stream that is free of the field synchronization component, as a result of which the data stream (output of MPEG byte data) from blocks 74 and 75 follows with a constant and uniform speed and with invariable and uniform interpackage gaps. In particular, the data stream corresponding to the output of MPEG byte data to the receiver (Fig. 14) is similar to the data stream corresponding to the input of MPEG byte data at the input of the transmitting system (Fig. 12). This is due to the characteristics of the receiving input stream of symbolic data along with the output byte clock frequency (SC / 2), which is an integer subharmonic of the input symbol clock frequency (SC). This responds to the feedback between the input and output clock frequencies in the transmitter / encoder. However, in both the transmitter and the receiver, the byte clock (SC / 2) is an integer subharmonic of the symbol clock (SC). The process of generating a data stream with a constant and uniform speed is facilitated by the correct selection of the read / write clock frequencies by the memory devices 70 and 72, along with the field speed multiplexing provided by block 74. Block 74 can, if desired, multiplex the symbol synchronization component selected from block 60 and directed by block 82 into the data stream.

 MPEG packets that include the MPEG synchronization component are recreated in the receiver before they are transferred to the transport processor 85. The MPEG synchronization component must be returned to the data stream if it was previously removed, and the synchronization component must be removed if it was previously inserted into the data stream. These operations are performed by the synchronous symbol detector and generator 82 in conjunction with the multiplexer 74. Block 82 senses the absence of the MPEG synchronization component and generates such a component as required. Block 74 multiplexes this synchronization component into a data stream. Block 82 also establishes the presence of the synchronization component in the data stream and makes it not there.

 The control signal generator 80 also provides an “RESOLVE” signal, which allows the transport decoder / processor 85 to receive and process MPEG standard byte data packets arriving at a constant and uniform speed from the direct error correction unit 75, for example, a Reed-Sollmon decoder. The transport decoder 85 performs the functions inverse to the functions produced by the transport processor 14 in the transmitter (FIG. 2) and responds to the byte clock frequency SC / 2, which is half the symbol clock frequency set by the clock generator 86. The transport processor 85 comprises various data processing and demultiplexing circuits, including service information analyzers, signal tracer circuits that respond to incoming service information, decompression circuits manufactured according to the MPEG standard, and other image and sound channel processors that output signals formatted as follows as required by the video sound processor 122 (FIG. 13a).

 Although in the preferred embodiments disclosed, the input byte clock and the output symbol clock are in an integer frequency relationship, the frequencies can also be in an integer ratio. In most cases, this seems less desirable due to the fact that it will then become necessary to use phase-locked loop circuits that will increase the cost and complexity of the system.

Claims (24)

 1. A system for processing a packetized digital data stream to obtain an output data stream representing structures from sequential data fields, each of which contains data and service information, containing input means for inputting a stream of data packets separated by inter-packet data gaps, means for supplying a service segment information of a field having a duration different from the duration of the inter-packet gaps within the data field, processing means for processing the data stream from means for supplying a field service information segment, for obtaining an output data stream representing a sequence of structures from data fields, each of which contains a service field information field and a data field containing a group of data segments, characterized in that the input means creates a data stream with certain constants and uniform inter-packet gaps for a plurality of data field structures having a size that speeds up the insertion of overhead information.  2. The system according to claim 1, characterized in that the field overhead segment has a duration longer than the gap between the packets, and the processing means provides an output data stream containing the field overhead segment without interrupting the data stream.  3. The system according to claim 1, characterized in that the constant and uniform interpackage gaps are a function of the duration of the segment with the service field information and the number of the mentioned data segments that make up the structure of the data field.  4. The system according to claim 1, characterized in that each group of data segments contains a certain number of data segments of a certain duration and each uniform inter-packet gap of the data field covers an interval containing the prescribed part of the interval occupied by the associated segment with the service information of the field.  5. The system according to claim 4, characterized in that each uniform inter-packet gap of the data field covers substantially equal parts of the associated interval of the service field segment so that the interval that is the same with respect to the existing interval of the field service field information accumulates after passing through each group data segments that make up the data field.  6. The system according to claim 1, characterized in that the field service information field contains synchronizing field information and the processing means further includes means for adding service components with package information to the data segments.  7. The system according to claim 6, characterized in that the processing means adds a service segment with field information to said data stream without interrupting the data stream.  8. The system according to claim 1, characterized in that the processing means comprises an input circuit responsive to an input clock frequency and an output circuit responsive to an output clock frequency, wherein the input and output clock frequencies are integer coupled.  9. The system of claim 8, wherein the input clock frequency is an even subharmonic of the output clock frequency.  10. The system of claim 8, wherein the input clock frequency is a byte clock, and the output clock frequency is a symbol clock.  11. A system for receiving a digital data stream, which is a sequence of data field structures, each of which includes a group of field data segments and a field service information segment containing information other than information contained in the field data segments, containing input means for inputting the data stream and processing means, characterized in that the processing means comprises means for removing service information from the data stream, issuing a processed packet upon receipt of the data stream The data stream is free of service information and contains data packets with constant and uniform inter-packet gaps and a constant and uniform data rate, and the system also contains decoding means for the processed data stream with a uniform data rate, designed to decode the processed data stream and obtain components of the signal.  12. The system according to claim 11, characterized in that each of the field data segments contains data and information about the service segment, while the field service information segment is characterized by a duration other than the duration of the service information segment.  13. The system according to claim 11, characterized in that the processing means provides a processed data stream without interrupting the data stream.  14. The system according to claim 11, characterized in that the constant and uniform gaps between the data packets are a function of the duration of the service information and the number of data segments that make up the data field.  15. The system according to claim 11, characterized in that each group of field data segments contains a certain number of data segments of a certain duration, and each inter-packet gap for the processed data stream covers an interval containing a portion of the interval intended for it, previously occupied by its associated service information.  16. The system of claim 15, wherein each inter-packet gap of the processed data stream covers substantially equal parts of the associated interval with overhead information.  17. The system according to claim 11, characterized in that the field service information field contains information about the synchronization of the field.  18. The system according to claim 11, characterized in that the processing means comprises an input circuit responsive to the input clock frequency (SC) and an output circuit responsive to the input clock frequency (SC / 2), the input and output clock frequencies are integer related.  19. The system of claim 18, wherein the output clock frequency (SC / 2) is an even subharmonic of the input clock frequency (SC).  20. The system of claim 18, wherein the input clock frequency is a symbol clock rate, and the output clock frequency is a byte clock frequency.  21. The system according to claim 11, characterized in that the processing means comprises a first storage device responsive to the data stream, a write clock frequency (SC / 4) and a read clock frequency (SC / 2), a second memory device responsive to data stream, to the write clock frequency (SC / 4) and to the read clock frequency (SC / 2), means for controlling the first and second memory devices at the field speed and means for combining the output data from the first and second memory devices.  22. The system according to p. 21, characterized in that the write clock frequency is a frequency that is an integer subharmonic of the read clock frequency.  23. The system according to item 21, wherein the combining means is a temporary multiplexer.  24. The system according to item 21, characterized in that it further comprises means for decoding data for the first and second storage devices and means for detecting and correcting errors, responsive to the output coming from the means of combining.

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