JP2953500B2 - Digital signal transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission system and a transmitter and a receiver used therefor, and more particularly to a time division multiplexing technique for a plurality of composite digital signals obtained by encoding a plurality of composite video signals. The present invention relates to a transmission system for transmitting a component digital signal on a transmission line for serial transmission using the same, and an improvement of a transmission device and a reception device used for the transmission system.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing an example of a conventional digital signal transmission system. As shown in FIG. 1, the conventional digital signal transmission system includes a time division multiplexer 30 and a time division demultiplexer 50 connected via a cable 40.
And a transmitting device 20 and a receiving device 60 are connected to each other.

[0003] A component serial digital signal is input to one input terminal 10 of a transmission device 20. The component serial digital signal is supplied to the decoder 21.
Then, using a second clock obtained by converting a clock in the parallel digital signal into a predetermined frequency, dummy data is added to the component parallel digital signal to generate a redundant parallel digital signal having a second sampling frequency. Generate a signal. The redundant parallel digital signal is converted into a serial signal and then alternately distributed to two output terminals one bit at a time by a switching signal obtained by multiplying the frequency of the second clock to a predetermined frequency. Is output as a pseudo second serial digital signal. At least two pseudo second serial digital signals are transmitted to a time division demultiplexer via a cable 40 from a time division multiplexer for time division multiplexing as a two-channel serial digital signal. A third signal extracted from the two pseudo second serial digital signals by a time division separator.
The two pseudo second serial digital signals are converted into one using a fourth clock obtained by multiplying the clock of
After converting to a serial digital signal of the system, it is converted to a redundant parallel digital signal. Thereafter, dummy data is deleted from the redundant parallel digital signal based on a signal obtained by dividing the fourth clock to a predetermined frequency, the component data is restored to a component parallel digital signal, and the component parallel digital signal is encoded into a component serial digital signal. Restore.

[0004]

A first problem with the conventional digital signal transmission method is that when a component serial digital signal is restored on the receiving side, a bit slip occurs in one of the two signals. When,
It is impossible to restore synchronization forever.
The reason is that two spurious second signals separated and generated from one component serial digital signal on the transmitting side are used.
This is because in the case of the serial digital signal, the synchronization signal originally superimposed on the signal is separated, and the conversion into the parallel digital signal is not performed normally.

[0005] The second problem is that even if the bit slip does not occur as described above, a low frequency phase change of the serial digital signal caused by a change in temperature in the device causes a difference between the two serial digital signals. If the phase relationship is lost and the phase is shifted by one or more bits, the receiving side cannot normally restore the component signal. The reason for this is that, similarly to the first problem, the pseudo second serial digital signal itself that has been separated into two has no synchronization information.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a digital signal transmission system in which a composite serial digital signal of a plurality of channels is time-division multiplexed and transmitted on one transmission line without any change in the internal structure of the system. An object of the present invention is to enable transmission of a signal having a transmission speed different from that of a serial digital signal. Another object of the present invention is to provide a transmitting device and a receiving device that provide stable operation by the above-described digital signal transmission system.

[0007]

According to the present invention, in a digital signal transmission system including a transmitting device and a receiving device, the transmitting device converts a component parallel digital signal and a 27 MHz clock from an input component serial digital signal. And a component serial / parallel conversion circuit (101) for outputting the component parallel digital signal and the 27 MHz signal.
A Y / C separation circuit (102) for receiving a clock and outputting a parallel signal and a synchronization detection signal, a transmission-side frequency divider (103) for receiving the 27 MHz clock and generating a 13.5 MHz clock obtained by dividing the frequency by 2; Receives 13.5 MHz clock and synchronizes it with 35/33 times frequency 1
Multiplying circuit for generating a 4.3 MHz clock (104)
And the 1 of the parallel signal from the Y / C separation circuit.
Writing with 3.5 MHz clock and 14.3 MHz
The transmitting side memory (105,
106) and a TRS output circuit (1) for inserting a frame pattern necessary for synchronization detection on the receiving side into the parallel signal.
07), a switching circuit (108) for combining the parallel signal and the frame pattern and outputting a pseudo composite parallel signal, and a composite parallel / serial conversion circuit for receiving the pseudo composite parallel signal and converting it to a pseudo composite serial digital signal (109, 110), wherein the receiving device converts the composite serial digital signal into a pseudo-composite parallel signal and simultaneously synchronizes with the pseudo-serial composite signal.
A composite serial / parallel conversion circuit (201, 201) that outputs a 4.3 MHz clock and outputs a detection signal when a TRS signal that is a frame pattern is detected.
02), a receiving-side frequency dividing circuit (203) that receives the 14.3 MHz clock and outputs a 33/35 frequency synchronized with the clock, and a control circuit that receives the synchronization detecting signal and controls writing of data to a memory. (204, 205),
A receiving memory (206, 207) controlled by the control circuit to perform writing at the 14.3 MHz clock and reading at the 13.5 MHz clock, data output from the receiving memory and the 13.5 MHz
A Y / C synthesis circuit (208) for receiving a clock and outputting a component parallel digital signal; and a component parallel / serial conversion circuit (209) for receiving and converting and outputting the component parallel digital signal to a component serial digital signal. A characteristic digital signal transmission system is obtained.

[0008]

[0009]

According to the present invention, the composite serial digital signal from the transmitting device is converted into a pseudo-composite parallel signal and simultaneously synchronized therewith.
A composite serial / parallel conversion circuit (201, 20) that outputs a 3 MHz clock and outputs a detection signal when detecting a TRS signal that is a frame pattern.
2) and a receiving-side frequency dividing circuit (2) that receives the 14.3 MHz clock and outputs a 33/35 frequency synchronized with the 14.3 MHz clock.
03) and a control circuit (204, 20) which receives the synchronization detection signal from the transmission device and controls the writing of data to the memory.
5), controlled by the control circuit, and
Reception-side memory (206, 207) for performing writing with a 1 MHz clock and reading with a 13.5 MHz clock
And the data output from the receiving side memory and the 13.5
A Y / C synthesizing circuit (208) for receiving the MHz clock and outputting a component parallel digital signal; and a component parallel / serial converting circuit (209) for receiving and converting and outputting the component parallel digital signal to a component serial digital signal. Thus, a receiving device characterized by the above is obtained.

Further, according to the present invention, the two pseudo second serial digital signals extracted in parallel by the time division separator are converted into redundant parallel digital signals, and a synchronization detection signal and a third clock are output. Second cereal /
A parallel conversion circuit, write control means for receiving the synchronization detection signal, controlling the writing of the redundant parallel digital signal to the memory and the reading of the parallel digital signal excluding the synchronization pattern, and dividing the frequency from the third clock to a clock of a predetermined frequency A frequency dividing circuit for generating a second clock, and a receiving side memory which is controlled by the control means based on the second and third clocks and which writes a redundant parallel digital signal and reads out a second parallel digital signal excluding a synchronization pattern A Y / C synthesizing circuit for receiving the two kinds of second parallel digital signals output in parallel from the receiving side memory and restoring the first parallel digital signal, and converting the first parallel digital signal to a first serial digital signal; A second parallel / serial conversion circuit for restoring a digital signal. Receiving device is obtained to.

According to the present invention, after the first serial digital signal of the first transmission rate is converted into the first parallel digital signal of the first sampling frequency, the first serial digital signal is converted to the first parallel digital signal.
Is separated into a second parallel digital signal and a synchronization detection signal, and the second clock is generated by dividing the first clock in the first parallel digital signal. 2 are respectively written in a memory, and read out as a third parallel digital signal from the memory using a third clock obtained by multiplying the frequency of the second clock to a predetermined frequency, and the synchronization detection signal is read out. Dummy data is inserted into the third parallel digital signal by a switcher that operates as a switching signal, a redundant parallel digital signal is generated and converted into a serial digital signal, and at least two pseudo second serial digital signals are generated. Time-division multiplexing as a 2-channel serial digital signal The signal is transmitted from the division multiplexer to the time division separator via the transmission path, and the two pseudo second serial digital signals are extracted in parallel by the time division separator, and are extracted in parallel from the time division separator. After converting the two pseudo second serial digital signals into a redundant parallel digital signal, a synchronization pattern is formed from the redundant parallel digital signal based on the third clock extracted from the redundant parallel digital signal and the synchronization detection signal. The deleted portion is written to the memory, read from the memory using the fourth clock obtained by dividing the third clock to a predetermined frequency, and restored to the first parallel digital signal.
A digital signal transmission method is characterized in that the first parallel digital signal is encoded and restored to a first serial digital signal.

The time division multiplexer has a second serial digital signal input terminal having a second transmission rate of at least three or more channels, of which two pseudo input terminals are connected to two pseudo input terminals. It is preferable that the second serial digital signal is input and time-division multiplexed with the second serial digital signal into one system.

[0014]

According to the present invention, the transmitting device converts the first serial digital signal of the first transmission rate into a pseudo second serial digital signal of the second transmission rate from two output terminals and outputs the converted signal. However, since the synchronization signal is included in this signal and the signal is output, the second serial digital signal of the second transmission rate received from the two input channels in the receiving device has a phase shift or a bit shift. Synchronization can be restored even if it cannot be correctly converted to a parallel digital signal due to a shift.

[0015]

Next, an embodiment of the present invention will be described. FIG. 1 shows a configuration diagram of a digital signal transmission system according to an embodiment of the present invention. In the figure,
The transmitting device 1 converts one component serial digital signal input from the input terminal 100 into two composite serial digital signals, and
1 and 112 to the time division multiplexer 300. The time-division multiplexer 30, the cable 40 and the time-division separator 50 constitute the conventional composite serial digital signal time-division transmission system described above.

The receiving device 2 restores the two composite serial digital signals input from the time division separator 50 via the input terminals 210 and 211 into a single component serial digital signal and outputs it to the output terminal 200.

Here, the component serial digital signal is obtained by converting the luminance signal Y to a sampling frequency of 13.5 MHz.
After sampling at z, the digital luminance signal obtained by quantization and encoding with the quantization bit number of 10 bits and two types of color difference signals (color signals) CR and CB are separately sampled at a sampling frequency of 6.75 MHz, respectively. The two types of digital chrominance signals obtained by quantization and encoding with the quantization bit number of 10 bits correspond to, for example, a first digital chrominance signal, a digital luminance signal, a second digital chrominance signal, and a digital luminance signal in this order. It is a serial signal that is serially combined in time series as a cycle, and its transmission speed is 270 Mbps. It should be noted that the component parallel digital signal is composed of a digital luminance signal and 2
A kind of digital color difference signal is a parallel signal transmitted in parallel.

On the other hand, the sampling serial frequency of the composite serial digital signal is an analog composite video signal (composite signal) which is a multiplexed signal composed of a luminance signal and a carrier chrominance signal which is multiplexed in a high frequency region of the luminance signal. After sampling at 3 MHz, it is a serial signal obtained by serially combining bit-by-bit composite parallel digital signals obtained by quantizing and encoding with 10-bit quantization bits, and the transmission speed is 143 MHz.
z.

The transmitting apparatus 1 includes a first serial / parallel conversion circuit 101, a Y / C separation circuit 102, and a two-frequency dividing circuit 10.
3, 35/33 multiplication circuit 104, transmission side memories (1H memory) 105 and 106, synchronization pattern generation circuit 10
7, a switching circuit 108, and parallel / serial conversion circuits 109 and 110. The serial / parallel conversion circuit 101 decodes the input component serial digital signal and outputs a component parallel digital signal. During the output of the serial / parallel conversion circuit 101, a repetition frequency of 27 MHz extracted from the component serial digital signal is output.
The clock of z (CLK) is also included.

The Y / C separation circuit 102 separates the component parallel signal into a 13.5 MHz component parallel luminance signal and a component parallel color difference signal.
At the same time, a synchronization detection signal is output.

The divide-by-2 circuit 103 receives a 27 MHz clock as an input, divides the frequency by 2 and outputs a 13.5 MHz clock. The 35/33 multiplication circuit 104 is 1
It receives a 3.5 MHz clock as an input and outputs a 14.3 MHz clock 35/33 times the frequency. Here, the frequency of 14.3 MHz corresponds to the sampling frequency of the composite parallel signal.

The transmission side memories 105 and 106 store the above 1
The component parallel luminance signal and the component parallel color difference signal are written using 3.5 MHz as a clock, and 14.3 MHz from the 35/33 multiplier 104 is written.
A clock is read and read is performed as a clock.

In the synchronization pattern generation circuit 107, the above 1
A synchronization pattern is generated using a 4.3 MHz clock as a sampling frequency, and a switching circuit 108 uses the synchronization detection signal as a switching signal to switch between the data read from the transmission side memories 105 and 106 and the synchronization pattern, thereby sampling the 14.3 MHz clock. A pseudo composite parallel digital signal having a frequency is generated.

First parallel / serial conversion circuit 109
Converts the pseudo composite parallel digital signal into a pseudo composite serial digital signal.

The receiving apparatus 2 includes second serial / parallel conversion circuits 201 and 202, and a 33/35 frequency dividing circuit 2
03, memory write control means 204 and 205, reception side memories (1H memory) 206 and 207, Y / C synthesis circuit 208, and second parallel / serial conversion circuit 2
09 is included. The second serial / parallel conversion circuit 201 outputs the transmission speed 1 input via the input terminal 210.
A 43 MHz pseudo composite serial digital signal is converted into a pseudo composite parallel digital signal having a sampling frequency of 14.3 MHz, and a 14.3 MHz clock is output. 33/35
The frequency divider 203 receives a 14.3 MHz clock and
Generate a 3.5 MHz clock. Write control means 20
In step 4, a write control signal for the memory is generated upon receiving the synchronization detection signal. The receiving memories 206 and 207 receive this control signal and write based on a 14.3 MHz clock.
Reading is performed based on the 3.5 MHz clock, and second component parallel digital signals (two types of luminance signal and color difference signal) are generated in parallel.

The Y / C synthesizing circuit 208 synthesizes the second component parallel digital signals obtained in parallel and restores them to the first component parallel digital signal, and the second parallel / serial converting circuit 209 outputs the first component parallel digital signal.
Is restored to the first component serial digital signal, and the component serial digital signal is output to the output terminal 200.

In the digital signal transmission system having such a configuration, a synchronization pattern is originally superimposed on the component serial digital signal. By superimposing the same synchronization pattern on the pseudo composite serial digital signal as described above,
By maintaining the synchronization of two parallel pseudo-composite serial digital signals, transmission of a single component serial digital signal is made more stable.

Next, the operation of the digital signal transmission system of FIG. 1 will be described. The component serial digital signal input to the input terminal 100 is supplied to a first serial / parallel conversion circuit 101 to be converted into a component parallel digital signal, and supplied to the Y / C separation circuit 102 in 10-bit parallel. The 27 MHz clock extracted from the component serial digital signal itself by the serial / parallel conversion circuit 101 is supplied to the divide-by-2 circuit 103, and the frequency is divided by 2 to 13.5 MHz. In addition, this 13.5 MH
The clock of z is supplied to the 35/33 frequency multiplying circuit 104 and is set to 14.3 MHz.

The Y / C separation circuit 102 converts the component parallel digital signal to a sampling frequency of 13.5M.
Hz component parallel digital luminance signal and component parallel digital color difference signal are supplied to the transmission side memories 105 and 106. At the same time, Y
The / C separation circuit 102 extracts a synchronization signal from the component parallel digital signal and outputs a detection signal to the switching circuit 108. 13.5 output component parallel digital signals of the Y / C separation circuit 102 for one horizontal scanning period (1H) are sent to the transmission side memories 105 and 06.
14.3 MHz while writing based on a MHz clock
z is read by the clock of z, and the switching circuit 10
Supply to 8. The switching circuit 108 switches the data read from the transmission side memories 105 and 106 and the synchronization pattern from the synchronization pattern generation circuit 107 according to the synchronization detection signal, and converts the data into parallel / serial conversion circuits 109 and 1 as pseudo composite parallel digital signals.
Supply 10 The parallel / serial conversion circuits 109 and 110 output two types of pseudo composite parallel digital signals from the output terminals 111 and 112 in parallel as pseudo composite serial digital signals.

Here, the term "pseudo composite serial digital signal" means that the transmission speed is 143 Mbps, which is equivalent to that of the composite serial digital signal. This means that the signal has a format different from that of the original composite serial digital signal.

The two composite pseudo serial digital signals having a transmission speed of 143 Mbps taken out from the output terminals 111 and 112 are supplied to the N
Are input to two of the two input terminals, where they are time-division multiplexed with the composite serial digital signals input to the other N-2 input terminals, and then time-division-multiplexed via a cable 40. The two pseudo-composite serial digital signals having a transmission speed of 143 Mbps are taken out at output terminals 210 and 211.

One of the pseudo composite serial digital signals input to the input terminals 210 and 211 is supplied to serial / parallel conversion circuits 201 and 202 to be converted into pseudo composite parallel digital signals and received by the receiving memories 206 and 207. At the same time, detection of a synchronization pattern and extraction of a 14.3 MHz clock are performed. 14.3MHz clock is 33/3
The clock is supplied to the divide-by-5 circuit 203 to generate a 13.5 MHz clock. In the receiving side memories 206 and 207, 1
Using the 4.3 MHz clock as a write clock, a pseudo composite parallel digital signal is written based on the control signal generated from the synchronization detection signal by the write control means 204 and 205, and at the same time 13.
Reading is performed by a 5 MHz clock and supplied to the Y / C synthesis circuit 208 as a second component parallel digital signal. At this time, the synchronization pattern added on the transmission side is not read from the memory. The Y / C synthesizing circuit 208 restores the first component parallel digital signal from the two parallel second component parallel digital signals and supplies it to the parallel / serial conversion circuit 209. Parallel / serial conversion circuit 209
Receives this signal, restores it to a component serial digital signal, and outputs it to the output terminal 200.

As described above, according to the digital signal transmission system of FIG. 1, since the synchronization pattern is superimposed on each of two parallel pseudo composite serial digital signals, even if one of them is out of synchronization, the maximum is obtained. Synchronization can be restored with a delay of 1H.

The present invention is not limited to the digital signal transmission system shown in FIG. 1. For example, in addition to using the cable 40 as an example of a transmission line, an optical fiber cable, a radio transmission line, and the like can be used. It is. Although the digital signal to be transmitted has been described as a composite signal and a component signal, the present invention is not limited to this, and the present invention is also applicable to the transmission of digital signals such as data.

[0035]

As described above, according to the present invention,
Even when a first serial digital signal at a first transmission rate is transmitted using a plurality of transmission paths for transmitting a second serial digital signal at a second transmission rate, the first serial digital signal is synchronized with each of the second serial digital signals. Since the signal is superimposed, it is possible to recover from the loss of synchronization, and more stable transmission becomes possible.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital signal transmission system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an example of a conventional digital signal transmission system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Transmission device 100 Input terminal 101 Serial / parallel conversion circuit 102 Y / C separation circuit 103 2 frequency dividing circuit 104 35/33 multiplication circuit 105, 106 Transmission side memory 107 Synchronization pattern generation circuit 108 Switching circuit 109, 110 Parallel / serial conversion Circuits 111, 112 Output terminal 30 Time division multiplexer 40 Cable 50 Time division separator 2 Receiver 210, 211 Input terminal 201, 202 Serial / parallel conversion circuit 203 33/35 frequency dividing circuit 204, 205 Writing control means 206, 207 Reception side memory (1H memory) 208 Y / C synthesis circuit 209 Parallel / serial conversion circuit 200 Output terminal

Claims (5)

(57) [Claims] 1. A digital signal transmission system including a transmission device and a reception device, wherein the transmission device outputs a component parallel digital signal and a 27 MHz clock from an input component serial digital signal, and a component serial / parallel conversion circuit. A Y / C separation circuit that receives the component parallel digital signal and the 27 MHz clock and outputs a parallel signal and a synchronization detection signal, and receives the 27 MHz clock and divides the frequency by 13.5.
A transmitting-side frequency dividing circuit for generating a MHz clock;
35/33 receiving and synchronizing with 3.5 MHz clock
A multiplying circuit for generating a 14.3 MHz clock having a double frequency;
Writing with 3.5 MHz clock and 14.3 MHz
A transmitting side memory for reading out with a clock, a TRS output circuit for inserting a frame pattern necessary for synchronization detection on a receiving side into the parallel signal, and a pseudo composite parallel signal by synthesizing the parallel signal and the frame pattern And a composite parallel / serial conversion circuit for receiving the pseudo-composite parallel signal and converting it to a pseudo-composite serial digital signal, wherein the receiving device receives the composite serial digital signal and converts it to a pseudo-composite parallel signal At the same time, a composite serial / parallel conversion circuit that outputs a 14.3 MHz clock synchronized therewith and that outputs a detection signal when a frame pattern TRS signal is detected, and receives the 14.3 MHz clock. A receiving-side frequency divider that outputs a 33/35 frequency synchronized with the received signal, a control circuit that receives the synchronization detection signal and controls the writing of data to a memory, and the 14.3 MHz Writing with clock and 1
13. A receiving-side memory that performs reading with a 3.5 MHz clock, data output from the receiving-side memory, and 13.
A digital signal, comprising: a Y / C synthesis circuit receiving a 5 MHz clock and outputting a component parallel digital signal; and a component parallel / serial conversion circuit receiving and converting the component parallel digital signal into a component serial digital signal. Transmission system. 2. A composite serial digital signal from a transmitting device is received and converted into a pseudo composite parallel signal, and at the same time, a 14.3 MHz clock synchronized with the signal is output. When a TRS signal which is a frame pattern is detected, a detection signal is output. Output composite serial /
A parallel conversion circuit, a receiving-side frequency dividing circuit that receives the 14.3 MHz clock and outputs a 33/35 frequency synchronized with the clock, and a control that controls the writing of data to a memory in response to a synchronization detection signal from a transmitting device. A receiving memory controlled by the control circuit to perform writing with the 14.3 MHz clock and reading with the 13.5 MHz clock; and a data output from the receiving memory and the 13.5 MHz clock. A receiving device comprising: a Y / C synthesis circuit that outputs a receiving component parallel digital signal; and a component parallel / serial conversion circuit that receives and converts the component parallel digital signal into a component serial digital signal. 3. A second serial / digital converter for converting two pseudo second serial digital signals extracted in parallel by a time division separator into a redundant parallel digital signal and outputting a synchronization detection signal and a third clock. A parallel conversion circuit, and write control means for receiving the synchronization detection signal, controlling the writing of the redundant parallel digital signal to the memory and the reading of the parallel digital signal excluding the synchronization pattern,
The frequency is divided from the third clock to a clock of a predetermined frequency,
A frequency dividing circuit for generating a redundant clock and a second pattern except for a synchronous parallel pattern and writing of a redundant parallel digital signal under the control of the control means based on the second and third clocks.
A receiving memory for reading the parallel digital signal of
A Y / C synthesizing circuit for receiving two kinds of second parallel digital signals output in parallel from the receiving side memory and restoring them into a first parallel digital signal, and converting the first parallel digital signal into a first serial digital signal And a second parallel / serial conversion circuit for restoring the data. 4. After converting a first serial digital signal of a first transmission rate into a first parallel digital signal of a first sampling frequency, the first parallel digital signal is synchronized with the second parallel digital signal. The second parallel digital signal is written into a memory using a second clock generated by dividing the first clock in the first parallel digital signal, and the second parallel digital signal is written into a memory. The third parallel digital signal is read from the memory as a third parallel digital signal using a third clock obtained by multiplying the frequency of the second clock to a predetermined frequency, and the synchronous detection signal is operated as a switching signal by the switcher. Dummy data is inserted into the signal, a redundant parallel digital signal is generated, and this is A time-division multiplexer which converts the at least two pseudo second serial digital signals into a two-channel serial digital signal as a two-channel serial digital signal, and transmits the resulting signal to a time-division separator via a transmission path;
The two pseudo second serial digital signals are extracted in parallel by the time division separator, and the redundant parallel digital signal is extracted from the two pseudo second serial digital signals extracted in parallel from the time division separator. After that, based on the third clock extracted from the redundant parallel digital signal and the synchronization detection signal, the portion where the synchronization pattern is deleted from the redundant parallel digital signal is written to the memory, and the third clock is divided into a predetermined frequency. Digital data read out from a memory using the fourth clock that has been rotated, restored to a first parallel digital signal, and encoded into the first serial digital signal to be restored to a first serial digital signal. Signal transmission method. 5. The time division multiplexer has a second serial digital signal input terminal having a second transmission rate of at least three or more channels, of which two pseudo input terminals are connected to two channel input terminals. 5. The digital signal transmission method according to claim 4, wherein the second serial digital signal is input and time-division multiplexed together with the second serial digital signal into one system.