JPH0622287A - Video signal multiplex transmitter - Google Patents

Abstract

PURPOSE:To reduce the scale of the circuit operated at a high speed by adding a word synchronization code at every channel individually at a timing synchronized with each video input. CONSTITUTION:An input n-channel video signal is divided in the unit of one horizontal scanning period and written in a memory by synchronizing with the input video signal, the signal is read by arranging only a clock rate without synchronizing a signal of n-channel, thereafter the same word synchronization code and an ID code different from a channel are added to each memory output of n-channels, the n-channel parallel signal is converted into a serial signal of n-channel and the result is further converted into one system of serial signal. When input composite video signals are composed of two channels A, B and inputted from input terminals 1, 2, the circuit to be operated at a high speed is only a 2nd parallel/serial conversion circuit 16 on the sender side and a shift register circuit and a 1/2 frequency division counter circuit being components of the 1st serial/parallel conversion circuit only are required on a receiver side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission apparatus for transmitting asynchronous multi-channel video signals such as a plurality of component color TV signals at high speed.

[0002]

2. Description of the Related Art In recent years, higher speed digital signal transmission has become possible with the practical use of optical fiber cables and the like. Therefore, the number of cases in which output signals of a plurality of television cameras and the like are collectively transmitted as one serial signal is increasing. When transmitting a digital signal in the form of a serial signal, it is usually necessary to add a word synchronization code for a mark that the receiving side knows the beginning of the data to a data break such as a blanking period of a video signal. There is. Moreover, it is difficult to multiplex signals having different rates into a serial signal. Therefore, according to the conventional technology, when multiplexing and transmitting such asynchronous multi-channel video signals, a large-capacity memory such as a frame synchronizer is used to synchronize each video signal and then A method of adding a word synchronization code and converting into a serial signal is adopted.

As an example of a conventional technique, a block diagram of a transmission section of an A / B 2-channel asynchronous video signal multiplex transmission apparatus is shown in FIG. 2, and this operation will be briefly described below. The input video signals applied from the two input terminals A and B are converted into parallel digital signals of m bits for each channel by the two A / D converters 21 and 22, respectively. Further, the sync separation circuits 23 and 24 extract horizontal and vertical sync pulses and a pixel clock of each channel from the input video signal. The memory write address controllers 25 and 26 output write addresses with the horizontal and vertical synchronizing pulses and the pixel clock as reference timings, and write the digitized video signals in the frame memories 27 and 28.

On the other hand, when reading from the two frame memories 27 and 28, a common read address controller 30 is used with the output of the reference synchronizing signal generating circuit 29 as a reference timing.
Output controlled. By doing so, the asynchronous input video signal shown by the analog signal image in (1) of FIG.
The output of one frame memory is synchronized as shown in (2) of FIG. The signals thus synchronized are
A parallel / serial conversion circuit, which is sent to the word synchronization code adding circuit 31 and adds a word synchronization code for a mark for knowing the word break on the receiving side to a data break such as a blanking period of a video signal. It was converted to a serial signal at 32. As a supplementary explanation of the meaning of the word synchronization code, a 12-bit code such as 111100001111 is used as this code, and it is defined that the beginning of the word starts immediately after this code. It is something. The receiving device detects this word synchronization code from the transmitted serial signal and restores the original parallel signal.

[0005]

As described above, the conventional method requires a large-capacity frame memory to multiplex and transmit video signals. Therefore, there is a problem in that the size and cost of the transmitting device cannot be reduced.
Further, in the conventional method, on the transmission side, many parallel signals are converted into serial signals at once, and on the reception side, it is necessary to detect the word synchronization code and then convert the serial signals into many parallel signals at once. The circuit that operates at high speed is large in scale, and there are problems in terms of power, cost, stability, and the like. It is an object of the present invention to eliminate these drawbacks, eliminate the need for a large-capacity memory on the transmission side, and realize a video signal multiplex transmission device capable of significantly reducing the scale of a circuit operating at high speed.

[0006]

In order to achieve the above-mentioned object, the present invention provides n memories for respectively inputting n-channel asynchronous video signals and storing them for at least one horizontal scanning period, and each of the n memories. Means for generating individual memory write clocks and write address control signals synchronized with the horizontal synchronizing signal of the video signal input, and means for generating a common read clock having a frequency higher than any of the n clocks for memory reading. A means for generating n read address control signals which are delayed from the individual write addresses of the n channels by a predetermined time and are synchronized with a common read clock; and the same word synchronization code for each memory output of the n channels. A means for adding a different ID code depending on the channel, and n channel parallel signals are converted into serial signals respectively. Means for obtaining a serial signal channel,
It is configured to further include means for converting the n-channel serial signal into a one-system serial signal and transmitting the serial signal.

[0007]

According to the present invention, the input n-channel video signal is divided into units of one horizontal scanning period and written in the memory in synchronization with the input video signal, and only the clock rate is adjusted without synchronizing the n-channel signals. The same word sync code and different ID code depending on the channel are added to each memory output of the n-channel, and the parallel signal of the n-channel is once converted into the serial signal of the n-channel. Configuration to convert to serial signal of
That is, by adopting the method of individually adding the word synchronization code for each channel at the timing synchronized with each video input,
It eliminates the need to synchronize video signals between channels and eliminates the need for a large-capacity memory on the transmission side by simply matching the data rate with a small-capacity memory such as a line memory. It is possible to reduce the scale of a digital circuit that operates at high speed, which is required when converting into one serial signal and when restoring the serial signal into an n-channel video signal on the receiving side.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, and this operation will be described in detail below. In the following description, the case where the input composite video signal is the A and B2 channels is taken as an example.
The composite video signals of the A and B2 channels are input from the input terminals 1 and 2 and sent to the respective A / D conversion circuits 3 and 4 and the sync signal separation circuits 5 and 6. The sync signal separation circuits 5 and 6 reproduce a clock and a horizontal sync signal which are synchronized with the respective input video signals. The A / D converters 3 and 4 convert the analog input video signal into a digital signal in synchronization with this clock. Needless to say, this A / D converter is not necessary when the input signal is a digital signal in advance.

Next, the outputs of the A / D converters 3 and 4 are line FIFO (Firs) for storing the video signal for one horizontal scanning period or more.
t In First Out) Added to the input ports of memories 7 and 8. The FIFO memories 7 and 8 will be briefly described below.
This is the input and output port 41, 4 as shown in FIG.
3, memory cell 42, write address pointer 44,
This memory is composed of a read address pointer 45 and is capable of simultaneously performing asynchronous reading and writing by adding respective clocks for writing and reading and a reset signal.

The clocks and horizontal sync signals output from the sync signal separation circuits 5 and 6 are applied to the write clock and reset terminals of the memories 7 and 8, and the read clock terminal has a frequency higher than that of the write clock of either channel. If the clock generated by the high read clock generation circuit 9 and the write reset signal are delayed by the clock synchronization circuits 10 and 11 for a certain time at the reset terminal, and a signal synchronized with the read clock is added,
As shown in (1) of FIG.
The A / D conversion output of the B2 channel is stored in the two memories 7, 8
At the output, the output is converted into the output shown in (2) of FIG. 6 which is time-axis compressed at the same output rate and in units of one horizontal scanning period. Here, as a precaution, a specific configuration example of a clock synchronization circuit that generates a reset signal, a synchronization signal, and the like will be shown. As shown in FIG. 4, this is a counter 51 having a reset input and a decoder for decoding this output. It can be easily configured with 52.
The outputs of the memories 7 and 8 are next synchronized and the ID code addition circuit 1
2 and 13 and, as shown in (3) of FIG. 6, a sync code common to each channel and an ID code different for each channel are added to the head portion of the video signal, and each first parallel / serial conversion is performed. It is converted into a serial signal by the circuits 14 and 15. The two-channel serial signals are converted by the second parallel / serial conversion circuit 16 into one series of serial signals and transmitted.

Next, an example of a circuit for receiving the signals multiplexed by the above method is shown in FIG. 7 and its operation will be described. The reception interface circuit 61 receives the data transmitted through the transmission line, Regenerate serial data and clock. The serial data and the clock are sent to a serial IN / parallel OUT shift register 62 and a first serial / parallel conversion circuit including a divide-by-2 counter 63. Here, the serial data is connected to the serial IN terminal 62-1 of the shift register 62, the clock before frequency division is connected to the serial clock terminal 62-2, and the clock after frequency division is connected to the parallel load clock terminal 62-3. . In this way, the parallel OUT terminal 6 of the shift register 62
From 2-4, the data of the A and B2 channels are output in parallel at a rate down to ½ of the original serial data.

However, in this serial / parallel conversion, A, which corresponds to a break of a word of serial data,
Since the serial signal is simply parallelized without determining where the B2 channel delimiter is, it is not determined which of the two parallel OUT terminals outputs the A and B channel signals. Usually, in order to confirm this, a word synchronization code is added when the second parallel / serial conversion of the transmission unit is performed, and the reception unit detects this from the received serial data, It is necessary to reset the frequency division counter 63. However, since the word sync code detection circuit is usually composed of a multi-stage shift register and a data coincidence determination circuit, this increases the number of circuits that must operate at high speed. Therefore, in the present invention, the following method enables the subsequent processing without determining the output channel. That is, the two serial signals output from the parallel OUT terminal of the shift register 62 are added to the two second serial / parallel conversion circuits 64 and 65. As described above, these two serial / parallel conversion circuits 64,
The channel of the signal input to each of the channels 65 is not determined. However, since the word synchronization code common to each channel is added in the transmitting unit, serial data can be obtained in parallel from the output regardless of which channel the serial signal is input.

Next, of the outputs obtained in parallel, the output of the serial / parallel conversion circuit 65 is sent to the channel ID determination circuit 66, the channel ID code added by the transmission unit is read, and this signal is output to which channel. It is determined whether it is a signal. The serial / parallel conversion circuit 6
Only the output of No. 5 is sent to the channel ID judging circuit 66 because if one of the two channels can be judged, the other will be decided by itself, and the serial / parallel conversion circuit 6
The output of the serial / parallel conversion circuit 64 may be used in place of 5, to make the determination. Also, the second serial /
The outputs of the parallel conversion circuits 64 and 65 are sent to a switching circuit 68 having two channels of parallel inputs and two channels of parallel outputs. Also, the channel ID
The output of the determination circuit 66 is sent to the switching control circuit 67. Then, the switching control circuit 67 controls the switching circuit 68 so that the output of the switching circuit 68 becomes A and B channels in order from the top.

By using the multiplexing method of the present invention as described above, it is possible to obtain the parallel data of the correct channel without the word synchronization detection at the receiving side during the first serial / parallel conversion. As described above, when the present invention is used, the memory capacity required on the transmitting side is only one horizontal line, and the circuit operating at high speed has the second memory on the transmitting side.
The parallel / serial conversion circuit 16 of FIG. 3 and the shift register circuit 62 and the divide-by-two frequency dividing circuit circuit 63 which form the first serial / parallel conversion circuit on the receiving side are all necessary. It can be composed of a low-speed circuit that operates at a rate of. Incidentally, if the data transmitted in this way is D / A converted as it is, the jitter may become a problem, so that the receiving side device usually needs the frame synchronizers 69 and 70 for removing the jitter. However, in such a video signal transmission system, it is generally necessary to output the video signal when the transmission rate is fixed or in synchronization with control from an external system.
As in the conventional method, there are many cases in which the frame synchronizer is required on the receiving side even when the frame synchronizer is on the transmitting side. Further, in the above description, the number of channels of the video signal is set to 2 for simplification of description, but even if this number is 3 or more, the effects of the present invention can be obtained with the same configuration.

[0015]

As described above, the use of the present invention eliminates the need for a large-capacity memory on the transmission side, and also makes it possible to greatly reduce the scale of a circuit that operates at high speed for both transmission and reception. The problem that the cost was high,
Since there are many high-speed operation circuits, a large amount of power is required, and it is possible to solve the problem that stability is also a problem.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional transmission unit.

FIG. 3 is a diagram illustrating a structure of a FIFO memory used in the present invention.

FIG. 4 is a diagram illustrating a configuration example of a circuit that generates a reset signal, a synchronization signal, and the like.

FIG. 5 is an input / output timing chart of a conventional video synchronization circuit.

FIG. 6 is a timing chart of video signal rate equalization and synchronization ID code addition according to the present invention.

FIG. 7 is a diagram illustrating an example of a device that receives a signal transmitted by the device of the present invention.

[Explanation of symbols]

5,6 Sync signal separation circuit, 7,8 line memory, 1
0,11 clock synchronization circuit, 12,13 synchronization, I
D code addition circuit, 14 to 16 parallel / serial conversion circuit, 61 reception interface, 62 shift register, 63 2 frequency division counter, 64, 65 serial /
Parallel conversion circuit, 66 channel ID determination circuit, 67
Switching control circuit, 68 Switching circuit, 6
9,70 frame synchronizer.

Claims (1)

[Claims] 1. An n number of memories for inputting n-channel asynchronous video signals and storing them for at least one horizontal scanning period, and an individual memory write in synchronization with a horizontal synchronizing signal of each of the n video signal inputs. Means for generating a clock and write address control signal, means for generating a common read clock having a higher frequency than any of the n clocks for reading the memory, and a fixed time delay from the n-channel individual write address and A means for generating n read address control signals synchronized with the common read clock, a means for adding the same word synchronization code and an ID code different depending on the channel to each memory output of the n channel, and a means for adding the n channel. Means for converting parallel signals into serial signals to obtain n-channel serial signals, and the n-channel The video signal multiplex transmission device, further comprising means for converting the serial signal of 1) into a serial signal of one system and transmitting the serial signal.