JP2573766B2 - Video signal transceiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal transmitting / receiving apparatus for time-division multiplexing two-channel digital video signals and transmitting them as serial signals.

[0002]

2. Description of the Related Art In recent years, development of digital video equipment such as a digital VTR has been activated. Along with this, the development of a video signal transmitting device and a video signal receiving device for transmission between digital video devices has been activated, and communication signal processing technology has been remarkably developed.

As a conventional video signal transmitting device and video signal receiving device, for example, there is a device that serially transmits a composite video signal in a digital manner. Hereinafter, a conventional video signal transmitting apparatus will be described.

FIG. 4 is a block diagram of the conventional video signal transmitting apparatus. In FIG. 4, 33 is a video signal input terminal,
34 is a limiter, 35 is a horizontal synchronization detection circuit, 36 is a synchronization signal generation circuit, 37 is a selection circuit, 38 is a parallel / serial converter, 39 is an output circuit, and 40 is a transmission output terminal.

[0005] The operation of the video signal transmitting apparatus thus configured will be described below. First, a composite digital video signal having a sampling frequency of 14.3 MHz and a quantization of 10 bits is input from the video signal input terminal 33. In the limiter 34, the upper limit of the 10-bit signal input from the video signal input terminal 33 is 3FBh (h is
Hexadecimal number), the lower limit is 004h, 10
Outputs a bit signal. The horizontal synchronization detection circuit 35 detects a horizontal synchronization pulse from the 10-bit signal output from the limiter 34, and outputs a horizontal synchronization signal indicating a horizontal synchronization period for each line. In the synchronizing signal generating circuit 36, based on the horizontal synchronizing signal output from the horizontal synchronizing detecting circuit 35, a limiter 34 of 3FFh, 000h, 000h after 5 cycles of the sampling clock from the start of the horizontal synchronizing period of the video signal.
The communication synchronization signal of the value prohibited by is output. In the selection circuit 37, based on the horizontal synchronization signal output from the horizontal synchronization detection circuit 35, three words for 5 words after the sampling clock from the beginning of the horizontal synchronization period of the video signal are 10-bit signals output from the synchronization signal generation circuit 36. And outputs a 10-bit signal from the limiter 34 during other periods. parallel/
The serial converter 38 sequentially converts the 10-bit signal output from the selection circuit 37 from the LSB to a 1-bit serial signal and outputs the signal. The 1-bit serial signal output from the parallel / serial converter 38 is a bit string as shown in FIG. Here, A _m represents a group of data of word units, m denotes a temporal position of the start of m = 0 is a horizontal synchronizing period by an integer. The output circuit 39 performs self-synchronous scrambling on the 1-bit signal output from the parallel / serial converter 38 so that the coaxial cable can be driven.
The DC component of the signal is removed, amplified, and output to the transmission output terminal 40.

Next, a conventional video signal receiving apparatus will be described. FIG. 5 shows a block diagram of a conventional video signal receiving apparatus. In FIG. 5, 41 is a reception input terminal, 42 is a waveform equalizer, 43 is a code converter, 44 is a synchronization circuit, 45 is a serial / parallel converter, 46 is a hold circuit, and 47 is a video signal output terminal. .

[0007] The operation of the video signal receiving apparatus thus configured will be described below. First, the reception signal input from the reception input terminal 41 is waveform-equalized by the waveform equalization discriminator 42, and becomes a signal of an eye pattern with open eyes.
A serial transmission clock is extracted from this signal, data is identified, and a 1-bit digital signal is output. The code converter 43 self-synchronizes from the signal output from the waveform equalization discriminator 42 and outputs a 1-bit digital signal. The synchronization circuit 44 detects a communication synchronization signal indicating that 10 “1s” and 20 “0s” continue from the 1-bit signal output from the code converter 43, and a word synchronization signal indicating the boundary of each word in the serial bit string. And outputting a signal and a communication synchronization position signal indicating a period position where the communication synchronization signal exists. The serial / parallel converter 45 converts the 1-bit signal output from the code converter 43 based on the word synchronization signal output from the synchronization circuit 44.
Convert to a 10-bit parallel signal for each word and output. In the hold circuit 46, a serial / parallel converter 45
Of the words of the output signal, the value _{Am + 4} of the word immediately before the start of the communication synchronization signal period for the period during which the communication synchronization signal is present due to the communication synchronization position signal output from the synchronization circuit 44 is held, and the 10-bit signal is output. It is output to the video signal output terminal 47.

[0008]

However, in an apparatus for performing communication by inserting a communication synchronization signal for each horizontal synchronization period as in the above-described conventional configuration, a composite image having a different temporal position (phase) in the horizontal synchronization period. When two signals are multiplexed and communicated, the bit pattern of the communication synchronization signal at a position other than the original communication synchronization signal in relation to the data of the other channel even if the communication synchronization signal is inserted during the horizontal synchronization period of one channel. This causes a problem that a malfunction occurs.

For example, in the conventional video signal transmitting apparatus shown in FIG. 4, a 10-bit signal (first
And the channel) and another channel (second channel, showing the collection of data in word units in B _m) of 10
When the bit video signal is time-division multiplexed, the serial bit string after the parallel / serial conversion is as shown in FIG. In this case, if the MSB of B _{m + 4} is “1” and the MSBs of B _{m + 5} and B _{m + 6} are “0” as shown in FIG. 6B, 3FFh, 000h, 000h In this case, the bit pattern of the communication synchronization signal is generated at an erroneous time position, so that the word synchronization in the video signal receiving device cannot be obtained and a malfunction occurs. Even if the LSB of B _{m + 5} is “1” and the LSBs of B _{m + 6} and B _{m + 7} are “0”, the bit pattern of the communication synchronization signal occurs at an incorrect time position. Further, depending on the data values of both the first and second channels, there is a possibility that a bit pattern of the communication synchronization signal may be generated at a temporal position other than the horizontal synchronization period of the first channel, which causes a malfunction.

The present invention solves the above-mentioned conventional problem. When two composite video signals having different temporal positions (phases) in a horizontal synchronization period are multiplexed, communication synchronization is performed at a position other than the communication synchronization signal. It is an object of the present invention to provide a video signal transmitting / receiving apparatus that accurately receives a communication synchronization signal without generating a signal bit pattern.

[0011]

In order to achieve this object, a video signal transmitting apparatus according to the present invention comprises an n-bit quantization of two channels consisting of a first channel and a second channel (n is an integer of 2 or more). A multiplexing circuit that time-division multiplexes the composite digital video signal to output an n-bit signal, a limiter that limits possible values of an n-bit signal output from the multiplexing circuit to predetermined upper and lower limits, and a limiter output n A register for delaying a bit signal by three periods of a clock having a frequency twice as high as the sampling frequency of a digital video signal, and three predetermined words consisting of n-bit values forbidden by a limiter are used as communication synchronization signals, and horizontal synchronization of the first channel is performed. During the signal period, a communication synchronization signal for three words is output for three periods of the clock twice the sampling frequency of the digital video signal. And a selection circuit that outputs an n-bit signal of a register output in the next cycle, outputs an n-bit signal of a register output in the next cycle, and outputs an n-bit signal of a limiter output in another period. is there.

The video signal receiving apparatus according to the present invention further comprises a register for delaying the n-bit signal output from the serial / parallel converter by three periods of the parallel clock, and a n-bit signal output from the register based on the communication synchronization position signal output from the synchronization circuit. A selection circuit that outputs an n-bit signal of the serial / parallel converter only four words after the first word of the communication synchronization signal of the signal, and outputs an n-bit signal of the register output during other periods; A separation circuit for performing time-division separation of a signal and outputting an n-bit signal of the first channel where the head word of the communication synchronization signal exists and an n-bit signal of a second channel where the head word of the communication synchronization signal does not exist; The period of the communication synchronization signal among the n-bit signals of the first channel of the separation circuit output is determined by the communication synchronization position signal of the output. Hold the value before the first word of the signal, the other time period is obtained by a hold circuit for outputting a n-bit signal of the first channel separating circuit output.

The video signal receiving apparatus according to the present invention further comprises a register for delaying the n-bit signal output from the serial / parallel converter by three periods of the parallel clock, and an n-bit signal output from the register based on the communication synchronization position signal output from the synchronization circuit. A selection circuit that outputs an n-bit signal output from the serial / parallel converter only four words after the first word of the communication synchronization signal of the signal, and outputs an n-bit signal output from the register during other periods; A separation circuit for performing time-division separation of the bit signal and outputting an n-bit signal of the first channel where the head word of the communication synchronization signal exists and an n-bit signal of the second channel where the head word of the communication synchronization signal does not exist; The period of the communication synchronization signal among the n-bit signals of the first channel of the separation circuit output is determined by the communication synchronization position signal of the circuit output. The replacement to a predetermined value, other periods is obtained by a permutation circuit for outputting an n-bit signal of the first channel separating circuit output.

[0014]

According to the present invention, when detecting a communication synchronizing signal from a serial bit string, the present invention detects a continuous 3n-bit (three-word) bit pattern, and the data of the video signal takes any value. At any rate, there is no false detection of the communication synchronization signal.

[0015]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a video signal transmitting apparatus according to a first embodiment of the present invention. In FIG. 1, reference numeral 10 denotes a first channel video signal input terminal, and 11 denotes a second channel video signal input terminal.
Channel video signal input terminal, 12 is a horizontal synchronization detection circuit, 13 is a multiplexing circuit, 14 is a limiter, 15 is a register, 16 is a synchronization signal generation circuit, 17 is a selection circuit, 18 is a parallel / serial converter, and 19 is an output Circuit, 20 is a transmission output terminal,
n = 10 indicates a 10-bit parallel signal.

The operation of the video signal transmitting apparatus according to the present embodiment thus configured will be described below. A composite digital video signal having a sampling frequency of 14.3 MHz and a quantization of 10 bits is input from the video signal input terminal 10 of the first channel and the video signal input terminal 11 of the second channel, respectively. The horizontal synchronization detection circuit 12 detects a horizontal synchronization pulse from the 10-bit signal input from the first channel video signal input terminal 10 and outputs a horizontal synchronization signal indicating a horizontal synchronization period. On the other hand, the multiplexing circuit 13 time-division multiplexes the two-channel video signals input from the first-channel video signal input terminal 10 and the second-channel video signal input terminal 11 to obtain a 10-bit video signal for the first channel and the second channel. Data is output alternately. As a result, the output signal of the multiplexing circuit 13 changes every 28.6 MHz (two times the sampling frequency of the video signal) clock cycle. In the limiter 14, the multiplexing circuit 13 output 10
The upper limit of the bit signal is limited to 3FBh and the lower limit is 004h, and a 10-bit signal is output. Register 15 outputs 28.6 MHz 10-bit signal of limiter 14
It is delayed by three clock cycles.

The synchronizing signal generating circuit 16 uses the horizontal synchronizing signal output from the horizontal synchronizing detecting circuit 12 to output 3FFh, 000h, 3FFh, 000h, 10 cycles of 28.6 MHz clock from the beginning of the horizontal synchronizing period of the first channel video signal. It outputs a communication synchronization signal of a value prohibited by the limiter 14 of 000h. In the selection circuit 17, based on the horizontal synchronizing signal output from the horizontal synchronizing signal detecting circuit 12, three 10 cycles after 28.6 MHz clock from the beginning of the horizontal synchronizing period of the first channel video signal.
The word outputs a 10-bit signal from the sync signal generator 16 output, the next cycle outputs a 10-bit signal from the limiter 14 output, the next cycle outputs a 10-bit signal from the register 15 output, and other periods Outputs a 10-bit signal of the limiter 14 output. The parallel / serial converter 18 sequentially converts the 10-bit signal output from the selection circuit 17 into a 1-bit serial signal from the LSB side and outputs the signal. The output circuit 19 has a parallel / serial converter so that the coaxial cable can be driven.
The 18-output 1-bit signal is subjected to a self-synchronous scrambling process to remove the DC component of the signal, amplified, and output to the transmission output terminal 20.

As a result, the 1-bit serial signal output from the parallel / serial converter 18 becomes a bit string as shown in FIG. As shown in A _{m + 5 to} A _{m + 7} , the communication synchronization signal is continuous for three words, and the data of B _{m + 5} is also transmitted.

As described above, according to the present embodiment, 28.6 MH
By providing a register 15 for delaying three cycles by the z clock and a selection circuit 17 for outputting a communication synchronization signal continuously for three words, a communication synchronization signal of 30 bits continuous can be used. No bit pattern of the communication synchronization signal is generated at a position other than the original communication synchronization signal. Also, the information of the second channel can be transmitted without loss.

In the first embodiment, the limiter 14 is provided to input the output signal of the multiplexing circuit 13. However, two limiters are used, and the two-channel video signal input from the video signal input terminals 10 and 11 is used. Into the limiters,
The same effect can be obtained by inputting the respective limiter outputs to the multiplexing circuit 13.

FIG. 2 is a block diagram of a video signal receiving apparatus according to a second embodiment of the present invention. In FIG. 2, 21 is a reception input terminal, 22 is a waveform equalizer, 23 is a code converter,
24 is a synchronous circuit, 25 is a serial-to-parallel converter, 26 is a register, 27 is a selection circuit, 28 is a separation circuit, 29 is a hold circuit, 30 is a video signal output terminal of the first channel, and 31 is a second
Channel video signal output terminal.

The video signal according to the present embodiment thus configured
The operation of the transmitting device will be described below. First, the reception signal input from the reception input terminal 21 is waveform-equalized by the waveform equalization discriminator 22 to become a signal of an eye pattern with open eyes, and a serial transmission clock is extracted from this signal to perform data identification. Outputs a 1-bit digital signal. The code converter 23 self-synchronizes from the signal output from the waveform equalization discriminator 22, and outputs a 1-bit digital signal. The synchronization circuit 24 detects a communication synchronization signal in which 10 “1s” and 20 “0s” are continuous from the 1-bit signal output from the code converter 23, and a word synchronization signal indicating a boundary of each word in the serial bit string. And outputs a communication synchronization position signal indicating a period position where the communication synchronization signal exists.
The serial / parallel converter 25 converts a 1-bit signal output from the code converter 23 into a 10-bit parallel signal for each word based on the word synchronization signal output from the synchronization circuit 24, and outputs the parallel signal. The register 26 delays the 10-bit signal output from the serial / parallel converter 25 by three periods of the parallel clock. The selection circuit 27 outputs a 10-bit signal of the output of the serial / parallel converter 25 only four words after the first word of the communication synchronization signal based on the communication synchronization position signal of the synchronization circuit 24, and outputs the register 26 during other periods. Output a 10-bit signal. In the separation circuit 28, the 10-bit signal output from the selection circuit 27 is time-division-separated and a 10-bit signal is output alternately for each word, and the first word of the communication synchronization signal that can be determined from the communication synchronization position signal of the synchronization circuit 24 is output. Of existing channels
The 10-bit signal is output to the hold circuit 29, and the 10-bit signal of the channel where the first word of the communication synchronization signal does not exist is output to the video signal output terminal 31 of the second channel. In the hold circuit 29, the value of the word immediately before the first word of the communication synchronization signal for a period of 3 words from the first word of the communication synchronization signal by the communication synchronization position signal of the synchronization circuit 24 (not shown in FIG. _{m + 4} ) and the 10-bit signal is
Output to the video signal output terminal 30 of the channel.

As described above, according to this embodiment, '1' is
By providing a synchronization circuit 24 for detecting a 30-bit communication synchronization signal consisting of 20 consecutive "0" s, it is possible to detect a bit pattern of the communication synchronization signal at a time position other than the original communication synchronization signal. Disappears and can be received accurately.

Further, by providing a register 26 for delaying three cycles by a parallel clock and a selection circuit 27 for selecting the output of the register 26 only four words after the head of the communication synchronization signal, the video signal of the second channel is also one word ( Sample) can be continuously received.

FIG. 3 is a block diagram showing a video signal receiving apparatus according to a third embodiment of the present invention. In FIG. 3, 21 is a reception input terminal, 22 is a waveform equalizer, 23 is a code converter,
24 is a synchronous circuit, 25 is a serial / parallel converter, 26 is a register, 27 is a selection circuit, 28 is a separation circuit, 30 is a video signal output terminal of the first channel, and 31 is a video signal output terminal of the second channel. The above is the same as the configuration in FIG. 2 in that a replacement circuit 32 is provided in place of the hold circuit 29.

The video signal according to the present embodiment thus configured
The operation of the receiving device will be described below. First, the reception signal input from the reception input terminal 21 is waveform-equalized by the waveform equalization discriminator 22 to become a signal of an eye pattern with open eyes, and a serial transmission clock is extracted from this signal to perform data identification. Outputs a 1-bit digital signal. The code converter 23 self-synchronizes from the signal output from the waveform equalization discriminator 22, and outputs a 1-bit digital signal. The synchronization circuit 24 detects a communication synchronization signal in which 10 “1s” and 20 “0s” are continuous from the 1-bit signal output from the code converter 23, and a word synchronization signal indicating a boundary of each word in the serial bit string. And outputs a communication synchronization position signal indicating a period position where the communication synchronization signal exists.
The serial / parallel converter 25 converts a 1-bit signal output from the code converter 23 into a 10-bit parallel signal for each word based on the word synchronization signal output from the synchronization circuit 24, and outputs the parallel signal. The register 26 delays the 10-bit signal output from the serial / parallel converter 25 by three periods of the parallel clock. The selection circuit 27 outputs a 10-bit signal of the output of the serial / parallel converter 25 only four words after the first word of the communication synchronization signal based on the communication synchronization position signal of the synchronization circuit 24, and outputs the register 26 during other periods. Output a 10-bit signal. In the separation circuit 28, the 10-bit signal output from the selection circuit 27 is time-division-separated and a 10-bit signal is output alternately for each word, and the first word of the communication synchronization signal that can be determined from the communication synchronization position signal of the synchronization circuit 24 is output. Of existing channels
The 10-bit signal is output to the replacement circuit 32, and the 10-bit signal of the channel without the first word of the communication synchronization signal is output to the second circuit.
Output to the video signal output terminal 31 of the channel. Replacement circuit
At 32, the communication synchronization position signal of the synchronization circuit 24 holds a value of 010h, which is the prescribed level of the horizontal synchronization period, for a period of 3 words from the first word of the communication synchronization signal, and outputs the 10-bit signal to the video signal output of the first channel. Output to terminal 30.

As described above, according to the present embodiment, '1' is
By providing a synchronization circuit 24 for detecting a 30-bit communication synchronization signal consisting of 20 consecutive "0" s, it is possible to detect a bit pattern of the communication synchronization signal at a time position other than the original communication synchronization signal. Disappears and can be received accurately.

Further, by providing a register 26 for delaying three cycles by the parallel clock and a selection circuit 27 for selecting the output of the register 26 only after four words from the head of the communication synchronization signal, the video signal of the second channel is also one word ( Sample) can be continuously received.

[0029]

As described above, according to the present invention, a 2-channel n-bit quantization (n is 2
A multiplexing circuit for time-division multiplexing the composite digital video signal of the above integer), a limiter for limiting the possible value of the n-bit signal output from the multiplexing circuit, A register that delays by three periods of the double frequency clock, and a predetermined three that is an n-bit value prohibited by the limiter.
A word is used as a communication synchronization signal, and a communication synchronization signal for three words is output for three periods of the double clock of the sampling frequency of the digital video signal during the horizontal synchronization signal period of the first channel, and the next period is n of the limiter output. A selection circuit for outputting a bit signal, outputting an n-bit signal of a register output in the next period, and outputting an n-bit signal of a limiter output in another period.
A register for delaying the n-bit signal output from the parallel converter by three periods of the parallel clock, and a serial / communication signal only four words after the first word of the communication synchronization signal of the n-bit signal output from the register by the communication synchronization position signal output from the synchronization circuit.
A selection circuit that outputs an n-bit signal of a parallel converter output and outputs an n-bit signal of a register output during other periods;
The n-bit signal output from the selection circuit is time-division-separated, and an n-bit signal of the first channel where the head word of the communication synchronization signal exists and an n-bit signal of the second channel where the head word of the communication synchronization signal does not exist are output. A separation circuit;
According to the communication synchronization position signal output from the synchronization circuit, the period of the communication synchronization signal among the n-bit signals of the first channel of the separation circuit output is held at the value before the first word of the communication synchronization signal, and during the other periods, the value of the separation circuit output is maintained. A hold circuit that outputs an n-bit signal of one channel, or a communication synchronization position signal of a synchronization circuit output, replaces the period of the communication synchronization signal in the first channel n-bit signal of the separation circuit output with a predetermined value, and By providing a replacement circuit that outputs an n-bit signal of the first channel of the separation circuit output during the period, erroneous detection of the communication synchronization signal can be prevented regardless of the value of the video signal data. Further, since there is no loss of the information of the second channel, even if the phases of the video signals of the two channels are different, transmission is possible, and the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a block diagram of a video signal transmitting device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a video signal receiving device according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a video signal receiving device according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a video signal transmission device in a conventional example.

FIG. 5 is a block diagram of a video signal receiving device in a conventional example.

6A is a bit pattern diagram showing a serial signal of a video signal transmitting device in a conventional example, and FIG. 6B is a bit pattern diagram showing a serial signal when time-division multiplexing is performed in the video signal transmitting device in a conventional example; (c) is a bit pattern diagram showing a serial signal of the video signal transmitting device according to the embodiment of the present invention.

[Explanation of symbols]

 10, 11 Video signal input terminal 12 Horizontal synchronization detection circuit 13 Multiplex circuit 14 Limiter 15, 26 Register 16 Synchronization signal generation circuit 17, 27 Selection circuit 18 Parallel / serial converter 19 Output circuit 20 Transmission output terminal 21 Receive input terminal 22 Waveform Equalization discriminator 23 Code converter 24 Synchronization circuit 25 Serial / parallel converter 28 Separation circuit 29 Hold circuit 30, 31 Video signal output terminal 32 Replacement circuit

Claims (3)

(57) [Claims] 1. A multiplexing circuit for time-division multiplexing a 2-channel n-bit quantized (n is an integer of 2 or more) composite digital video signal comprising a first channel and a second channel and outputting an n-bit signal; A limiter for limiting the possible value of the n-bit signal output from the multiplexing circuit to predetermined upper and lower limits, and the n-bit signal output from the limiter is three periods of a double frequency clock of the sampling frequency of the digital video signal .
Only a register that delays, predetermined three of values of n bits which is prohibited by the limiter
A word is used as a communication synchronization signal, and a communication synchronization signal for three words is output for three periods of a double frequency clock of the sampling frequency of the digital video signal during a horizontal synchronization signal period of the first channel, and the next period is a limiter output. a selection circuit that outputs an n-bit signal, outputs an n-bit signal of a register output in the next cycle, and outputs an n-bit signal of a limiter output in another period; A video signal transmission device comprising a parallel / serial converter for converting a bit into a serial signal. 2. A synchronization circuit for detecting a communication synchronization signal from a received 1-bit serial signal and outputting a word synchronization signal indicating a word boundary in the serial signal and a communication synchronization position signal indicating a period position of the communication synchronization signal. A serial / parallel converter for converting a 1-bit serial signal received at the timing of the word synchronization signal output from the synchronization circuit into an n-bit parallel signal in word units; and an n-bit signal output from the serial / parallel converter. A register for delaying by three periods of the parallel clock; and a communication synchronization position signal output from the synchronization circuit, which outputs four bits from the first word of the communication synchronization signal of the n-bit signal output from the register.
Outputs n-bit signal of the only after over cereal / parallel converter output, other periods a selection circuit for outputting an n-bit signal of the register output, the time division demultiplexing the n-bit signal of the selection circuit output Do
A separation circuit for outputting an n-bit signal of the first channel where the head word of the communication synchronization signal exists and an n-bit signal of the second channel where the head word of the communication synchronization signal does not exist; and a communication synchronization position signal output from the synchronization circuit. The period of the communication synchronization signal among the n-bit signals of the first channel of the separation circuit output is held at the value before the first word of the communication synchronization signal, and during the other period, the n-bit signal of the first channel of the separation circuit output is output. A video signal receiving device comprising: 3. A synchronization circuit for detecting a communication synchronization signal from a received 1-bit serial signal and outputting a word synchronization signal indicating a word boundary in the serial signal and a communication synchronization position signal indicating a period position of the communication synchronization signal. A serial / parallel converter for converting a 1-bit serial signal received at the timing of the word synchronization signal output from the synchronization circuit into an n-bit parallel signal in word units; and an n-bit signal output from the serial / parallel converter. A register for delaying by three periods of the parallel clock; and a communication synchronization position signal output from the synchronization circuit, which outputs four bits from the first word of the communication synchronization signal of the n-bit signal output from the register.
Outputs n-bit signal of the only after over cereal / parallel converter output, other periods a selection circuit for outputting an n-bit signal of the register output, the time division demultiplexing the n-bit signal of the selection circuit output Do
A separation circuit for outputting an n-bit signal of the first channel where the head word of the communication synchronization signal exists and an n-bit signal of the second channel where the head word of the communication synchronization signal does not exist; and a communication synchronization position signal output from the synchronization circuit. A replacement circuit that replaces the period of the communication synchronization signal in the n-bit signal of the first channel of the separation circuit with a predetermined value and outputs the n-bit signal of the first channel of the separation circuit during the other period. Video signal receiving device.