JPH06139133A - Input/output device - Google Patents

Abstract

PURPOSE:To connect respective devices without being conscious of synchronization between devices, the rate of data, etc., by using an input/output circuit writing video signals in two frame memories based upon input side clocks and alternately reading out data from the two frame memories based upon output side clocks as a connection between devices. CONSTITUTION:This I/O device 1 is provided with frame memories 6, 7 for storing an input video signal in each frame unit and input and output control circuit 5, 8 supplying write signal to the memories 6, 7 based upon a clock signal and a synchronization signal obtained from the input side and supplying read signal to the memories 6, 7 based upon a clock signal and a synchronizing signal obtained from the output side and the circuits 5, 8 are constituted so as to alternately execute the writing and reading control of both the frames 6, 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output device suitable for application to, for example, an image processing device or an image processing system.

[0002]

2. Description of the Related Art Conventionally, for example, a video special effect device (DM
In the image processing apparatus such as E), 1 channel is used in the case of monaural processing (black and white signal processing), and normally 3 to 4 input / output channels are used for processing color signals (R, G, B). Has been done.

In the color signal processing, since it is premised that the input and output of 3 to 4 input / output channels are synchronized, for example, the same clock signal and synchronization signal are supplied to each channel. Color signals are input and output after synchronizing all channels.

[0004]

By the way, in the image processing apparatus as described above, the data transmission rate between the channels of the device connected to the input side and the device connected to the output side is the same. And that the devices on the input and output sides are synchronized.

Therefore, there is an inconvenience that it is not possible to cope with the case where the data transmission rates of the channels of the input and output side devices are different from each other and the case where the input and output side devices are not synchronized. .

Further, when inputting / outputting high-speed data such as a high-definition television signal, there is a disadvantage that the data is delayed.

The present invention has been made in view of the above points, and can cope with the case where the transmission rate is different between the input and the output or the case where the input and output are not synchronized, and moreover, high-speed data can be output without delay. It is intended to propose a possible input / output device.

[0008]

According to the present invention, input information is written in a predetermined unit by a write signal, and the input information written is read by a read signal, and the input information is written by a write signal. And a second storage means 7 from which the written input information is read out by a read signal, and the input information is written to the first storage means and the second storage means 6 and 7. The reading control is alternately performed.

Further, in the present invention described above, the write signal is an input side signal and the read signal is an output side signal.

Furthermore, in the present invention described above, the signal on the writing side is at least a clock signal and a synchronizing signal.

Further, in the present invention described above, the input information is image information, and the image information is written in the first and second storage means 6 and 7 with one frame unit as a predetermined unit.

Further, according to the present invention, the first storage means 6 for storing the input video signal in the frame unit, the second storage means 7 for storing the input video signal in the frame unit, the clock signal from the input side and the synchronization. A write signal is supplied to the first and second storage means 6 and 7 based on the signal, and first and second based on the clock signal and the synchronization signal from the output side.
Control means 5 and 8 for supplying a read signal to the storage means 6 and 7, and the control means 5 and 8 include the first and second
The writing and reading controls for the storage means 6 and 7 are alternately performed.

Further, in the above-mentioned present invention, the phase shift means 22a, 23a, 23 for shifting the phase of the input information.
b, 24a, 24b, 24c, 25a, 25b, 25
c, 25d and the phase shift means 22a, 23a, 2
3b, 24a, 24b, 24c, 25a, 25b, 25
It has a plurality of storage means 6 and 7 for storing the outputs from c and 25d for each predetermined unit, and an output means 26 for switching and outputting a plurality of outputs from the plurality of storage means 6 and 7.

Further, in the present invention, the input information is a video signal, and the video signal is stored in the plurality of storage means 6 and 7 in a predetermined unit for each frame.

Furthermore, the present invention has been described above in connection with the phase shift means 22a, 23a, 23b, 24a, 24b, 24c,
25a, 25b, 25c and 25d are first phase shift means 22a having the phase of the input information as the basic phase, and the phase of the input information made the basic phase by the first phase shift means 22a is phase shifted by 90 degrees. The second phase shifting means 23a, 23b and the third phase shifting means 24a, 24b, 24c for shifting the phase of the input information 180 degrees by the first phase shifting means 22a.
And fourth phase shift means 25a, 25b, 25c, 25d for phase-shifting the phase of the input information, which is the basic phase by the first phase shift means 22a, by 270 degrees.

Further, in the present invention described above, the first phase shift means 22a is the first latch means for latching the input information with the first clock, and the second phase shift means 23 is used.
a and 23b are second latch means for latching the first clock n times and latching the input information with the latched first clock, and third phase shift means 24a, 24b,
24c latches the first clock n + 1 times,
A third latch means for latching input information with the first clock latched once, and a fourth phase shift means 25a,
25b, 25c, and 25d are the m-th latch means for latching the first clock n + m times and latching the input information with the first clock latched n + m times.

Further, according to the present invention, in the above description, the input information is written in the plurality of storage means 6 and 7 by the write signal from the input side, and the input information is read by the read signal from the output side. Storage means 6 and 7
And switching means 5 and 8 for switching writing and reading of input information to and from the first and second storage means 6 and 7.

Further, in the above-mentioned invention, the output means 26 is provided.
However, using a read signal for reading input information from at least the plurality of storage means 6 and 7, the plurality of storage means 6 are used.
And a plurality of outputs from 7 are output in series.

[0019]

According to the above-described structure of the present invention, writing and reading control of the input information to the first storage means and the second storage means 6 and 7 are alternately performed.

Further in the above, according to the configuration of the present invention,
The write signal is used as a signal on the input side, the write signal is used to write input information in the first and second storage means 6 and 7, and the read signal is used as a signal on the output side. The input information written in the second storage means 6 and 7 is read.

Further in the above, according to the configuration of the present invention,
A signal on the writing side is at least a clock signal and a synchronization signal, and the first signal is generated using these clock signal and synchronization signal.
And input information is written in the second storage means 6 and 7.

Further in the above, according to the configuration of the present invention,
The input information is used as image information, and the image information is stored in the first and second storage means 6 in units of one frame as a predetermined unit.
And 7

Further, according to the above-mentioned configuration of the present invention, the frame of the input video signal by supplying the write signal to the first and second storage means 6 and 7 based on the clock signal and the synchronizing signal from the input side. By writing to the first and second storage means 6 and 7 in units, and supplying read signals to the first and second storage means 6 and 7 based on the clock signal and the synchronization signal from the output side. The control means 5 and 8 alternately perform the read control of the input video signal stored in the first and second storage means 6 and 7.

Further in the above, according to the configuration of the present invention,
Phase shift means 22a, 2 for shifting the phase of input information
3a, 23b, 24a, 24b, 24c, 25a, 25
The outputs from b, 25c, and 25d are stored in a plurality of storage units 6 and 7 for each predetermined unit, and a plurality of outputs from the plurality of storage units 6 and 7 are switched by the output unit 26 and output.

Further in the above, according to the configuration of the present invention,
The input information is a video signal, and the video signal is stored in the plurality of storage units 6 and 7 in a predetermined unit for each frame.

Further in the above, according to the configuration of the present invention,
The first phase shift means 22a shifts the phase of the input information to obtain the basic phase input information, and the first phase shift means 22a shifts the phase of the input information to the second phase.
Phase shift means 23a, 23b of 90 degrees, and the phase of the input information which is the basic phase by the first phase shift means 22a is the third phase shift means 24a, 24.
The phase of the input information that has been phase-shifted by 180 degrees by b and 24c and the basic phase by the first phase shift means 22a is shifted by 270 degrees by the fourth phase shift means 25a, 25b, 25c and 25d.

Further in the above, according to the configuration of the present invention,
The first latch means 22a latches the input information with the first clock, the second latch means 23a and 23b latch the first clock n times, and the input information is latched with the latched first clock. , Third latch means 24a, 24
b and 24c latch the first clock n + 1 times, latch the input information with the first clock latched n + 1 times, and latch the mth latch means 25a, 25b, 25c, 25d.
Then, the first clock is latched n + m times, and the input information is latched by the first clock latched n + m times.

Further in the above, according to the configuration of the present invention,
Is switched by the switching means 5 and 8 between the writing of the input information to the first and second storage means 6 and 7 by the write signal from the input side and the reading of the written input information by the read signal from the output side. .

Further, according to the structure of the present invention described above,
The output means 26 serially outputs the plurality of outputs from the plurality of storage means 6 and 7 using the read signal for reading the input information from at least the plurality of storage means 6 and 7.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the input / output device of the present invention will be described in detail below with reference to FIG.

In FIG. 1, reference numeral 1 denotes the entire input / output circuit, 2 denotes an input terminal to which data da such as a video signal from an external device (not shown) is supplied, and 3 denotes a clock signal clk1 from the external device (not shown). Input terminals 4 to be supplied are sync signals sync1 from an external device (not shown).
Are input terminals to which the input terminals 2, 3 and 4 are supplied.
The video data da, the clock signal clk1 and the synchronization signal sync1 which are supplied from the outside via the are respectively supplied to the input control circuit 5.

The input control circuit 5 supplies the video signal supplied through the input terminal 2 to the frame memory 6 or 7, and also based on the clock signal clk1 and the synchronization signal sync1 supplied through the input terminals 3 and 4. Then, a write control signal wcon such as a write address signal wad and a write signal is generated, and these signals are transmitted to the frame memory 6
And 7 respectively.

Here, for example, in the nth frame, the input control circuit 5 changes the write signal of the write control signal wcon supplied to the frame memory 6 to a signal indicating writing (for example, low level "0"), and the frame memory 7 The write control signal wcon supplied to the write control signal wcon is made inactive (for example, high level “1”), and n +
In the first frame, the write signal of the write control signal wcon supplied to the frame memory 6 is made inactive (for example, high level “1”), and the write signal of the write control signal wcon supplied to the frame memory 7 is written. The signal, for example, low level "0") is set.

Reference numeral 8 is an output control circuit.
Is a read control signal rco such as a read address signal rad and a read signal based on a clock signal clk2 supplied from an external device (not shown) via the input terminal 10 and a synchronization signal sync2 supplied via the input terminal 11.
n, and supplies these signals to the frame memories 6 and 7, respectively.

Here, for example, in the nth frame, the output control circuit 5 changes the read signal of the read control signal rcon supplied to the frame memory 6 to a signal indicating reading (for example, low level "0"), and the frame memory 7 Write control signal rcon supplied to the write control signal is made inactive (for example, high level “1”), and n +
In the first frame, the read signal of the read control signal rcon supplied to the frame memory 6 is made inactive (for example, high level “1”), and the read signal of the read control signal rcon supplied to the frame memory 7 is read. The signal, for example, low level "0") is set.

Therefore, video signals are alternately read from the frame memories 6 and 7 in frame units and supplied to an external device (not shown) via the output control circuit 8 and the output terminal 9.

In the above example, the case where the input control circuit 5 and the output control circuit 8 are provided in the input / output circuit 1 has been described, but the present invention is not limited to this.

For example, the input control circuit 5 and the output control circuit 8 are combined into one control circuit, and the read signal and the write signal are not separately supplied to the frame memories 6 and 7, but are read / write signals which are generally used, When the low level is “0”, the writing is performed, and when the high level is “1”, the reading is performed, and the read / write signals are supplied from the one control circuit to the two frame memories 6 and 7, respectively. / When the write signal is low level "0" (write), the frame memory 7
The read / write signal being supplied to the high level "1"
With (reading), writing and reading of the frame memories 6 and 7 can be performed alternately.

Further, the input control circuit 5 and the output control circuit 8 respectively obtain write and read address signals by external clock signals clk1 and clk2 and synchronization signals sync1 and sync2. Even if the signal clk1 and the synchronization signal sync1 are directly input to the frame memories 6 and 7 for writing, or the clock signal clk2 and the synchronization signal sync2 from the outside are directly input to the frame memories 6 and 7 for reading. good.

FIG. 2 shows an example of a system using the image processing apparatus 15 having the input / output circuit 1 shown in FIG.

As shown in FIG. 2, in this system, for example, the output end of the video data of the camera 12 and the input end of the video data of the input / output circuit 1a of the image processing device 15 are connected, and the clock of the camera 12 is connected. The output terminal of the signal and the input terminal of the clock signal of the input / output circuit 1a are connected, the output terminal of the synchronization signal of the camera 12 and the input terminal of the synchronization signal of the input / output circuit 1a are connected, and the image of the input / output circuit 1a is connected. The data output terminal and the video data input terminal of the image processing apparatus main circuit 16 are connected, and the clock signal input terminal of the input / output circuit 1a and the clock signal output terminal of the image processing apparatus main circuit 16 are connected. The input terminal of the synchronizing signal of the input / output circuit 1a and the output terminal of the synchronizing signal of the image processing apparatus main body circuit 16 are connected, and the output terminal and the input terminal of the image data of the image processing apparatus main body circuit 16 are connected. The video data input terminals of the input / output circuit 1b are connected, the clock signal output terminal of the image processing apparatus main circuit 16 and the clock signal input terminals of the input / output circuit 1b are connected, and the image processing apparatus main circuit 16 is synchronized. The signal output terminal and the input terminal of the synchronizing signal of the input / output circuit 1b are connected to each other, and the output terminal of the video data of the input / output circuit 1b and the monitor 17 are connected.
This input / output circuit 1b is connected between the input terminals of the video data of
The input terminal of the clock signal and the output terminal of the clock signal of the monitor 17 are connected, and the input terminal of the synchronizing signal of the input / output circuit 1b and the output terminal of the synchronizing signal of the monitor 17 are connected.

Then, the output end of the video data of the VTR 13 and the input end of the video data of the input / output circuit 1c of the image processing device 15 are connected, and the output end of the clock signal of the VTR 13 and the input of the clock signal of the input / output circuit 1c are connected. The ends are connected to each other, the output end of the VTR 13 synchronizing signal and the input / output circuit 1c are connected.
Of the input / output circuit 1c and the input end of the video data of the image processing apparatus main body circuit 16 are connected to each other, and the input end of the clock signal of the input / output circuit 1c is connected. And a clock signal output terminal of the image processing apparatus main circuit 16 is connected, and a synchronization signal input terminal of the input / output circuit 1c and a synchronization signal output terminal of the image processing apparatus main circuit 16 are connected, and further image processing is performed. Between the video data output end of the apparatus main body circuit 16 and the video data input end of the input / output circuit 1d are connected, and between the clock signal output end of the image processing apparatus main body circuit 16 and the clock signal input end of the input / output circuit 1d. Is connected between the output terminal of the synchronizing signal of the image processing apparatus main body circuit 16 and the input terminal of the synchronizing signal of the input / output circuit 1d, and the output terminal of the video data of the input / output circuit 1d and the video data of the monitor 17 are connected. Input terminals of the input / output circuit 1d and the input terminal of the clock signal of the input / output circuit 1d and the output terminal of the clock signal of the monitor 17 are connected, and the input terminal of the synchronizing signal of the input / output circuit 1d and the synchronization of the monitor 17 are connected. Connect between the signal output terminals.

The output end of the video data of the camera 14 and the input end of the video data of the input / output circuit 1e of the image processing device 15 are connected to each other, and the output end of the clock signal of the camera 14 and the clock signal of the input / output circuit 1e are connected. Of the input / output circuit 1e and the output end of the synchronizing signal of the camera 14 by connecting the input ends of
Of the input / output circuit 1e and the input end of the image data of the image processing apparatus main circuit 16 are connected to each other, and the input end of the clock signal of the input / output circuit 1e is connected. And a clock signal output terminal of the image processing apparatus main body circuit 16 is connected, and a synchronization signal input terminal of the input / output circuit 1e and a synchronization signal output terminal of the image processing apparatus main body circuit 16 are connected, and further image processing is performed. Between the video data output end of the apparatus main body circuit 16 and the video data input end of the input / output circuit 1f are connected, and between the clock signal output end of the image processing apparatus main body circuit 16 and the clock signal input end of the input / output circuit 1f. Is connected between the output terminal of the synchronizing signal of the image processing apparatus main body circuit 16 and the input terminal of the synchronizing signal of the input / output circuit 1f, and the output terminal of the video data of the input / output circuit 1f and the video data of the monitor 19 are connected. The input ends of the clock signals of the input / output circuit 1f and the output ends of the clock signals of the monitor 19 are connected to each other, and the input ends of the synchronization signals of the input / output circuit 1d and the synchronization of the monitor 19 are connected. Connect between the signal output terminals.

Next, the operation of the system shown in FIG. 2 will be described.

First, the video data picked up and output by the camera 12 is supplied to the input / output circuit 1a, and together with this,
A clock signal and a synchronization signal from the camera 12 (or from a control system that supplies the synchronization signal to the camera 12) are supplied to the input / output circuit 1a.

The input control circuit 5 (see FIG. 1) is provided in the frame memories 6 and 7 (see FIG. 1) of the input / output circuit 1a.
Is supplied with a write address signal wad and a write control signal wcon obtained based on a clock signal (for example, 14.31818 MHz in the NTSC system) and a synchronization signal from the camera 12, whereby the input / output circuit 1a is supplied.
The video data from the camera 12 is sequentially written in each of the frame memories 6 and 7, and the output control circuit 8 (see FIG. 1) supplies a clock signal (for example, 16 MHz) and a synchronization signal supplied from the image processing apparatus main body circuit 16. Based on the read address signal rad and the read control signal rc
is supplied to the frame memories 6 and 7 to read the video data written in the frame memories 6 and 7,
The read video data is supplied to the image processing device main circuit 16.

The image processing apparatus main body circuit 16 subjects the supplied video data from the camera 12 to processing such as special effect processing and supplies it to the input / output circuit 1b, and also supplies a clock signal and a synchronizing signal to the input / output circuit 1b. To do.

In the input / output circuit 1b, the write address signal wad and the write control signal wcon obtained by the input control circuit 5 based on the clock signal and the synchronizing signal from the image processing apparatus main body circuit 16 are supplied to the frame memories 6 and 7, respectively. The supplied video data from the image processing apparatus main circuit 16 is sequentially written in the frame memories 6 and 7, and the output control circuit 8 obtains the read address signal rad and the read control based on the clock signal and the synchronization signal from the monitor 17. The signal rcon is supplied to the frame memories 6 and 7, respectively, and the video data is read from the frame memories 6 and 7, and the read video data is supplied to the monitor 17 and displayed as an image on the screen.

In parallel with this, the video data reproduced and output by the VTR 13 is supplied to the input / output circuit 1c, and at the same time, the input / output circuit 1c is supplied with a sync signal from the VTR 13 (or a sync signal to the VTR 13). A clock signal and a synchronization signal (from the control system) are supplied.

Here, the input control circuit 5 (see FIG. 1) is provided in the frame memories 6 and 7 (see FIG. 1) of the input / output circuit 1c.
Is supplied with the clock signal (eg, 14.31818 MHz in the NTSC system) from the VTR 13 and the write address signal wad and the write control signal wcon, which are obtained based on the synchronizing signal.
The video data from the VTR 13 is sequentially written in each of the frame memories 6 and 7, and the output control circuit 8 (see FIG. 1) outputs the clock signal (for example, 16 MHz) and the synchronization signal supplied from the image processing apparatus main circuit 16. Based on the read address signal rad and the read control signal rc
is supplied to the frame memories 6 and 7 to read the video data written in the frame memories 6 and 7,
The read video data is supplied to the image processing device main circuit 16.

The image processing apparatus main body circuit 16 receives the supplied V
The video data from the TR 13 is subjected to processing such as special effect processing and supplied to the input / output circuit 1d, and at the same time, the clock signal and the synchronization signal are supplied to the input / output circuit 1d.

In the input / output circuit 1d, the write address signal wad and the write control signal wcon obtained by the input control circuit 5 based on the clock signal and the synchronizing signal from the image processing apparatus main body circuit 16 are supplied to the frame memories 6 and 7, respectively. The video data supplied from the image processing apparatus main circuit 16 is sequentially written into the frame memories 6 and 7, and the output control circuit 8 obtains the read address signal rad and the read control based on the clock signal and the synchronization signal from the monitor 18. The signal rcon is supplied to the frame memories 6 and 7, respectively, to read the video data from the frame memories 6 and 7, and the read video data is supplied to the monitor 18 to be displayed as an image on the screen.

In parallel with this, the image data picked up and output by the camera 14 is supplied to the input / output circuit 1e, and at the same time, the input / output circuit 1e receives a synchronization signal from the camera 14 (or a synchronization signal to the camera 14). A clock signal and a synchronization signal (from the supplying control system) are supplied.

Here, the input control circuit 5 (see FIG. 1) is provided in the frame memories 6 and 7 (see FIG. 1) of the input / output circuit 1e.
Is supplied with the write address signal wad and the write control signal wcon obtained based on the clock signal (for example, 14.31818 MHz in the NTSC system) from the camera 14 and the synchronizing signal, whereby the input / output circuit 1e.
The video data from the camera 14 is sequentially written in each of the frame memories 6 and 7, and the output control circuit 8 (see FIG. 1) supplies a clock signal (for example, 16 MHz) and a synchronization signal supplied from the image processing apparatus main body circuit 16. Based on the read address signal rad and the read control signal rc
is supplied to the frame memories 6 and 7 to read the video data written in the frame memories 6 and 7,
The read video data is supplied to the image processing device main circuit 16.

The image processing apparatus main circuit 16 performs special effect processing or the like on the supplied video data from the camera 14 and supplies it to the input / output circuit 1f, and also supplies a clock signal and a synchronization signal to the input / output circuit 1f. To do.

In the input / output circuit 1f, the write address signal wad and the write control signal wcon obtained by the input control circuit 5 based on the clock signal and the synchronizing signal from the image processing apparatus main body circuit 16 are supplied to the frame memories 6 and 7, respectively. The video data supplied from the image processing apparatus main circuit 16 is sequentially written into the frame memories 6 and 7, and the output control circuit 8 obtains the read address signal rad and the read control based on the clock signal and the synchronization signal from the monitor 19. The signal rcon is supplied to the frame memories 6 and 7, respectively, to read the video data from the frame memories 6 and 7, and the read video data is supplied to the monitor 19 to be displayed as an image on the screen.

As is apparent from the above description, for example, the camera 12, the VTR 13 and the camera 14, the monitor 1 described above.
Even if the television systems 7, 18 and 19 are different from each other, the user can use the television system without being aware of it.

For example, if the camera 12 is a PAL system, VTR1
Even if 3 is the NTSC system and the camera 14 is the NTSC system, they are simply connected, the image processing device 15 is operated to perform various processes, and then output to the monitors 17, 18 and 19, respectively. The image processing device 15 can be used in any method such as mixing and combining and outputting to one monitor 17, 18 or 19.

As described above, in this example, the input / output circuits 1a and 1b, 1c and 1d, 1e and 1f having the frame memories 6 and 7 are provided on the input side and the output side of the image processing apparatus 15, respectively, and at the time of inputting. Video data is written in the frame memories 6 and 7 by using the clock signal and the synchronization signal on the input side, and further, the frame memories 6 and 7 are used by using the clock signal and the synchronization signal from the image processing apparatus main circuit 16.
The video data is read from the image processing device 15
When outputting from the image processing apparatus main body circuit 16, the video signal is written into the frame memories 6 and 7 by using the clock signal and the synchronizing signal, and the video data is written by using the clock signal and the synchronizing signal on the output side. Since the data is read out from the device 7 and outputted, the image processing work can be carried out without any trouble even when the data transmission rates are different between the connected peripheral devices or when the peripheral devices are not synchronized.

FIG. 3 is a block diagram showing another example of the input / output device of this example.

Another example of the input / output device will be described below with reference to FIG. 3. The parts corresponding to those in FIGS. 1 and 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 3, when a very high-speed data such as a high-definition television signal is processed and output by the image processing device 15, the signal is not delayed.

That is, in FIG. 3, reference numeral 20 denotes, for example, a high-definition camera (HD camera), which is an output end of a synchronization signal of the camera 20 (or an output end of a control device or the like which supplies the synchronization signal to the camera 20). Is connected to the input end of the image processing device 15. Although not shown, the image processing apparatus 15 has a plurality of input / output circuits 1 described with reference to FIGS. 1 and 2, and the plurality of input / output circuits 1 of the image processing apparatus main circuit 16 (not shown). It is assumed that the input and output terminals of the synchronization signals are arranged in front and in the back and are connected to the input terminals of the respective synchronization signals of the plurality of input / output circuits 1 of all stages of the image processing apparatus main circuit 16.

The output end of the video data of this camera 20 is set to D
Type flip-flop circuits 22a, 23b, 24c and 25d are connected to the respective data input terminals D, and the output terminal of the clock signal (for example, 74.25 MHz) of this camera 20 is connected to the D-type flip-flop circuits 23a, 24a, 25.
It is connected to each clock input terminal of a and the input terminal of the clock signal of the image processing apparatus 15.

Although not shown, the image processing apparatus 15 has a plurality of input / output circuits 1 described with reference to FIGS. 1 and 2, and these plurality of input / output circuits 1 are not shown in the figure. It is assumed that the clock signal input terminals are arranged before and after the circuit 16 and are connected to the clock signal input terminals of the plurality of input / output circuits 1 in the preceding stage of the image processing apparatus main circuit 16.

Further, a frequency (18.625) which is a quarter of the basic clock signal (sampling clock) of the camera 20 is used.
The input terminal 21 to which the signal of (MHz) is supplied is connected to the clock input terminal of the D-type flip-flop circuit 22a and each data input terminal of the D-type flip-flop circuits 23a, 24a and 25a.

Then, the D-type flip-flop circuit 22a
Is connected to the data input terminal of the input / output circuit 1 of the preceding stage (not shown) of the image processing device 15, and the data output terminal Q of the D-type flip-flop circuit 23a is input to the clock of the D-type flip-flop circuit 23b. The data output terminal Q of the D-type flip-flop circuit 23b is connected to the data input terminal of the input / output circuit 1 in the preceding stage of the image processing apparatus main body circuit 16, and the data of the D-type flip-flop circuit 24a is connected. The output terminal Q is connected to the data input terminal D of the D-type flip-flop circuit 24b, and the data output terminal Q of this D-type flip-flop circuit 24b is set to D.
Connected to the clock input terminal of the D-type flip-flop circuit 24c, the data output terminal Q of the D-type flip-flop circuit 24c is connected to the data input terminal of the input / output circuit 1 of all the stages of the image processing device main circuit 16, The data output terminal Q of the D-type flip-flop circuit 25a is connected to the data input terminal D of the D-type flip-flop circuit 25b, and the data output terminal Q of this D-type flip-flop circuit 25b is connected to the D-type flip-flop circuit 25c. Data input terminal D of the D-type flip-flop circuit 25c, and the data output terminal Q of the D-type flip-flop circuit 25c is connected to the clock input terminal of the D-type flip-flop circuit 25d. Q is the image processing apparatus main circuit 1
6 is connected to the data input terminal of the input / output circuit 1 in the preceding stage, and further, the clock output terminal of the camera 20 and each clock input terminal of the D-type flip-flop circuits 24b, 25b, 25c are connected.

That is, these D-type flip-flop circuits 22a, 23a, 23b, 24a, 24b, 24c, 2
5a, 25b, 25c and 25d, the D-type flip-flop circuit 22a is used as the first phase shift means,
The D-type flip-flop circuit 22a latches the image data from the camera 20 at a frequency (18.625 MHz) which is a quarter of the basic clock (sampling clock) 74.5 MHz of the high definition television signal. Video data of basic phase.

Next, the D-type flip-flop circuit 23a
And 23b as the second phase shift means, and the D-type flip-flop circuit 23a supplies 74.5 MHz from the camera 20.
The video of 18.625 MHz is latched by the clock of z, the video data is latched by the latched 18.625 MHz clock signal in the D-type flip-flop circuit 23b, and the video is delayed by 90 degrees from the video data of the basic phase. Get the data.

Next, the D-type flip-flop circuit 24
a, 24b and 24c are the third phase shift means, and D
Type flip-flop circuit 24a
The 18.625 MHz clock is latched with the 4.5 MHz clock, and the latched 18.625 MHz clock is applied to the camera 2 by the D-type flip-flop circuit 24b.
It is latched with a clock of 74.5 MHz from 0 and latched with 1 in the D-type flip-flop circuit 24c.
Latch video data with a clock of 8.625MHz,
Image data that is 180 degrees out of phase with the basic phase image data is obtained.

Next, the D-type flip-flop circuit 25
a, 25b, 25c, and 25d are used as the fourth phase shift means, and the D-type flip-flop circuit 25a is used for the camera 20.
With a clock of 74.5MHz from 18.625MHz
Latches the clock of this latched 18.625M
The Hz clock is latched by the D-type flip-flop circuit 25b with the 74.5 MHz clock from the camera 20, and the latched 18.625 MHz clock is D
Type flip-flop circuit 25c
18.625M latched by the 4.5-MHz clock and latched by the D-type flip-flop circuit 25d
The video data is latched with a clock of Hz to obtain video data which is delayed by 270 degrees from the basic phase video data.

The 74.5 MHz clock signal from the camera 20 need not be output from the camera 20, and may be output from a device for synchronizing the camera 20, such as a synchronization signal generator. Also, 1
Even with a clock of 8.625 MHz, a frequency divider is arranged in the front stage of the circuit shown in FIG.
You can divide the MHz clock to get it,
It may be generated by the above-mentioned synchronization signal generator and used.

Each D-type flip-flop circuit 22 described above
a, 23b, 24c and 25d output video data of the basic phase, video data delayed by 90 degrees from the basic phase, video data delayed by 180 degrees from the basic phase,
The video data whose phase is delayed by 270 degrees from the basic phase is supplied to the input / output circuit 1 of the image processing apparatus 15 and sequentially processed by the internal image processing apparatus main circuit 16 and sequentially passed through the input / output circuit 1 on the output side. Are sequentially output.

The image-processed basic phase image data from the image processing device 15, image data delayed by 90 degrees from the basic phase, image data delayed by 180 degrees from the basic phase, and 270 degrees phase from the basic phase. The video data with a delay is supplied to a multiplexer 26, and is sequentially output by the multiplexer 26, that is, is supplied to a high-definition monitor 27 as one high-definition video data, and a high-definition image is displayed on the screen. Is projected as.

The operation will be described with reference to FIG.
When high-definition video data as shown in FIG. 4A is input, the clock of the D-type flip-flop circuit 22a rises (see FIG. 4B) and the clock of the D-type flip-flop circuit 23b rises (see FIG. 4C). ), The rising edge of the clock of the D-type flip-flop circuit 24c (see FIG. 4D) and the rising edge of the clock of the D-type flip-flop circuit 25d (see FIG. 4E) latch the video data pixel by pixel.

That is, 1-channel high-definition video data is converted into 4-channel parallel video data. For example, if the numbers are numbered 1, 2, 3, ... From the top pixel, the D-type flip-flop circuit 22a outputs 1, 5 ,.
Video data composed of pixel data of 9, ..., Is output, and 2 is output from the D-type flip-flop circuit 23b.
The video data composed of the pixel data of 6, 10, ..., Is outputted, and the video data composed of the pixel data of 3, 7, 11, ..., Is outputted from the D-type flip-flop circuit 24c. The D-type flip-flop circuit 25 is output.
Video data composed of pixel data of 4, 8, 12, ... Is output from d.

These video data are supplied to the image processing apparatus main body circuit 16 via the input / output circuit 1 and subjected to predetermined processing as described above, and then to the multiplexer 26 via the input / output circuit 1, respectively. The supplied high-definition video data is restored and restored to the original high-definition video data by being switched by the multiplexer 26 at the 74.5 MHz clock, and is supplied to the high-definition monitor 27. Therefore, even if the high definition television signal is processed by the image processing device 15, there is no delay.

It should be noted that in the image processing device 15, the video data is stored in the frame memories 6 and 7 of the input / output circuit 1 (not shown).
After being written with a 74.5 MHz clock from the camera 20, each is read with a 16 MHz clock from an image processing apparatus main body circuit 16 (not shown) and subjected to image processing in the image processing apparatus main body circuit 16. After being written in the frame memories 6 and 7 of the output side input / output circuit 1 at the 16 MHz clock from the image processing apparatus main circuit 16, it is read at the 74.5 MHz clock from the camera 20 and supplied to the multiplexer 26. Will be done.

In the above example, the case where the high definition video data is simply processed by four channels has been described, but the channels may be assigned to the high and low bands of luminance and two color difference signals.

As described above, in this example, a high-speed signal such as a high-definition television signal is supplied to the D-type flip-flop circuit 22a, the D-type flip-flop circuits 23a and 23b, the D-type flip-flop circuit 24a, and the like. 24b and 24c, D-type flip-flop circuits 25a and 25
b, 25c, and 25d phase-shift, and the four-system video data obtained by phase-shifting are supplied to the image processing apparatus main circuit 16 via the input / output circuit 1 to perform image processing.
Since the original high definition video data is supplied to the multiplexer 26 via the input / output circuit 1, image processing can be performed without delay even for a high speed signal such as a high definition television signal. It can be carried out.

In each of the above examples, the input / output circuit 1
However, if the input / output circuit 1 is used as an independent device, the image processing device 15 can be used without modification. .

The above-described embodiment is an example of the present invention, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0083]

According to the present invention described above, writing and reading of input information to and from the first storage means and the second storage means are alternately performed, so that data input / output can be performed without delay. It can be performed.

Further, according to the present invention described above, the write signal is used as the input signal, the write signal is used to write the input information in the first and second storage means, and the read signal is used as the output signal. Since the read information is used to read the input information written in the first and second storage means, it is possible to connect the devices without being aware of the synchronization or data rate between the devices on the input side and the output side. It can be done and processed.

Furthermore, according to the present invention described above, the signal on the write side is at least the clock signal and the synchronization signal, and the input information is written in the first and second storage means using the clock signal and the synchronization signal. Because I did
In addition to the above effects, writing to the storage means can be performed reliably.

Further, according to the present invention, the input information is image information and the image information is written in the first and second storage means in units of one frame as a predetermined unit. In addition, it is possible to easily and surely input image information in various formats.

Further, according to the present invention described above, the first video signal in the frame unit of the input video signal by supplying the write signal to the first and second storage means based on the clock signal and the synchronization signal from the input side. And writing to the second storage means, and storing in the first and second storage means by supplying a read signal to the first and second storage means based on the clock signal and the synchronization signal from the output side. Since the reading control of the input video signal is alternately performed by the control means, it is possible to perform the processing by connecting the devices without being aware of the synchronization between the input side device and the output side device and the data rate, Further, the input video signal can be input / output without delay.

Further, according to the present invention described above, the output from the phase shift means for shifting the phase of the input information is stored in a plurality of storage means for each predetermined unit, and the plurality of outputs from the plurality of storage means are output. Since the output is switched by the means, it is possible to cope with the above-mentioned effect even if the input information is a high speed signal.

Further, according to the present invention described above, the input information is a video signal, and the video signal is stored in a plurality of storage means in a predetermined unit for each frame. Therefore, in addition to the above-mentioned effects, various formats can be used. The video signal of can be reliably input.

Further, according to the present invention described above, the phase of the input information is shifted by the first phase shift means to obtain the input information of the basic phase, and the input information made the basic phase by the first phase shift means. The second phase shift means shifts the phase of 90 degrees by 90 degrees, and the first phase shift means shifts the phase of the input information by 180 degrees by the third phase shift means. Since the phase of the input information that has been made the basic phase by the shift means is phase-shifted by 270 degrees by the fourth phase shift means, in addition to the above effects, for example, in an image processing apparatus, high-definition image information or the like can be obtained. A high-speed input signal can be processed and output without delay.

Further, according to the present invention described above, the first latch means latches the input information at the first clock, the second latch means latches the first clock n times, and the latched first Latch the input information with the clock of
Latch means latches the first clock n + 1 times, latches the input information by the first clock latched n + 1 times, the mth latch means latches the first clock n + m times, and latches this n + m times. Since the input information is latched by the first clock that has been set, in addition to the above effects,
It is possible to eliminate the delay at the time of outputting the input signal with a simple circuit configuration.

Further, according to the present invention described above, the writing of the input information by the write signal from the input side to the first and second storage means and the reading of the written input information by the read signal from the output side are performed. Since switching is performed by the switching means, in addition to the above effects, the devices can be connected, data can be input, and processing can be performed without being aware of the synchronization between the connected devices and the data rate.

Further, in the above description, according to the present invention, the output means outputs the plurality of outputs from the plurality of storage means in series by using the read signal for reading the input information from at least the plurality of storage means. Therefore, in addition to the effects described above, it is possible to process a high-speed signal without delay.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an input / output device of the present invention.

FIG. 2 is a configuration diagram showing an example of a system using an image processing apparatus incorporating the input / output device of the present invention.

FIG. 3 is a configuration diagram showing another example of the input / output device of the present invention.

FIG. 4 is a timing chart for explaining another example of the input / output device of the present invention.

[Explanation of symbols]

1, 1a, 1b, 1c, 1d, 1e, 1f Input / output circuit 5 Input control circuit 6, 7 Frame memory 8 Output control 22a, 23a, 23b, 24a, 24b, 24c, 2
5a, 25b, 25c, 25d flip-flop circuit 26 multiplexer

Claims (11)

[Claims] 1. A first storage unit in which input information is written in a predetermined unit by a write signal, the written input information is read in by a read signal, and the input information is written in a predetermined unit by the write signal. A second storage means for reading the written input information by a read signal, and writing and reading control of the input information to and from the first storage means and the second storage means are alternately performed. An input / output device characterized by the above. 2. The write signal is used as a signal on the input side,
The input / output device according to claim 1, wherein the read signal is a signal on an output side. 3. The write-side signal is at least a clock signal and a synchronization signal.
The input / output device described. 4. The input information is image information, and
2. The input / output device according to claim 1, wherein the image information is written in the first and second storage means in units of one frame as a predetermined unit. 5. A first storage means for storing an input video signal in frame units, a second storage means for storing the input video signal in frame units, and a clock signal and a synchronization signal from the input side. And a control means for supplying a write signal to the first and second storage means and supplying a read signal to the first and second storage means based on a clock signal and a synchronization signal from the output side. The input / output device, wherein the control means alternately performs writing and reading control with respect to the first and second storage means. 6. A phase shift means for shifting the phase of input information, a plurality of storage means for storing the output from the phase shift means for each predetermined unit, and a plurality of outputs from the plurality of storage means for switching. An input / output device having an output means for outputting. 7. The input information is a video signal, and
7. The input / output device according to claim 6, wherein the video signal is stored in the plurality of storage units with a predetermined unit for each frame. 8. The phase shift means comprises first phase shift means having a phase of input information as a basic phase, and 90 degrees phase of the phase of the input information made the basic phase by the first phase shift means. The second phase shifting means for shifting, the third phase shifting means for shifting the phase of the input information, which is the basic phase by the first phase shifting means, by 180 degrees, and the first phase shifting means. 7. The input / output device according to claim 6, further comprising a fourth phase shift means for shifting the phase of the input information, which is the basic phase, by 270 degrees. 9. The phase shift means latches the input information with a first clock, the first latch means latches the first clock n times, and the input information is latched with the first clock. Latching the first clock n + 1 times, latching the input information with the first clock latched n + 1 times, and the first clock. 7. The input / output device according to claim 6, wherein the input / output device is configured to be latched n + m times, and the m-th latch means for latching the input information with the first clock latched n + m times. 10. The first and second storage means in which the input information is written by a write signal from an input side and the input information is read by a read signal from an output side, in the plurality of storage means. 7. The input / output device according to claim 6, further comprising switching means for switching writing and reading of the input information to and from the first and second storage means. 11. The output means serially outputs the plurality of outputs from the plurality of storage means by using a read signal for reading the input information from at least the plurality of storage means. The input / output device according to claim 6.