JPH0612235A - Circuit and method for multiplication over integer - Google Patents

Abstract

PURPOSE:To provide the circuit and method for efficient integral multiplication considering carry by using a multiplier with the small number of digits. CONSTITUTION:When (h), (m) and (n) are defined as positive integers, this multiplication circuit multiplies an integer A of (nXm) bits and an integer B of (hXm) bits and is provided with multipliers B0-B3 of mXm bits for multiplying the (m) bits of the integer B to the respective (m) bits of the integer A when the integer A is inputted from the high-order digit while being divided into (n) clocks for every (m) bits, 2m bit full adders +0-+3 with carries for adding the carry bit of the output from the 2m bit full adder at the following digit in the case of the last clock to the outputs of the multipliers B0-B3, and registers R0-R3 connected between the two 2m bit full adders +0 to +3 with carries. Then, a multiplied result A.B is outputted from the high-order digit from the most-significant register R3 synchronously with the clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integer multiplication circuit, and more particularly to a circuit and method for performing multiplication with a large number of digits by using a multiplier with a small number of digits. The present invention is an RSA cipher that requires multiplication of a large number of digits (Shinichi Ikeno, Kenji Koyama: "Modern Cryptography", IEICE, 1
It can be used for many integer operations, including encryption techniques such as 980, 6).

[0002]

2. Description of the Related Art In a gate array design or substrate design, a multiplier on an integer having a small number of digits can be easily constructed because a cell library, TTL, etc. are prepared. However, when trying to realize a multiplication circuit with a large number of digits, there is no cell library or the like, so it is necessary to design by yourself. However, in the case of designing a multiplier with a large number of digits by itself, if the circuit configuration of the multiplier with a small number of digits is expanded as it is, the circuit configuration becomes very complicated and difficult to realize.

When an input value is divided into predetermined bits and multiplication is performed by a plurality of clocks, if the input value is regarded as a polynomial, Galois field (Yo Miyakawa, Hiroshi Harajima, Hideki Imai:
It is known that multiplication is performed by a circuit as shown in FIG. 2 in an arithmetic system with no carry such as “Theory of Information and Code”, Iwanami Course, 1982, Chapter 6). In Figure 2, *
B _i is a multiplier on the Galois field of m bits * m bits with B _i (i = 0, ..., N−1) as a multiplier, EX is an EXOR of m bits, and r is a register of m bits.

However, in the multiplication on an integer, carrying out a division operation as shown in FIG. 2 causes a carry for each digit of the division operation, so that it is difficult to realize an efficient multiplier.

[0005]

SUMMARY OF THE INVENTION The present invention eliminates the above-mentioned drawbacks, and when a multiplication circuit divides an input value having a large number of digits for arithmetic operation, a carry with a carry having a small number of digits is used. It is an object of the present invention to provide an efficient integer multiplication circuit and multiplication method in consideration.

[0006]

To solve this problem, the integer multiplication circuit of the present invention uses an integer A of (n × m) bits when h, m, and n are positive integers. And (h ×
m) A multiplication circuit on an integer which multiplies the bit B by an integer B. The integer A is divided into n clocks for every m bits and is input from the upper digit, and the integer B is assigned to each m bit of the integer A. Of m bits x m bits connected in parallel to the integer A for multiplying m bits of the output, the output of the multiplier, and the last clock of the 2m bit full adder with one lower digit carrier. The lower 2m bit of the output and the lower 2m bit of the output of the 3m lower 2m bit full adder with the carry at the previous clock are added, one for each of the multipliers and one for the final stage. The 2m bit full adder with the carrier and the 2m bit full adder with the carrier arranged one-dimensionally
It is equipped with a register for inputting and outputting the output of the bit at the same time, which is connected between the two 2m bit full adders with a carrier, and the highest carrier with the carrier 2 synchronized with the clock.
The multiplication results A and B are output from the upper digit from the m bitful adder.

Here, the 2m bit full adder with a carrier corresponding to the m bit × m bit multiplier for multiplying the m bit of the least significant digit of the integer B is deleted. The full adder with a carrier is realized by a plurality of 2-input full adders or half adders.

The integer multiplication method of the present invention uses h,
If m and n are positive integers, the (n × m) bit order
On an integer that multiplies the number A by the (h × m) bit integer B
And a multiplier of m bits × m bits,
2m bit full adder with carrier and the full adder
The address is arranged corresponding to the digit of the integer B that stores the output
At least 2m + 1 bit memory with multiple areas
And (A) an n-divided m bit of the integer A (A_i )
And an integer B divided by m bits (B_j ) And the above
The process of multiplying with a multiplier of m × m bits and (B) Multiplication result
Fruit and a predetermined area of the memory (R_j-1 ) Lower 2m bit
And predetermined area (R_j-3 ) 2m + 1 bit eyes and full above
The process of adding with an adder and (C) The addition result is stored in the memory.
Predetermined area (R_i ) Is stored in the
(A) to (C) for each A_i(i = n-1, n-2, ..., 0 order)
About B _j Repeat j from n-1 to 0
Return each A_i About B_n-1 Note after the end of the process
Predetermined area (R_n-1 ) Lower 2m + 1 bits and predetermined area
Area (R _n-2 ) 2m + 1 bit and a predetermined area (R_n-3 )
2m + 1 bit and the result of adding with the full adder
Is output from the upper digit of the multiplication result A / B.

[0009]

[Embodiment] In this embodiment, an integer A of n · m bits and h · m
A multiplier with a bit integer B is assumed, but for the sake of simplicity, it will be described as h = n. This limitation does not lose generality. That is, it is considered that the two integers of n · m bits are A and B, and the operation of A · B = C is executed. Here, the multiplication a · b of two integers a and b of m bits
The multiplier for executing = c can be easily realized by a known structure such as a cell library or TTL.

If the integers A and B are each divided into m bits, the result can be expressed as follows.

A = A _n- 1.X ^n-1 + A _n- 2.X ^n-2 + ...
+ A ₁ · X + A ₀ B = B _n-1 · X ^n-1 + B _n-2 · X ^n-2 + ... + B ₁ · X +
B ₀ Here, assuming that X = 2 ^m−1 , the bit sequences obtained by dividing the high-order digit by m bits for A and B are A _i and B _i (i
= N-1, ..., 0). In this case, since the integers A and B can be regarded as polynomials, A · B can be expressed as follows.

[0012]

[Equation 1] Here, the case of n = 4 is considered for simplification, but this limitation does not lose generality.

[0013]

[Formula 2] A · B = A ₃ · (B ₃ · X ⁶ + B ₂ · X ⁵ + B ₁ · X ⁴ + B ₀ · X ³ ) + A ₂ · (B ₃ · X ⁵ + B ₂ · X ⁴ + B ₁ · X ³ + B ₀ · X ² ) + A ₁ · (B ₃ · X ⁴ + B ₂ · X ³ + B ₁ · X ² + B ₀ · X) + A ₀ · (B ₃ · X ³ + B ₂ · X ² + B ₁ · X + B ₀ ) = C ₆ · X ⁶ + C ₅ · X ⁵ + C ₄ · X ⁴ + C ₃ · X ³ + C ₂ · X ² + C ₁ · X + C ₀ This can be constructed by a circuit as shown in FIG. Figure 1
Multiplier 4 which performs multiplication a · b = c of m bits × m bits is _{(× B 0 ~ × B 3} ) and, 2m bit the carry with adder (full adder) 4 (+ ₁ + ₄₎ And (2m
+1) 4 bit registers (R _{0 to} R ₃ ).

In FIG. 1, the initial state of each register is all "0".

When A ₃ is input at the first clock,
Output coefficient A ₃ · B _i of each term of the formula (i = 3 ... 0) from the multiplier is stored in each register (R ₀ to R ₃₎ through each full adder (+ ₁ + ₃₎ .

A at the next clock₂ When is input, A
・ X, which is the most significant digit of B⁶ Coefficient C ₆ (= A₃ ・ B₃ )
Is the rightmost register R₃ To full adder_Four Output through
To be done. At that time, another full adder (+₁ ~ +₃ )so
Is the register output A to the left of the full adder.₃ ・ B
_i-1 (I = 3 ... 0) and the output A from the multiplier₂ ・ B_i (I
= 3 ... 0) (A₃ ・ B_i-1 + A₂ ・ B_i )
(I = 3 ... 0) is calculated, and the output is the register on the right of each.
It is input to the studio. This is the formula and the X of the formula
_Five , X_Four , X₃ Means to compute the sum of each coefficient of
It

However, B _i (i = -1 ...- n) is always "0". Since each value of A ₃ · B _{i −1} and A ₂ · B _i is 2 m bits, the output from the full adder is 2 m + 1 bits if there is a carry. Therefore, each register requires 2m + 1 bits. Here, each bit of the register means digit, the most significant bit of one register hits ² digit 2 ^2m = X with respect to the least significant bit.
However, since each register R _i stores the operation result of X digits, the most significant bit of each register R _i has the same digit as the least significant bit of the register R _{i + 2 on} the right of the two.

[0018] When A ₁ is entered in the next _{clock, C 5 = (A 3 ·} B 2 + A 2 · B 3) which corresponds to the coefficient of X ⁵ from the full adder (+ ₄₎ of the right end of the circuit of Figure 1 Is output. At this time, the most significant bit of the immediate left of the register R ₃ is the same order of magnitude as the least significant bit is two left neighboring same order of magnitude as X digit the most significant bit and C ₅ of the register R ₂ in C ₅ is also added Is output. At this time, the other of the full adder (+ ₁ to +
₃ ) is the addition of the 2m bit output from the register on the left side and the 2m bit output from the multiplier, and the addition of the most significant bit, which is the carry output from the register on the left side, as a carrier. Output 2m + 1 bits. As a result, the coefficients of the respective terms up to the above equation are added.

[0019] When the next last input A ₀ in clock is input, likewise C ₄ is the coefficient of X ⁴ is outputted from the right end of the full adder (+ _4), each term of the above equation in each of the multipliers The coefficient A ₀ · B _i (i = 3 ... 0) of is output. In response to the output, in each full adder is the coefficient C ₃ -C ₀ are sequentially output to X ³ to X ^0, all of the multiplication result is output. As a result, when the value of the integer A is divided and input,
The calculation of B is efficiently performed.

From the above, it can be shown that when the input value is divided into n bits every m bits and is input, an n · m bits multiplication circuit can be efficiently realized by using an m bits × m bits multiplier. It was It is clear that the multiplication can be executed by the same circuit even when h ≠ n. It is also apparent that the same configuration can be achieved by omitting the full adder and the register at the right end of FIG. 1 or by adding the full adder and the register. Further, the configuration in which the same arithmetic element is repeated as shown in FIG. 1 has an advantage that a large-scale circuit such as VLSI is easily configured.

Further, the multiplier (× B ₀ ) and the register R shown in FIG.
It is equivalent to provide a full adder (+ ₀ ) between ₀ and
In this example, a multiplier (× B _i ), a full adder (+ _i ) and a register (R _i ) are combined into one processing element (P).
It can also be realized by the pipeline method considered as E). Furthermore,
It can also be realized by sequential or parallel processing by software, comprising a multiplier (× B _i ), a full adder (+ _i ) and a memory having a plurality of areas.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0023]

According to the present invention, when an input value having a large number of digits is divided and operated in a multiplying circuit, a multiplier having a small number of digits is used, and an efficient integer multiplication circuit considering a carry is provided. A multiplication method can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing an integer multiplication circuit according to the present embodiment.

FIG. 2 is a diagram illustrating a known polynomial multiplication circuit on a Galois field.

[Explanation of symbols]

R ... 2m + 1 bit register, + ... Full adder, × B
m bit xm where _i ... _Bi (i = 0 ... n-1) is a multiplier
Multiplier on bit integer, * B _i ... B _i (i = 0 ... n-
1) multiplier with m bits x m bits Galois field multiplier, EX ... m bits EXOR, r ... m bits register

Claims (4)

[Claims] 1. When h, m, and n are positive integers,
(N × m) bit integer A and (h × m) bit integer B
A multiplication circuit on an integer for multiplying with, the integer A is divided into n clocks for every m bits and inputted from the upper digit, and each m bit of the integer A is multiplied by a predetermined m bit of the integer B. An m-bit × m-bit multiplier connected in parallel to the integer A, an output of the multiplier, and a lower-order 2m-bit of the output at the last clock of the 2m-bit full adder with one lower digit carrier. Adds the carry bit of the output from the previous clock of the 2m bit full adder with the carrier of the three lower digits, one for each of the multipliers and one more for the final stage
A register connected between the two 2m bit-full adders with a carrier for simultaneously inputting and outputting the 2m bit-full adder with a carrier and the 2m + 1 bit output of the 2m bit-full adder with a carrier And a multiplication circuit on an integer, which outputs the multiplication results A and B from the upper digit from the highest 2m bit full adder with a carrier in synchronization with the clock. 2. A 2m bit full adder with a carrier corresponding to the m bit × m bit multiplier for multiplying the m bit of the least significant digit of the integer B is deleted. Multiply circuit on integer. 3. The multiplication circuit on an integer according to claim 1, wherein the carrier-added full adder is realized by a plurality of 2-input full adders or half adders. 4. When h, m, and n are positive integers,
(N × m) bit integer A and (h × m) bit integer B
An integer multiplication method for multiplying with m bit x m bit multiplier and 2m bit with carrier
Full adder and an integer B that stores the output of the full adder
A small number of areas with addresses arranged corresponding to the digits of
It has at least 2m + 1 bits of memory, and (A) m bits divided by n of integer A (A_i ) And the integer B
h divided m bits (B_j ) And the above m bits x m bits
Step of multiplying by the multiplier of the bridge, (B) multiplication result and a predetermined area (R_j-1 ) Lower
2m bit and predetermined area (R_j-3 ) 2m + 1 bit eyes
With the full adder, and (C) the addition result is stored in a predetermined area (R) of the memory._i )
And the above steps (A) to (C)_i(i = n-1, n-2, ...,
0 order), B _j Of j is changed from n-1 to 0
Let's repeat, each A_i About B_n-1 After the process of
Predetermined area (R_n-1 ) Lower 2m + 1 bit
And predetermined area (R _n-2 ) 2m + 1 bit and predetermined area
(R_n-3 ) 2m + 1 bit eyes with the full adder
The result of the calculation can be output from the upper digit of the multiplication result A / B.
A method of multiplication over integers characterized by and.