JP3129524B2 - Multiplication circuit on integer and multiplication method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplication circuit for integers, and more particularly to a circuit for multiplying a large number of digits using a multiplier of a small number of digits. The present invention provides an RSA cryptosystem that requires multiplication of a large number of digits (Shinichi Ikeno, Kenji Koyama:
“Modern Cryptography”, IEICE, 1986, Chapter 6)
It can be used for many integer operations including encryption techniques such as.

[0002]

2. Description of the Related Art In designing a gate array or a substrate, a multiplier on an integer having a small number of digits can be easily configured because a cell library, TTL, and the like are provided. However, when trying to realize a multiplication circuit with a large number of digits, there is no cell library or the like, so that the user has to design it by himself. However, when designing a multiplier with a large number of digits by itself, if the circuit configuration of the multiplier with a small number of digits is directly expanded, the circuit configuration becomes extremely complicated and difficult to realize.

In the case where an input value is divided for each predetermined bit and multiplication is performed by a plurality of clocks, the Galois field (Yo Miyagawa, Hiroshi Harashima, Hideki Imai:
It is known that an arithmetic system having no carry, such as "Theory of Information and Codes", Iwanami Koza, 1982, Chapter 6, performs multiplication by a circuit as shown in FIG. In FIG. 4 , *
B _i is _{B i (i = 0, ...} , n-1) multiplier and the m bits * m bits of the Galois field on the multiplier, EX is EXOR of m bits, r is a register m bits.

However, in multiplication on integers, if a division operation as shown in FIG. 4 is performed, a carry is generated for each digit obtained by the division operation, so that it is difficult to realize an efficient multiplier.

SUMMARY OF THE INVENTION The present invention eliminates the above-mentioned drawbacks and, when dividing and calculating an input value having a large number of digits in a multiplication circuit, uses a multiplier having a small number of digits to efficiently perform an integer operation considering a carry. It is an object to provide the above multiplication circuit.

[0006]

In order to solve this problem, a multiplication circuit on an integer according to the present invention provides an integer A of (n × m) bits when h, m, and n are positive integers. And (h ×
m) A multiplication circuit on an integer for multiplying a bit by an integer B, wherein each m bits of an integer A input from the lower digit after being divided into n clocks for each m bits, each of which is an integer B A plurality of m-bit × m-bit multipliers for multiplying different predetermined m-bits in parallel;
Two outputs arranged one-dimensionally corresponding to the multiplier, adding the output of the last clock of the full adder of one upper digit and the output of the previous clock of the full adder to the lower bit.
An m-bit full adder, a buffer that holds the carrier from the full adder and feeds back to the full adder with a delay of two clocks, each stores one output of the 2 m bit of the 2 m bit full adder, and stores the lower output with the next clock. And a plurality of registers for outputting to the 2 m bit full adder, and multiplying results A and B are output from the least significant digit from the least significant 2 m bit full adder in synchronization with the clock.

Here, the 2 m-bit full adder for adding the output of the m-bit × m-bit multiplier for multiplying the m-bit of the most significant digit of the integer B is omitted, and the output is stored in one of the plurality of registers. One to store.

Further, the multiplication method on integers according to the present invention comprises:
An integer multiplication method for multiplying an integer A of (n × m) bits and an integer B of (h × m) bits where m and n are positive integers, wherein m bits × m bits And a multiplier of
A full adder for adding the output of the multiplier, the data at the predetermined address position and the carry at the predetermined address position, and a memory having a plurality of areas for storing the output of the full adder and the carry corresponding to the integer B digit In the multiplication circuit, (A) the n-divided m-bits (A _i ) of the integer A and the h-divided m-bits (B _j ) of the integer B are divided into the m bits ×
(B) multiplication results, data of a predetermined area (R _{j + 1} ) of the memory and a predetermined area (B
A step for adding the the carry of two previous F _j) in the full adder, (C) an addition result of the full adder in a predetermined region (R _j) of the memory, a predetermined area of the memory the carry (BF _j) And the step (A) ~
(C) for each A _i (in the order of 0, 1,..., N−1)
B _j is executed in order or in parallel with j, and the output of the full adder during the process of B ₀ or the data of the predetermined area (R ₀ ) of the memory after completion is multiplied by A · B for each A _i.
Output from the lower digit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In this embodiment, an integer A and hm
It is assumed that a multiplier with a bit integer B is used. This limitation does not cause loss of generality. That is, it is assumed that two integers of nm bits are A and B, and an operation of AB = C is executed. Here, multiplication a · b of two integers a and b of m bits
= C can be easily realized by a known configuration such as a cell library or TTL.

When the integers A and B are each divided into n for every m bits, the following expression can be obtained.

A = A _n-1 · X ^n-1 + A _n-2 · X ^n-2 + ...
_{+ A 1 · X + A 0} B = B n-1 · X n-1 + B n-2 · X n-2 + ... + B 1 · X +
B ₀ Here, X = 2 ^m−1, and bit sequences obtained by dividing A and B from the upper digit for each m bits are A _i and B _i (i
= N-1, ..., 0). In this case, since the integers A and B can be regarded as polynomials, AB can be expressed as follows.

[0012]

(Equation 1) Therefore, a multiplier can be constituted by a circuit as shown in FIG. FIG.
Represents n multipliers (××) which execute m-bit multiplication a · b = c
B _i ; i = n−1,..., 0) and n−1 adders (full adders) with carry of 2 m bits (+ i; i = n−
2,..., 0) and n-1 registers of 2 m bits (R
_i ; i = n-1,..., 1) and 2n-1 buffers (BF _i ; i = n-2,.
0).

In FIG. 1, when A ₀ is inputted in the first clock, C ₀ (= A ₀ · B ₀ ) which is the least significant digit is outputted, and A ₀ · B _i (i = n) is outputted to each register. , ..., n-
2) is stored. The initial state of the register is all "0"
It is.

In the next clock, A₁ Is entered, right
End register output A₀ ・ B₁ And the output of the multiplier, A₁ 
・ B₀ Sum C₁ (= A₀ ・ B₁ + A₁ ・ B₀ ) Is output
It is. This is the coefficient of the next digit, X. A₀ ・ B
₁ + A₁ ・ B₀ Is a two-bit buffer on the far right
BF₀ And added after 2 clocks as carry
Used in This is A₀ ・ B₁ + A₁ ・ B₀ 
Is a 2 m bit, ie X ^Two In contrast to the value of minutes,
The output from the circuit has the digit raised by X per clock.
Therefore, carry representing carry is counted two clocks later.
It is because it is calculated.

Further, each register R _i and buffer BF
_{In i} , (A ₀ · B _i + A ₁ · B _i ), which is the sum of the output from the previous-stage register R _{i + 1} and the output from the multiplier, and the carry thereof are stored.

The above operation is repeated for n clocks, and A _n-1
If the input to the digits of the multiplication result to X ^n-1 is known to be outputted from the full adder + _0. Thereafter, by inputting "0" for n clocks and repeating the same operation, the values in the respective registers are sequentially output, and all of the multiplication results are output.

Further, the above embodiment is different from the embodiment shown in FIG.
One multiplier B_i And full adder + _i And buffer BF_i 
And register R_i An arithmetic element consisting of
Element; PE), as shown in FIG.
It is clear that this can be realized by the parallel processing.

Thus, when the value of A is divided and input, the calculation of AB is efficiently performed. As described above, it has been shown that when an input value is input after being divided into n units of m bits, an m-bit multiplication circuit can be efficiently realized using an m-bit multiplier. It is clear that multiplication can be performed by a similar circuit even when h ≠ n.

In this method, since the carry by the full adder is closed by the feedback using the buffer, there is no problem such as a delay related to the carry which becomes a problem in the multiplication on the integer.

The output from the circuits shown in FIGS. 1 and 2 is 2 m
It is a bit unit, but it is clear that m-bit output can be achieved by using this buffered full adder. That is, the upper m bits of the 2 m bits are input to the m bit register, which is input to the m bit full adder, the lower m bits are directly input to the full adder, the carry is delayed by one bit, and the full adder is fed back to the full adder. Just do it.

Further, the configuration by repeating the same arithmetic element as shown in FIGS. 2 and 3 has an advantage that a large-scale circuit such as VSLI can be easily configured.

The present invention may be applied to a system constituted by a plurality of devices or to an apparatus constituted by a single device. It is needless to say that the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

[0023]

According to the present invention, when an input value having a large number of digits is divided and operated in a multiplication circuit, an efficient multiplication circuit on an integer taking into account a carry is used by using a multiplier having a small number of digits. Can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a multiplication circuit on an integer according to an embodiment.

FIG. 2 is a diagram showing a multiplication circuit on integers according to the present embodiment constituted by PEs.

FIG. 3 is a diagram showing an internal configuration of a PE shown in FIG. 2;

FIG. 4 is a diagram showing a known polynomial multiplication circuit on a Galois field.

[Explanation of symbols]

R ... 2m bits of the register, + ... 2m bits of the full _{adder, × B i ... B i (} i = 0 ... n-1) was used as a multiplier the m bits of on integer _{multiplier, * B i ... B i (} i = 0 ... n-
Multiplier on m-bit Galois with multiplier 1), BF ...
Buffer, PE ... Processing element (P
E), EX ... m bit EXOR, r ... m bit register

Claims (3)

(57) [Claims] 1. When h, m, and n are positive integers,
(N × m) bit integer A and (h × m) bit integer B
A multiplying circuit on an integer for multiplying by an integer B. For each m bits of the integer A input from the lower digit, divided into n clocks for each m bits, each of the predetermined m bits of the integer B is different. A multiplicity of m-bit × m-bit multipliers, each of which multiplies the output of the multiplier and the output of the previous clock of the full-adder of one upper digit, and the low-order bit of the output from the previous clock and the previous two-time carry. , 1 corresponding to the multiplier.
A 2 m-bit full adder arranged in a dimension, a buffer that holds the carrier from the full adder and feeds back to the full adder with a delay of two clocks, and each stores one output of the 2 m bit of the 2 m bit full adder. A plurality of registers for outputting to the lower 2 m-bit full adder at the next clock, and multiplying results A and B are output from the lower-order digit from the lower 2 m-bit full adder in synchronization with the clock. Multiplying circuit on integer. 2. The addition of the output of the m-bit × m-bit multiplier for multiplying the m-bit of the most significant digit of the integer B by 2m
2. The integer multiplication circuit according to claim 1, wherein a bit full adder is omitted, and the output is stored in one of the plurality of registers. 3. When h, m, and n are positive integers,
(N × m) bit integer A and (h × m) bit integer B
An integer multiplication method for multiplying the multiplication by an m-bit × m-bit multiplier, a full adder for adding an output of the multiplier, data at a predetermined address position, and a carry at a predetermined address position, and a full adder. A multiplication circuit comprising a memory having a plurality of areas for storing the output of the integer A and the carrier corresponding to the digit of the integer B, wherein (A) m bits (A _i ) of the integer A divided into n and h of the integer B Multiplying the divided m-bit (B _j ) by the m-bit × m-bit multiplier; (B) multiplying result, data of a predetermined area (R _{j + 1} ) of the memory, and a predetermined area (BF) _j ) a step of adding the carry two times before by the full adder in the full adder; and (C) adding the addition result of the full adder to a predetermined area (R _j ) of the memory and carrying the carry to a predetermined area (BF _j ) of the memory.
And executing the steps (A) to (C) for each A _i (in the order of i = 0, 1,..., N−1) in order for _j of B _j or in parallel, For each A _i , the output of the full adder during the process of B ₀ or the data of a predetermined area (R ₀ ) of the memory after completion is output from the lower digit of the multiplication result A · B. Multiplication method.