JPH0612237A - Multiplication circuit over integer - Google Patents

Abstract

PURPOSE:To provide the efficient circuit considering carry by using a multiplier with the small number of digits in the case of separately calculating an input value with the large number of digits in the multiplication circuit. CONSTITUTION:This circuit is provided with multipliers B10-B13 of mXm bits which input an integer A from the high-order digit while dividing it into (n) clocks for every (m) bits and multiply the prescribed (m) bits of an integer B to the respective (m) bits of the integer A, three-input (m) bit full adders +10-+13 with carries for adding the low-order (m) bits of outputs from the high-order digit multiplier, the high-order (m) bits of outputs from the same digit multiplier, the output of the (m) bit full adder with carry at the following digit in the case of the last clock, and the carry bit of the (m) bit full adder with carry at wo digits behind in the case of the last clock, (m+1) bit registers R10-R13 connected between two of three-input (m) bit full adders with carries. Then, the content of the (m+1) bit register in the final step after each clock is defined as the output of a multiplied result A.B from the high-order digit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integer multiplication circuit, and more particularly to a circuit and method for performing multiplication with a large number of digits by using a multiplier with a small number of digits. The present invention is an RSA cipher that requires multiplication of a large number of digits (Shinichi Ikeno, Kenji Koyama: "Modern Cryptography", IEICE, 1
It can be used for many integer operations, including encryption techniques such as 980, 6).

[0002]

2. Description of the Related Art In a gate array design or substrate design, a multiplier on an integer having a small number of digits can be easily constructed because a cell library, TTL, etc. are prepared. However, when trying to realize a multiplication circuit with a large number of digits, there is no cell library or the like, so it is necessary to design by yourself. However, in the case of designing a multiplier with a large number of digits by itself, if the circuit configuration of the multiplier with a small number of digits is expanded as it is, the circuit configuration becomes very complicated and difficult to realize.

Further, the input value is divided into predetermined bits and duplicated.
If you want to multiply by a few clocks, you can
Considering that, Galois body (Hiro Miyakawa, Yoshihiro Iwadari, Hideki Imai:
Carriage such as "Code theory", Shokodo, 1973, Chapter 4)
In an arithmetic system without burrs, multiply by a circuit as shown in Fig. 3.
Is known to take place. In Figure 3, * B_i Is B _i 
M bits * m bits with (i = 0, ..., N-1) as a multiplier
The multiplier on the Galois field of G, EX is the EXOR of m bits,
r is an m-bit register.

However, in the multiplication on an integer, carrying out a division operation as shown in FIG. 2 causes a carry for each digit of the division operation, so that it is difficult to realize an efficient multiplier.

[0005]

SUMMARY OF THE INVENTION The present invention eliminates the above-mentioned drawbacks, and when a multiplication circuit divides an input value having a large number of digits for arithmetic operation, a carry with a carry having a small number of digits is used. It is an object of the present invention to provide an efficient multiplication circuit on an integer.

[0006]

To solve this problem, the integer multiplication circuit of the present invention uses an integer A of (n × m) bits when h, m, and n are positive integers. And (h ×
m) A multiplication circuit on an integer which multiplies the bit B by an integer B. The integer A is divided into n clocks for every m bits and is input from the upper digit, and the integer B is assigned to each m bit of the integer A. Of m bits multiplied by m bits, which are connected in parallel to the integer A, a lower m bits of the output of the higher-order multiplier, and a higher order of the output of the same-order multiplier. 3 with the above-mentioned carrier that adds the m bit and the output of the m-bit full adder with one lower digit at the previous clock and the carrier bit of the m-bit full adder with two lower digits at the previous clock An input m bitful adder and an m + 1 bit output of the m-bit full adder with carrier are simultaneously input / output, and m + 1 connected between the two m-bit full adder with carrier.
And the contents of the m + 1-bit register at the final stage after each clock are output from the upper digits of the multiplication results A and B.

Here, the carrier-added 3-bit m-bit full adder corresponding to the lower m-bit of the m-bit × m-bit multiplier that multiplies the m-bit of the least significant digit of the integer B is deleted. The carrier-equipped 3-input m-bit full adder is realized by a plurality of 2-input full adders or half adders. The m + 1-bit register is a memory having an arbitrary number of areas.

In addition, the integer multiplication circuit of the present invention uses h, n
Where n is a positive integer, an n-bit integer A is multiplied by an h-bit integer B, and the integer A is divided into n clocks every 1 bit and input from the upper digit. A 1-bit by 1-bit multiplier connected in parallel to the integer A for multiplying each 1-bit of the integer A by a predetermined 1-bit of the integer B, the output of the multiplier, and the previous clock. The 1-bit full adder with a carrier for adding the output of the 1-bit full-adder with a carrier at the time of the last time and the carry bit of the 1-bit full-adder with a carry for the last 2 low-order digits, and the carrier A 2-bit register connected between the two 1-bit full adders with a carrier for simultaneously inputting and outputting the 2-bit outputs of a 1-bit full adder with a clock, and the last stage after each clock. The contents of the bits of the register multiplication result as an output from the upper digit of A · B.

Here, the 1-bit full adder corresponding to the lower bit of the 1-bit by 1-bit multiplier for multiplying the 1-bit of the least significant digit of the integer B is deleted. In addition, the 1-bit full adder with a carrier has a plurality of 2
It is realized by an input full adder or a half adder. The 2-bit register is a memory having an arbitrary number of areas.

[0010]

[Embodiment] In this embodiment, an integer A of n · m bits and h · m
A multiplier with a bit integer B is assumed, but for the sake of simplicity, it will be described as h = n. This limitation does not lose generality. That is, it is considered that the two integers of n · m bits are A and B, and the operation of A · B = C is executed. Here, the multiplication a · b of two integers a and b of m bits
The multiplier for executing = c can be easily realized by a known structure such as a cell library or TTL.

If the integers A and B are each divided into m bits, the result can be expressed as follows.

A = A _n- 1.X ^n-1 + A _n- 2.X ^n-2 + ...
+ A ₁ · X + A ₀ B = B _n-1 · X ^n-1 + B _n-2 · X ^n-2 + ... + B ₁ · X +
B ₀ Here, assuming that X = 2 ^m−1 , the bit sequences obtained by dividing the high-order digit by m bits for A and B are A _i and B _i (i
= N-1, ..., 0). In this case, since the integers A and B can be regarded as polynomials, A · B can be expressed as follows.

[0013]

[Equation 1] Here, since the generality is not lost, the case of n = 4 is considered.

[0014]

[Formula 2] A · B = A ₃ · (B ₃ · X ⁶ + B ₂ · X ⁵ + B ₁ · X ⁴ + B ₀ · X ³ ) + A ₂ · (B ₃ · X ⁵ + B ₂ · X ⁴ + B ₁ · X ³ + B ₀ · X ² ) + A ₁ · (B ₃ · X ⁴ + B ₂ · X ³ + B ₁ · X ² + B ₀ · X) + A ₀ · (B ₃ · X ³ + B ₂ · X ² + B ₁ · X + B ^{_{0) = C 6 · X 6}} + C 5 · X 5 + C 4 · X 4 + C 3 · X 3 + C 2 · X 2 + C 1 · X + C 0 = C 7 'X 7 + C 6' X 6 + C 5 'X 5 + C ^{_{4 'X 4 + C 3'}} X 3 + C 2 'X 2 + C 1' X + C 0 'C i' = up (C i-1) + down (C i) ( example 1) which, circuit as shown in FIG. 1 Constitutes a multiplier with. Figure 1 is a multiplier 4 which performs multiplication a · b = c of m × m bits and (× B ₁₀ ~ × B _13), four the carry with the full adder of m bits of the 3-input (+ ₁₀ ~ + ₁₃₎ And m + 1
It is composed of four bit registers (R _{10 to} R ₁₃ ).
In FIG. 1, the initial state of each register is all "0".

When A ₃ is input at the first clock,
The coefficients A ₃ · B _i (i = 3, ..., 0) of each term in the equation are output from each multiplier. Since A ₃ .B _i output from the multiplier is an output of 2 m bits (2 ^{2 m} = X ² digit output), the lower m bits of the right multiplier (B _1i ) and the left multiplier (B 1 _i ). The upper m bits of _1i-1 ) output the same digit. Therefore, in the full adder (+ _1i-1 ) shown in FIG. 1, the upper m bits and the lower m bits of the left and right multipliers are added at the same time, and the addition result is input to each register (R _1i ) for each X digit. Stores the calculation result of.

As shown in the above equation, the upper m bits are
up (C_i-1 ), The lower m bits are down (C_i ). Servant
X, which is the most significant digit of A and B shown in the formula⁷ Person in charge
Number C ₇'Is the full adder (+₁₃) Is output through
It At this time, a carry is added to the sum of the upper and lower m bits.
If so, the m + 1th bit of each register is the carry bit.
It will store the dots. M which means this carry
The + 1st bit is the same digit as the least significant bit of the register on the right.
Is.

[0017] When the next A ₂ is entered in clock, the addition of the right end of the full adder (+ _13), the right end of the multiplier output A ₂ · B ₃ of the upper m bits and immediate left of the register R ₁₃ in FIG. 1 Is performed and the coefficient C ₆ 'of X ^{6 in} the equation is output. Then, the other of the full adder (+ ₁₀ ~ + _12), the high and low m bits output of the left and right above multipliers, the sum of the lower m bits output from the register to the left next to the full adder is calculated, The outputs are input to the registers on the right.

Further, the m + 1th bit of the register on the left of the two registers is added to the full adder as a carrier. As a result, the sum of the coefficients of the terms of the equation and the equation is calculated. Here, since the outputs from the register and the multiplier are m bits respectively, carry of two digits can be considered, and the number of bits of the register for storing the output from the full adder must be m + 2 bits.

[0019] When A ₁ is entered in the next clock, the coefficient C ₅ 'of X ⁵ is output from the right end of the full adder (+ _13). At this time, each full adder has the same digit as the lower 2 bits of the register on the left, and the upper 2 of the register on the left of 2
Bits are input as carriers, and each full adder performs addition and outputs m + 2 bits.

[0020] When the last input A ₀ is entered in the next clock, from the right end of the full adder (+ ₁₃₎ are output C ₄ 'is the coefficient of X ^4, coefficients for X ³ to X ⁰ in each full adder C ₃ ′ to C ₀ ′ are calculated and stored in each register.

Thereafter, by inputting four clocks of "0" and repeating the same operation, the values C ₃ 'to C in each register are repeated.
₀ 'are sequentially outputted from the right end of the full adder (+ _13), all of the multiplication result is output. Thus, when the value of A is divided and input, the calculation of A and B is efficiently performed.

[0022]

[Other Embodiments] Next, a multiplier is constructed by a circuit as shown in FIG. FIG. 2 shows a multiplication circuit when A _i and B _i (i = n-1, ..., 0) are in 1-bit units. 2 four 1 × 1 bit multiplier and (× B ₂₀ ~ × B _23), 1 the carry with full adder four bits and (+ ₂₀ ~ + _23), the four 2-bit register (R ₂₀ - consisting of R _23). In FIG. 2, the initial state of each register is all "0".

When A ₃ is input at the first clock,
The coefficient A ₃ · B _i (i = 3, ..., 0) of each term in the equation is output from each multiplier and stored in each register through each full adder.

A at the next clock₂ When is input, A
・ X, which is the most significant digit of B⁶ Coefficient C ₆ (= A₃ ・ B₃ )
Is the rightmost register R_{twenty three}To full adder (+_{twenty three}) Through
Is output. At that time, another full adder (+₂₀~ +_{twenty two})
Then the register output A at the left end of the full adder₃ ・ B
_i-1 (I = 3, ..., 0) and the output A from the multiplier₂ ・ B _i 
It is the sum of (i = 3, ..., 0) (A₃ ・ B_i-1 + A₂ ・
B_i ) (I = 3, ..., 0) is calculated, and the output is
It is input to the register on the right.

In the above equation, this is
Means to calculate the sum of the coefficients. However, B_i (I
= -1, ..., -n) is always "0". Where A₃ 
・ B _i-1 , A₂ ・ B_i Each term in is one bit each
The output from the full adder is 2 bits if there is a carry.
Become. Therefore, each register requires 2 bits. cash register
Each bit of the star means a digit, and the upper bit of each register.
Has the same digit as the lower bit of the register on the right.

[0026] When A ₁ is entered in the next _{clock, C 5 (= A 3 ·} B 2 + A 2 · B 3) which corresponds to the coefficient of X ⁵ from full adder (+ ₂₃₎ of the right end of the circuit of FIG. 2 Is output. At this time, the upper bit of the register R ₂₂ on the left side, which is the same digit as the lowest bit of C ₅ , is also added and output. At this time, the other full adders add one bit output from the register on the left and one bit output from the multiplier by adding the highest bit which is a carry output from the register on the left on the left as a carrier. Then, it outputs 2 bits. As a result, the coefficients of the respective terms up to the above equation are added.

[0027] When the last input A ₀ is entered in the next clock, as well as C ₄ is the coefficient of X ⁴ from full adder (+ ₂₃₎ of the right end is output, each term of the above equation in each of the multipliers The coefficient A ₀ · B _i (i = 3, ..., 0) of is output. In response to the output, the full adder (+ ₂₃ ~ + _20), the X ³
Factor C ₃ -C ₀ for to X ⁰ are computed and stored in each register.

[0028] Thereafter, Yotsute repeats the four clock input the same operation "0", the value C ₃ -C in each register
₀ are sequentially outputted from the right end of the full adder (+ _23), all of the multiplication result is output. Thereby, the calculation of A and B when the value of A is divided and input is efficiently performed.

From the above, it can be shown that when the input value is divided into m bits and input, the n · m bit multiplication circuit can be efficiently realized by using an m bit × m bit multiplier. It was When n ≠ 4, and when n ≠ h,
It is clear that multiplication can be performed with a similar circuit.

In FIG. 1, it is also apparent that the 3-input m-bit full adder having bit carry can be realized by a combination of a plurality of 2-input full adders and a half adder. Further, it is apparent that the same multiplier can be configured by omitting the full adder and the register at the right end in FIGS. 1 and 2 or adding the full adder and the register at the right end. Further, since FIG. 2 shows multiplication by 1 × 1 bit, there is no overlap of digits from the multiplier output, and a simpler circuit configuration than that of the circuit of FIG. 1 is sufficient. Further, the configuration in which the same arithmetic element is repeated as shown in FIGS. 1 and 2 has an advantage that a large-scale circuit such as VLSI can be easily configured.

Further, the present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0032]

According to the present invention, when an input value having a large number of digits is divided and operated in a multiplying circuit, a multiplier having a small number of digits is used to provide an efficient integer multiplication circuit considering carry. Can be provided.

[Brief description of drawings]

FIG. 1 is a diagram illustrating an integer multiplication circuit according to a first embodiment.

FIG. 2 is a diagram illustrating an integer multiplication circuit according to another embodiment.

FIG. 3 is a diagram showing a known polynomial multiplication circuit on a Galois field.

[Explanation of symbols]

R ₁₀ ~R ₁₃ ... 2m + 1 bit register, R ₂₀ ~R ₂₃ ... 2
Bit registers, + ₁₀ ~ + ₁₃ ... the carry with 3 input m-bit full adder, + ₂₀ ~ + ₂₃ ... the carry with 1 bit full adder and a multiplier of _{× B 1i ... B i (i} = 0 ... n-1) Multiplier on an integer of m bits × m bits, × B _2i ... B _i
(I = 0 ... n-1) multiplier, 1-bit x 1-bit integer multiplier, * B _i ... B _i (i = 0 ... n-1) m-bit * m-bit multiplier Multiplier over Galois field, E
X ... m bit EXOR, r ... m bit register

Claims (8)

[Claims] 1. When h, m, and n are positive integers,
(N × m) bit integer A and (h × m) bit integer B
A multiplication circuit on an integer for multiplying with, the integer A is divided into n clocks for every m bits and inputted from the upper digit, and each m bit of the integer A is multiplied by a predetermined m bit of the integer B. An m-bit × m-bit multiplier connected in parallel to the integer A, a lower m-bit of the output of the multiplier of the upper digit, an upper m-bit of the output of the multiplier of the same digit, and 1 at the time of clock
The output of the m-bit full adder with the carrier of the two lower digits,
Simultaneously input and output the 3-input m-bit full adder with the carrier and the m + 1 bit output of the m-bit full adder with the carrier, which adds the carry bit of the m-bit full adder with the lower two digits at the last clock And an m + 1-bit register connected between the two m-bit full adders with the carrier, and the contents of the m + 1-bit register at the final stage after each clock are output from the upper digit of the multiplication result A / B. A multiplication circuit on an integer characterized by the above. 2. The 3-input m-bit full adder with carrier corresponding to the lower m bits of the m-bit × m-bit multiplier that multiplies the m-bit of the least significant digit of the integer B is deleted. The integer multiplication circuit according to claim 1. 3. The multiplication circuit on an integer according to claim 1, wherein the 3-input m-bit full adder with carrier is realized by a plurality of 2-input full adders or half adders. 4. An integer multiplication circuit according to claim 1, wherein the m + 1-bit register is a memory having an arbitrary number of areas. 5. An integer multiplication circuit for multiplying an n-bit integer A and an h-bit integer B when h and n are positive integers, wherein the integer A is n for every 1 bit. A 1-bit by 1-bit multiplier which is divided into clocks and is inputted from the upper digit, and each 1-bit of the integer A is multiplied by a predetermined 1-bit of the integer B, which is connected in parallel to the integer A; With the above-mentioned carrier that adds the output of the vessel and the output of the 1-bit full adder with a carry of the last lower digit at the previous clock and the output of the 1-bit full adder with a carry of the lower digit at the previous clock It is equipped with a 1-bit full adder and a 2-bit register connected between two 1-bit full adders with a carrier for simultaneously inputting and outputting the 2-bit output of the 1-bit full adder with a carrier. A multiplication circuit on an integer, wherein the contents of the 2-bit register at the final stage after the packing is output from the upper digit of the multiplication result A / B. 6. The 1-bit full adder corresponding to the lower bit of the 1-bit by 1-bit multiplier for multiplying the 1-bit of the least significant digit of the integer B is deleted. A multiplication circuit on the described integer. 7. The multiplication circuit on integers according to claim 5, wherein the one bit full adder with carrier is realized by a plurality of two-input full adders or half adders. 8. A multiplication circuit on an integer according to claim 5, wherein the 2-bit register is a memory having an arbitrary number of areas.