JPH0612231A - Multiplication circuit over integer - Google Patents

Abstract

PURPOSE:To provide the multiplication circuit over integers, which is efficient and excellent in extensibility at high speed, considering carry by using a multiplier with the small number of digits in the case of separately calculating an input value with the large number of digits at the multiplication circuit. CONSTITUTION:When (h), (m) and (n) are defined as positive integers, this integral multiplication circuit multiplies an integer A of (nXm) bits and an integer B of (hXm) bits and is provided with identical arithmetic elements PE(0, 0) to PE(n-1, h-1) two-dimensionally arranged in the matrix of h row Xn columns. Ai (i=0, ..., n-1) dividing the integer A for every (m) bits and Bj (j=0, ..., h-1) dividing the integer B for every (m) bits are simultaneously inputted to the PE(i, 0) to PE(i, h-1) at the respective columns, Sj-Ai.Bj+Sj (j=0, ..., h-1) is calculated at each PE(i, j) and outputted to the PE(i+1, j-1) and the output from the PE(i, 0) and the PE(n-1, j) is defined as the multiplied value of A and B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integer multiplication circuit, and more particularly to a circuit for multiplying a large number of digits by using a multiplier having a small number of digits. The present invention is an RSA cipher requiring a large number of multiplications (Shinichi Ikeno, Kenji Koyama:
"Modern Cryptography", IEICE, 1986, Chapter 6)
It can be used for many integer operations including encryption techniques such as.

[0002]

2. Description of the Related Art In a gate array design or substrate design, a multiplier on an integer having a small number of digits can be easily constructed because a cell library, TTL, etc. are prepared. However, when trying to realize a multiplication circuit with a large number of digits, there is no cell library or the like, so it is necessary to design by yourself. However, in the case of designing a multiplier with a large number of digits by itself, if the circuit configuration of the multiplier with a small number of digits is expanded as it is, the circuit configuration becomes very complicated and difficult to realize.

When an input value is divided into predetermined bits and multiplication is performed by a plurality of clocks, if the input value is regarded as a polynomial, Galois field (Yo Miyakawa, Hiroshi Harajima, Hideki Imai:
It is known that multiplication is performed by a circuit as shown in FIG. 5 in an arithmetic system with no carry such as “Theory of Information and Code”, Iwanami Course, 1982, Chapter 6). In Figure 5, *
B _i is a multiplier on the Galois field of m bits * m bits with B _i (i = 0, ..., N−1) as a multiplier, EX is an EXOR of m bits, and r is a register of m bits.

However, in multiplication on an integer, if a division operation as shown in FIG. 5 is performed, a carry occurs for each digit of the division operation, so that it is difficult to realize an efficient multiplier. Also,
In the multiplication circuit as shown in FIG. 5, the divided input values A _i (i = n
-1, ..., 1) must be serially input for each clock, and A _i cannot be simultaneously input for high-speed calculation.

The present invention eliminates the above-mentioned drawbacks, and when a multiplication circuit divides an input value having a large number of digits to perform an operation, a multiplier with a small number of digits is used to efficiently and quickly consider a carry. It is an object of the present invention to provide a multiplication circuit on integers that is highly scalable.

[0006]

To solve this problem, the integer multiplication circuit of the present invention uses an integer A of (n × m) bits when h, m, and n are positive integers. And (h ×
m) A multiplication circuit on an integer for performing multiplication with the bit integer B, which is the same processing element PE (0,0) to PE (n-1, h) arranged in a two-dimensional array of h rows × n columns. -1) and P of each row
E (i, 0) to PE (i, h-1) are the integer A divided by m bits A _i (i = 0, ..., n-1) and the integer B are divided by m bits B _j (J = 0, ..., h−1) are input at the same time, and in each PE (i, j), S _j ← A _i · B _j + S _j (j = 0,
, H-1) is calculated and output to PE (i + 1, j-1),
The outputs from (i, 0) and PE (n-1, j) are taken as the product of A and B. Further, the PE of the h row in which zero is input as the A _i
A and B with 2 more rows after the last row and including the final carrier
Outputs the product of.

Here, the PE is a multiplier for executing a multiplication of m bits × m bits, a 2-input 2m bit adder for adding the output of the multiplier and the calculation result of the PE at the preceding stage, and A 2-m-bit register for storing the output of the adder, a flip-flop for latching the carrier output of the adder and outputting it to the carrier input of the PE in the same row two columns later, and a delay circuit for delaying the B _i by one clock. Composed of and.

[0008]

[Embodiment] In this embodiment, an integer A of n · m bits and h · m
A multiplier with a bit integer B is assumed, but for the sake of simplicity, it will be described as h = n. This limitation does not lose generality. That is, it is considered that the two integers of n · m bits are A and B, and the operation of A · B = C is executed. Here, the multiplication a · b of two integers a and b of m bits
The multiplier for executing = c can be easily realized by a known structure such as a cell library or TTL.

When the integers A and B are each divided into m bits by n, they can be expressed as follows.

A = A _n- 1.X ^n-1 + A _n- 2.X ^n-2 + ...
+ A ₁ · X + A ₀ B = B _n-1 · X ^n-1 + B _n-2 · X ^n-2 + ... + B ₁ · X +
B ₀ Here, assuming that X = 2 ^m−1 , the bit sequences obtained by dividing the high-order digit by m bits for A and B are A _i and B _i (i
= N-1, ..., 0). In this case, since the integers A and B can be regarded as polynomials, A · B can be expressed as follows.

[0011]

[Equation 1] Therefore, the multiplier as shown in FIG. 1 can be configured. Figure 1
Is performed by pipeline processing with small identical arithmetic blocks called processing elements (PEs). Vertical PE (i, 0) to PE (i, n-1) in Fig. 1
, The same A _i (i = 0, ..., N-1) is set in advance. In the arrangement of FIG. 1, as shown in FIG. 2, each PE outputs B _j (j = 0, ..., N−1) to the PE to the right with a delay of one clock. Furthermore, when S _j is input from the PE diagonally to the left, S _j ← A _i · B _j + S _j is computed, the computation result S _j is output to the PE diagonally to the right, and the carrier output by this computation is output. every other PE to the right of cr
Output to. Although the data input / output of each PE differs depending on the PE arrangement method, the PEs have the same role.

The PE shown in FIG. 2 is constructed as shown in FIG. FIG. 3 shows multiplication of m bits × m bits a.b = c (in this example, A
a multiplier for performing _{i ·} a B _j), the register R ₁ of two 2m bits, and R _2, and two inputs of the 2m-bit adder, is composed of a flip-flop FF to latch the the carry cr from the adder It

In FIG. 1, the values B ₀ to B _n-1 are simultaneously input to the corresponding left n (column) n PE (0,0) to PE (0, n-1). All “0” s are input from diagonally above the left, which corresponds to S _j input of the PE at the left end (column) and the PE at the top end (row).

The leftmost (column) n PE (0,0) to PE (0, n)
-1), in accordance with the input of B _j (j = 0, ..., N-1), 2 m bits of A ₀ · B ₀ , A ₀ · B in the multiplier
₁ , ... A ₀ · B _n-1 are calculated. This is S _j = A ₀ ·
It is output as B _{j to} the PE on the lower right, and B is synchronized with it.
Output _j to the PE to the right. At this time, from the PE (0,0) at the lower end of the left end (column), C ₀ (= A ₀ ·
B ₀ ) is output.

Next, the second n from the left (second column) in FIG.
In PE (1,0) to PE (1, n-1), the left end (row)
S from the PE in the row one row above (left diagonally above)_j By
A ₀ ・ B_j + A₁ ・ B_j-1 Is calculated, and new S_j When
And output one below (third right below) the third (third column).
And the carrier cr output by the adder is flipped.
Latched by floppy FF, number 4 from the left on the same line
It is output to the PE of the fourth column (fourth column).

At this time, the PE (1,
0) is the output of the next digit, C ₁ (= A ₀ · B ₁ + A ₁
・ B ₀ ) is output. Multiplication result in PE A _i · B _j
Is 2 m bits for m bits of A _i and B _j , and is therefore the number of digits of X ² minutes. However, since the digit shift of the operation performed for each PE is X, the output carrier is 1
It is a carry signal for every other PE.

The same processing is repeated from the PEs (n-1,0) to PE (n-1, n-1) at the right end (column) in FIG. 1 to PE (0 at the bottom end). , 0) to PE (n-1,0) output the multiplication result of the values A and B up to X ^n-1 digits, and P at the right end (column)
From E (n-1,0) to PE (n-1, n-1), ^Xn-1 digit or more of A.
It can be seen that the multiplication result of B and the carrier are output.

In order to obtain a multiplication result which has also been added by the carrier, as shown in FIG.
(n, 0) ~ PE (n, n-1) and PE (n + 1,0) ~ PE (n + 1, n-1)
Or may be added, or n adders for performing only carrier addition operation may be added.

As described above, when the input value is divided into n bits every m bits and is input, n bits are input by using an m-bit multiplier.
-It was shown that an m-bit multiplication circuit can be realized at high speed by pipeline processing. It is obvious that the multiplication can be executed by the same circuit even when h ≠ n. As a result, when the value of the integer A is divided and input, the calculation of A and B is efficiently performed.

Although this circuit has a large number of PEs, it is realized by a simple regular structure of the same PE.
Etc. are easy to configure. Further, the control is the same for each PE, and the data operates in synchronization with the same clock, which can be realized very easily. Furthermore, no matter how large the number of digits of A and B is, just by adding PE, it is well expandable. In addition, since this method is carried out in synchronization with the clock for every other carry for every PE, there is no problem such as carry delay which is a problem in multiplication on an integer.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0022]

According to the present invention, when an input value having a large number of digits is divided and operated in a multiplying circuit, a multiplier having a small number of digits is used to take into account carry, which is efficient, fast, and scalable. A multiplication circuit on a certain integer can be provided.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of an integer multiplication circuit according to the present embodiment.

FIG. 2 is a diagram showing an input / output relationship of the PE of this embodiment shown in FIG.

FIG. 3 is a diagram showing the internal configuration of the PE of this embodiment shown in FIG.

FIG. 4 is a diagram showing a configuration including a final carry operation of a multiplication circuit on an integer according to the present embodiment.

FIG. 5 is a diagram showing a known polynomial multiplication circuit on a Galois field.

[Explanation of symbols]

PE ... Processing element, R ... 2m bit register, FF ... 1 bit flip-flop, * B _i
... m bits with B _i (i = 0, ..., N-1) as a multiplier *
Multiplier on Galois field of m bits, EX ... EX of m bits
OR, r ... m bit registers

Claims (3)

[Claims] 1. When h, m, and n are positive integers,
(N × m) bit integer A and (h × m) bit integer B
A multiplication circuit on an integer that multiplies with the same arithmetic element PE arranged in a two-dimensional array of h rows × n columns.
(0,0) to PE (n-1, h-1), and PE (i, 0) to PE (i, h-1) in each column is an integer A _{i obtained} by dividing the integer A by m bits. (I = 0, ..., n-1) and the integer B are m
B _j (j = 0, ..., h-1) divided for each bit is input at the same time, and S _j ← A _i · B _j + S at each PE (i, j).
_j (j = 0, ..., h-1) is calculated and output to PE (i + 1, j-1), and the outputs from PE (i, 0) and PE (n-1, j) are output. A
A multiplication circuit on an integer, which is a multiplication value of B. 2. The P of the h-th row in which zero is input as the A _i
E with 2 more rows after the last row, including the final carrier
The multiplication circuit on the integer according to claim 1, wherein the multiplication value of B is output. 3. The PE is a multiplier for executing a multiplication of m bits × m bits, a 2-input 2m-bit adder for adding the output of the multiplier and the calculation result of the PE at the preceding stage, and the addition. 2m bit register that stores the output of the adder and latch the output of the adder
And a flip-flop for outputting to the carrier input of B.
3. A multiplication circuit on an integer according to claim 1, comprising a delay circuit for delaying _i by 1 clock.