JPH06104750A - Bit number reduction circuit and frequency synthesizer using the same - Google Patents

Abstract

PURPOSE:To improve the resolution of the oscillation frequency of a frequency synthesizer. CONSTITUTION:A sawtooth wave circuit 1 which works with a reference signal fr is provided together with a sawtooth wave circuit 2 which works based on the division number N designated previously and the output of a voltage control oscillator VCO 8, and a digital phase comparator which controls the oscillation frequency of the VCO 8 based on the difference between the output of the circuit 1 and the output of the circuit 2. Furthermore a circuit which controls the oscillation frequency of the VCO 8 consists of a bit number reduction circuit 53 containing a DELTASIGMA type noise shaping circuit, a D/A converter 9, and an LPF 54. In such a constitution, a frequency synthesizer of the high resolution of 100Hz or less can be obtained even with a D/A converter of about 12 bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit number reduction circuit and a frequency synthesizer using the same, and more specifically, to an input signal having a data word length of a fixed number of bits rather than the data word length of the fixed number of bits. The present invention relates to a digital phase comparison type frequency synthesizer using a bit number reducing circuit for converting an output signal having a short bit number and using the bit number reducing circuit in a phase locked loop.

[0002]

2. Description of the Related Art Various types of frequency synthesizers are known, and in particular, frequency synthesizers using a phase locked loop are often used due to the development of integrated circuits. In a mobile communication device having a large number of communication channels, a phase-locked loop (PLL) is configured using a voltage controlled oscillator (VCO), a variable frequency divider, and a crystal oscillator, and the frequency division number of the variable frequency divider is selected. It uses a frequency synthesizer to generate the required communication channel frequencies. The PLL compares the phase of the signal obtained by dividing the output signal of the VCO with the variable frequency divider with the phase of the reference signal generated from the crystal oscillator output signal with the phase comparator, and after integrating the comparison result of the analog value with the filter. , V
It is configured to have a series of feedback loops applied to the frequency control terminal of CO. Since this phase comparison result contains high frequency components, it is necessary to increase the integral time constant of the above filter in order to remove these components. Therefore, the frequency division number of the variable frequency divider is changed to When the frequency is switched, it takes time to charge and discharge the capacitor that constitutes the filter, so that there is a problem that the frequency cannot be switched at high speed.

Since this problem is caused by outputting the phase comparison output as an analog value, a frequency synthesizer for solving this has been proposed (Reference: Kajiwara, Nakagawa "PLL synthesizer capable of high-speed frequency hopping",
IEICE Transactions B-2, Vol. J73-B
-2, No. 2, pp95-102, 1990, 2
Month). This proposed frequency synthesizer performs phase comparison itself by numerical calculation and removes high-frequency components included in the comparison result by simple calculation.It is possible to eliminate the need for a filter with a large integration time constant and reduce the frequency switching time. Can be shortened.

The operation principle of the numerical phase comparison DC conversion frequency synthesizer will be briefly described. First, one input of the phase comparator has a period T / K in synchronization with the phase of the reference signal.
A sawtooth wave having a peak value M that is increased by M / K every (where K is an arbitrary integer) and is reset every cycle T is input, and the VCO output signal is divided into the other input of the phase comparator. Number P
The frequency is divided by a counter (P is an arbitrary integer), is increased by a predetermined value B for each output frequency of the frequency synthesizer in synchronization with the counter output, and when the counter output exceeds M, the counter output is changed to M. A sawtooth wave having a configuration that reduces the frequency is input. The phase comparator takes the difference between the two sawtooth waves and outputs the phase difference between the two sawtooth waves. If the peak values of the two sawtooth waves are out of phase with each other, a jump of amplitude ± M of period T occurs in the output of the phase comparator. Therefore, the phase corrector absorbs this jump,
DC output of the phase comparator. The DC phase comparison value is converted into an analog value by a D / A converter, and then V
Applied to the frequency control terminal of CO. The oscillation frequency f _V of the VCO at this time can be expressed by the equation (1). f _V = (M × P) ÷ (B × T) (1) Since the phase comparison can be performed numerically in this way, the filter described above is not required, and high-speed frequency switching is possible.

[0005]

When the VCO is controlled using the D / A converter, the resolution of the D / A converter is a factor that determines the frequency setting accuracy of the frequency synthesizer.
For example, when the variable control range of the frequency of the VCO is 40 MHz, the number of bits required for the D / A converter is 19 bits or more to obtain a setting accuracy of 100 Hz or less. Since miniaturization and low power consumption are important issues in mobile communication devices, it is required to integrate a frequency synthesizer on a semiconductor substrate. However, since it is difficult to realize a D / A converter of 19 bits or more due to the limit of element accuracy in semiconductors, conventionally, the number of bits to be D / A converted is appropriately divided, and for example, a 12-bit D / A converter is used. Is divided into 7-bit D / A converters, and the output of each D / A converter is added to reduce the number of bits of each D / A converter. However, because of the addition, discontinuity occurs in the quantization level, and when used in a frequency synthesizer, the desired frequency setting accuracy cannot be obtained. Therefore, it is an object of the present invention to realize a frequency synthesizer which can be easily integrated on a semiconductor substrate, whose frequency can be switched at high speed, and whose frequency setting accuracy is high. Another object of the present invention is to provide an input signal having a data word length of a certain number of bits effective for realizing the above frequency synthesizer,
It is to realize a bit number reduction circuit for converting into a signal of a bit number shorter than the data word length of the constant bit number.

[0006]

To achieve the above object, the present invention converts an input signal having a data word length of a fixed number of bits into a signal having a bit number shorter than the data word length of the fixed number of bits. A first quantizer for quantizing the input signal; a noise shaping circuit for inputting a difference between the output of the first quantizer and the input signal; Of the quantizer output, and an adder for adding the output of the delay device and the output of the noise shaping circuit. That is, the first
The number of effective bits is reduced by using the quantizer of No. 1, the difference between the output of the first quantizer and the input signal is input to the noise shaping circuit, and the first quantizer is used by the second quantizer. After converting to the same bit number as the quantizer, the output of the first quantizer is corrected by the noise shaping circuit to reduce the bit number.

Further, the frequency synthesizer of the present invention comprises a first sawtooth wave circuit for generating a sawtooth wave based on a reference signal supplied from a reference oscillator, a frequency division oscillator N having a predetermined frequency division number N, and a voltage controlled oscillator. Oscillation of the voltage controlled oscillator from the second sawtooth wave circuit that generates a sawtooth wave based on the output, and the difference between the output of the first sawtooth wave circuit and the output of the second sawtooth wave circuit. A circuit for controlling the oscillation frequency of the voltage controlled oscillator in a frequency synthesizer using a so-called digital phase comparison circuit that performs frequency control and oscillates at an oscillation frequency proportional to the product of the reference signal and the frequency division number N. And a D / A for converting the output of the bit number reducing circuit into an analog signal.
It is composed of a converter and a low-frequency cutoff filter which receives the output of the D / A converter.

[0008]

The input of the bit number reduction circuit is defined as x, the output of the first quantizer as y, the noise shaping circuit output as e, and the bit number reduction circuit output as DA. In the first quantizer, the lower bits of the input signal x are reduced. The error (b) at this time can be expressed by equation (2). b = xy (2) b is input to the noise shaping circuit. The transfer function of the noise shaping circuit can be expressed by equation (3). here,
Nq represents the quantization noise of the second quantizer in the noise shaping circuit.

[Equation 3] i represents the order of the noise shaping circuit, i = 1 for the first order, and i = 2 for the second order. This corresponds to the number of integrators in the circuit configuration. In order to match the delay amounts of the outputs y and e of the first quantizer, y is given a delay amount corresponding to the order of the noise shaping circuit.

Since the delayed y and the noise shaping circuit output e are added, the bit number reduction circuit output DA is expressed by equation (4).

[Equation 4] From the equation (4), the output DA of the bit number reduction circuit is obtained by delaying the value of the input x and the quantization noise (N
It becomes a signal in which quantization noise in which q) is multiplied by the noise-shaped frequency characteristic is added. Next, since the quantization noise can be suppressed by a low-pass filter having a signal obtained by converting DA into an analog signal with a desired low-pass cutoff characteristic, the quantization noise is effectively reduced in a desired frequency band. Can create circuits. Here, the quantization noise multiplied by the noise-shaped frequency characteristic is distributed so as to have an apex at a frequency that is half the sample frequency.

As a reference on the technology of utilizing the noise shaping effect in a D / A converter, see “A 17-bit oversampling D / A” written by Yasuyuki Matsuya.
A-Conversion Technology Eusing Multi-Stage Noise Shaping, IEE Journal of Solid-State Circuit, Volume 24 4
Issue August 1989 (Yasuyuki Matsuya, "A 17-bit Oversa
mpling D-to-AConvertion Technology Using Multistag
e Noise Shaping ", IEEE Journal of Solid-State Citc
uit, vol. 24, No. 4, Aug. 1989) and Kunihara Uchimura "Oversampling D / A and D / A Converters with multi-stage noise shaping"
Modulator Eye E-E-Transaction on Acoustic Stick, Speech and Signal Processing Vol.36, No.12 December 1899 (Kuniharu Uchimura ,, "Ove
rsampling A-to-D and D-to-A Converters with Multist
age Noise Shaping Modulators ", IEEETransaction on
Acoustics, Speech, and Signal Processing, Vol.
36, No. 12, Dec. 1899). Therefore, the bit number reduction circuit utilizing the noise shaping effect of the above configuration converts frequency data with fine resolution of 19 bits or more into a digital signal with a small number of bits, and after D / A converting the signal, a low-pass cutoff filter is used. If used, the quantization noise converted into the high frequency region by the noise shaping is suppressed by the low-pass cutoff filter, so that the resolution is effectively increased even if the D / A converter with a small number of bits is used. A frequency synthesizer can be realized.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a frequency synthesizer according to the present invention. The frequency synthesizer has a reference signal fr, a frequency division number N, a frequency corrector control signal Fcont, an initial value Init and a gain switching signal Ga.
in is input and a signal SYN having a predetermined oscillation frequency is output. In this embodiment, the first sawtooth wave circuit 1 that generates a sawtooth wave from the reference signal fr, the second sawtooth wave circuit 2 that generates a sawtooth wave from the output of the prescaler 7, and the sawtooth wave circuit 1 are provided. The output of the first difference circuit 3 that obtains the difference of the output in a certain time, the second difference circuit 4 that obtains the difference of the output of the sawtooth wave circuit 2 in the certain time, and the output of the difference circuit 4 is the reference signal f.
a capture circuit 19 that synchronizes with r, a subtracter 18 that subtracts the output of the capture circuit 19 from the difference circuit 3, an integrator 5 that integrates the output Fsa of the subtractor 18, and a sample period of the output of the integrator 5 is reduced. Decimator 62, digital filter 6 for band limiting the output of integrator 5, subtractor 18
Of the sawtooth wave circuit 1 from the output Dout of the digital filter 6 and the frequency corrector 12 that generates a frequency error correction signal from the output Fsa of the digital filter 6, the adder 17 that adds the output of the frequency corrector 12 to the output Dout of the digital filter 6.
Phase difference detector 1 for detecting the initial phase difference between the outputs of 2 and 2
1. The gain setting circuit 10 for setting the initial value and changing the loop gain from the output DAGC of the adder 17, the output of the phase difference detector 11, the initial value Init given from the outside and the control signal of the control signal generator 47, Bit number reduction circuit 5 for reducing the number of effective bits of the output DAC of the gain setting circuit 10.
3. A D / A converter 9 for converting a signal whose effective bit number is reduced by the bit number reduction circuit 53 into an analog signal,
A low-pass filter (LPF) 54 that suppresses high-frequency noise included in the output of the D / A converter 9, a voltage-controlled oscillator (VCO) 8 whose frequency is controlled by the output of the LPF 54, and a reference signal fr that is frequency-divided A timing generator 21 for supplying an operation clock and a prescaler 7 for dividing the output of the VCO 8 at a division ratio of P or P + 1, a reference signal fr, a frequency division number N given from the outside, and the sawtooth wave circuit 1, 2 and a control signal generator 47 for generating a control signal from each peak signal.

Next, the operation of this embodiment will be described. Here, for the sake of explanation, the case where the reference signal f _r = 12.8 MHz prescaler frequency division ratio P = 128 frequency division number N = 38000 is described, but these parameters are not limited to the above numerical values and can be operated with arbitrary numerical values. is there. In the sawtooth wave circuit 1, a sawtooth wave having an increase rate equal to the frequency division number N given from the outside is generated at every rise of the clock CLKR1 obtained by dividing the reference signal fr by the frequency division number R ₁ . The difference circuit 3 takes the difference between the output of the sawtooth wave circuit 1 and the output of the sawtooth wave circuit 1 at the immediately preceding timing. Therefore, the output of the difference circuit 3 becomes N which is a constant value for each clock CLKR1. Here, the maximum value M of the sawtooth wave circuits 1 and 2 is given by the equation (5). M = N × R ₂ (5) Further, the period T of each sawtooth wave can be expressed by equation (6). In _{T = R 1 × R 2 ÷} f r ... (6) (5) and equation (6), the dividing number R ₁ and R ₂ is an arbitrary integer.

Here, when the operation of the differential circuit 3 is performed, a value of NM is generated at the output of the differential circuit 3 at the next timing when the sawtooth wave circuit 1 exceeds the maximum value M. In the example, only at this timing, a constant value N is output with M = 0. This can prevent ± M jumps included in the phase comparison result. In the sawtooth wave circuit 2 and the difference circuit 4, the prescaler 7 output CLK as well as the operation by the sawtooth wave circuit 1 and the difference circuit 3.
The modulus signal of the prescaler (MO
D) P or P + 1 is output. Since the output of the difference circuit 4 is a signal that is asynchronous with respect to the reference signal fr,
The capture circuit 19 performs the synchronous / asynchronous conversion described below.

FIG. 2 is a block diagram showing the configuration of the fetch circuit 19 of FIG. 1, and FIG. 3 is a timing chart for explaining the operation of the fetch circuit 19. Capture circuit 19
Is a flip-flop 22 set by the rising edge signal CK2E of the output CLKP of the prescaler 7,
Register 23 for outputting the output of the flip-flop 22 to the Q output on the rising edge signal CK1RE of the reference signal f _r,
A delay circuit 25 that delays the edge signal CK1RE by a certain delay time, an AND circuit 24 that takes the logical product of the output CK1R-Delay of the delay circuit 25 and the output (b) of the register 23, and a register that takes in the modulus signal MOD at the timing of CK2E. 28, a register 29 for taking the output of the register 28 by the output (c) of the AND circuit 24, and an AND circuit 27 for taking the logical product of the output SYMOD of the register 29 and the output of the register 23. Capture circuit 1
The output of 9 is the most significant bit of the AND circuit 27, register 2
The Q output of 3 is the least significant bit, and all other bits are fixed values L.

In the timing chart of FIG. 3, CK1RE, CK2E, MO which are input signals of the fetch circuit 19 are shown.
D, internal signals CK1R-Delay, SYMO
D, (a), (b) and (c) and the output signals b _{0 to} b ₇ are shown. Also, to compare the signal position, the output CLKP of the reference signal f _r and prescaler 7 is also shown at the same time. CK1R
E is signal synchronized with the rising edge of the reference signal f _r, CK
2E is a signal synchronized with the rising edge of CLKP, CK1
R-Delay is a signal obtained by delaying CK2E for a certain time. There is no problem if the fixed time delay is larger than the delay time of the register 22. The modulus signal MOD changes in synchronization with the output CLKP of the prescaler 7,
Is "L", the frequency division number of the prescaler 7 is P, and "H" indicates that the frequency division number of the prescaler 7 is P + 1.

At the rising timing of CK2E, the output Q of the flip-flop 22 becomes "H". Since the fetch clock CK1RE of the register 23 to which the output Q of the flip-flop 22 is connected is a signal synchronized with f _r , in the present embodiment, the Q output (a) of the flip-flop 22 is fetched every 12.8 MHz to register It outputs (b) to the Q output of 23. Output of flip-flop 22 (a)
Is "H", and a rising edge of CK1RE occurs, the Q output (b) of the register 23 becomes "H". Next, when the Q output (b) of the register 23 is “H”, AN
The output (c) of the D circuit 24 is the delayed signal CK1R-Dela.
Since y is output, the Q output (a) of the flip-flop 22 is reset to "L".

The output (a) of the flip-flop 22
When the rising edge of CK1RE occurs when is “L”, the Q output (b) of the register 23 becomes “L”, and AN
Output (c) of D circuit 24 and Q of flip-flop 22
The output (a) holds "L". Flip-flop 22
The condition that the rising edge of CK1RE occurs when the output of is LOW is when the rising edge of CLKP does not occur between the previous rising edge of CK1RE and the rising edge of this time. The operation of the fetch circuit 19 is such that the Q output of the register 23 becomes "L" when the rising edge of CLKP does not occur between the previous rising edge of CK1RE and the rising edge of this time, and C
When the rising edge of LKP occurs, Q of register 23
The output becomes "H". As a result, CLKP that is asynchronous with respect to the reference signal fr is converted into a synchronous signal.

On the other hand, since MOD is also synchronized with CLKP, it is asynchronous with respect to the reference signal fr. Therefore, MO
D is also converted into a signal synchronized with fr using the registers 28 and 29. First, the MOD is input to the register 28 and captured by the output CLKP of the prescaler 7.
This is because the frequency division number of the prescaler 7 is specified by the MOD before the rising edge of the output CLKP of the prescaler 7, so that the delay times are matched. Next, the Q output of the register 28 is taken in the register 29 at the output timing of the AND circuit 24. AND circuit 2
The output (c) of 4 is a signal that outputs “H” when the rising edge of CLKP occurs between the previous rising edge of CK1RE and the rising edge of this time.
It is possible to obtain SYMOD which is a MOD signal synchronized with.

Finally, the output of the prescaler 7 and the MOD
Is synchronized with the reference signal fr to generate the output of the fetch circuit 19 by the AND circuit 27. When the frequency division number P of the prescaler 7 is 128 as in this embodiment, when P and P + 1 are represented by binary numbers, P is b.
₇ only the "H", P + 1 is b ₁ ~b ₆ 2 a bit is "H", the other of b ₇ and b ₀ is always "L".
Therefore, the output of the capture circuit 19 is CL between the previous rising edge of CK1RE and the rising edge of this time.
0 when the rising edge of KP does not occur, CLKP
Rising edge occurs, and SYMOD is "H".
, P + 1 when SYMOD is "L".

Next, returning to FIG. 1, the output of the fetch circuit 19 is input to the subtractor 18, and the difference from the output of the difference circuit 3 is calculated. The output of the subtracter 18 is the sawtooth wave circuits 1 and 2
Is the difference in the slopes of the two sawtooth waves. That is, the subtractor 1
By differentiating the eight outputs, a value proportional to the frequency deviation from the reference signal fr can be obtained. Next, the output Fsa of the subtractor 18 is
It is input to the integrator 5 and the frequency error corrector 12. First,
The signal input to the integrator 5 will be described. Integrator 5
Function integrates the frequency error component, the output of the integrator 5 outputs the phase difference component between the two sawtooth waves. The transfer function of the integrator 5 is expressed by equation (7).

[Equation 7]

The output of the integrator 5 is input to the decimator 62. The decimator 62 is a filter of the transfer function shown in the equation (8) and reduces the sample rate.

[Equation 8]

The output of the decimator 62 is input to the digital filter 6. The digital filter 6 is an integrator 5
It is for limiting the band of the phase difference component which is the output of, and the configuration is not particularly limited, but it is optimum from the relationship between the phase jitter component contained in the output signal SYN of the synthesizer and the frequency synthesizer convergence speed. You need to choose a configuration. In this embodiment, a moving average that is easy to realize is adopted. The transfer function is shown in equation (9). The period T of the sawtooth wave circuits 1 and 2 was selected as the range for obtaining the moving average.

[Equation 9] Here, R ₂ is represented by the equation (10).

[Equation 10] The output Dout of the digital filter 6 is added to the output of the frequency corrector 12 by the adder 17, and the gain setting circuit 10
Entered in.

FIG. 4 shows a block diagram showing the configuration of the frequency error corrector 12 of FIG. 1 and a timing chart for explaining the operation thereof. The other one of the branched outputs Fsa of the subtractor 18 is input to the frequency error corrector 12.
The frequency error corrector 12 receives the adder 30 that accumulates the output Fsa of the subtractor 18, a register 31, a register 32 that captures the Q output of the register 31, and a Q output of the register 32, and multiplies with the Q output of the register 32. A comparator 26 for selecting a coefficient, a selector 34 for selecting a desired coefficient by the output of the comparator 26, an output of the selector 34 and a register 32
It is composed of a multiplier 33 that performs multiplication with the Q output of the above, an adder 44 that integrates the output of the multiplier 33, and a register 45.
Four operation clocks Reset, CK1 and C shown in FIG.
Although not shown in the drawing of FIG. 1, K2 and CK3 are all signals supplied from the timing generation circuit 21.
The control signal Fcont is a signal input from the outside to control the operation of the frequency corrector 12.

The operation of the frequency error correction circuit 12 will be described below. The input signal Fsa of the frequency error correction circuit 12 and the Q output of the register 31 are added by the adder 30. The output of the adder 30 is again taken into the register 31 at the timing of CK1. Since the register 31 is reset by Reset, the number of times of CK1 included during the Reset clock is added. In addition, the register 31
The Q output of the register 31 is captured by the register 32 at a timing CK2 earlier than the resetting of. Therefore, the register 31 stores a numerical value proportional to the frequency error component for a certain period. The fixed period is not particularly limited, but here, a period that coincides with the cycle T of the sawtooth wave is selected and the number of additions is set to R ₂ represented by the equation (10).

The Q output of the register 32 is input to the multiplier 33 and the comparator 26. The relationship between the frequency error Δf and the value X of the register 32 is shown in equation (11).

[Equation 11] The comparator 26 has a configuration in which the addition rate of the correction value is variable according to the magnitude of the frequency error Δf. In the present embodiment, an example is shown in which the frequency error Δf has thresholds of ± 300 kHz and ± 150 kHz. Numerical values to be compared using the equation (11) are ± 24576 and ± 12288. The comparator 26 expresses these numerical values in a binary number and compares only the upper 8 bits.

FIG. 5 shows a truth table of the comparator 26 of FIG. When X <-24576, X> +24576, the coefficient a is selected. When −24576 <X <−12288 and 12288 <X <24576, the coefficient b is selected. When 12288 <X <12288, the coefficient c is selected. The value of the selected coefficient depends on the convergence speed to be realized and is not particularly limited. Comparator 2
A selection signal is output from 6, and the coefficient selected by the selector 34 is selected and is input to one side of the multiplier 33.
The output of the multiplier 33 is input to the adder 44. Adder 4
4 and the register 45 constitute an integrator and store the frequency correction value. Further, the register 45 is reset by the control signal Fcont. Output F of frequency error corrector 12
Hout is added to the digital filter 6 in the adder 17.
Is added to the output of and is input to the gain setting circuit 10.

FIG. 6 shows a phase difference detecting procedure between the output of the sawtooth wave circuit 1 and the output of the sawtooth wave circuit 2 of FIG. In the figure, the clock K _YO1 showing a peak timing of the sawtooth wave circuit 1, a clock K _yo2 indicative of peak timings of the saw-tooth-wave circuit 2, the dividing number N, the sawtooth wave circuit 2 internal dividing an externally applied Number Nx, input of D / A converter 9, phase difference detection signal Pcont, phase difference detector output Pout,
Frequency division switching signal Ncont and digital filter 6
The output Dout of is shown.

Although the cycle of the clock K _yo2 indicating the peak timing of the sawtooth wave circuit 2 is almost equal to the cycle T of the clock K _yo1 indicating the peak timing of the sawtooth wave circuit 1,
It is an asynchronous signal. Therefore, when the frequency division number N given from the outside is changed from N0 to N1 as shown in FIG. 6, the inclination of the sawtooth wave is changed in the middle of the sawtooth wave,
There is a problem of discontinuous operation. Therefore, the frequency division switching signal N is _generated at the next clock K _yo2 whose frequency division has been switched.
cont, and the frequency division number Nx inside the sawtooth wave circuit 2
To update. At the same time as this update timing, the input of the D / A converter 9 is changed to an initial value Init given from the outside, and the output Pout of the phase difference detector 11 is reset. From this state, the phase difference detection signal Pcont is generated after two clocks of K _yo1 . The input of the D / A converter 9 during this period is fixed to the initial value Init. This makes it possible to detect the phase difference during at least one cycle of the sawtooth wave. Since the phase difference between the two sawtooth waves is output from the digital filter 6 in synchronization with K _yo1 , the phase difference detector 11 holds the value as the phase difference detection signal Pcont. Therefore, the digital filter 6 output Dou
When t is P (0), P (1), P (2) ... From the point that the frequency division number N given from the outside is changed, P (2) is stored in the phase difference detector 11. . The output of the phase difference detector 11 Pout is used to correct the input of the D / A converter 9. The gain setting circuit 10 seeks correction.

FIG. 7 is a block diagram showing the configuration of the gain setting circuit 10 of FIG. 1, and FIG. 8 is a time chart for explaining the loop gain setting operation of the gain setting circuit 10. The gain setting circuit 10 has two functions: a function of setting a value obtained by correcting the initial value Init by the output Pout of the phase difference detector 11 and a function of changing the loop gain by a gain control signal Gain given from the outside.

The gain setting circuit 10 has a gain control signal Gai.
Gain designating circuit 3 for designating the gain designated by n
5, a multiplier 38 that takes the product of the input signal DAGC of the gain setting circuit 10 and the gain designation circuit 35, an adder 39 that adds the output of the multiplier 38 and the output of the correction value storage circuit 36, and the output of the multiplier 38. Multiplier 37 for multiplying with a constant β, multiplier 3
7 and the output of the correction value memory 36, an adder 40, a multiplier 46 that takes the product of the output Pout of the phase difference detector 11 and the output of the gain designation circuit 35, and an initial value Init given from the outside. 41 for obtaining the difference between the output of the multiplier 46 and the output of the multiplier 46, a selector 42 for switching between the output of the subtractor 41 and the output of the adder 40, a correction value storage circuit 36 for storing the output of the selector 42, a gain control signal Gain and The OR circuit 43 is configured to generate a timing for taking in the input of the correction value storage circuit 36 from the phase correction control signal Pget and the frequency division number switching signal Ncont.

The operation of the gain setting circuit 10 will be described below with reference to the time chart of FIG. Gain control signal Gain
Is a signal indicating the timing of switching the loop gain. The gain control signal Gain is input to the gain designation circuit 35, and the output of the gain setting circuit 10 is updated according to a predetermined gain switching width α at the rising edge of the gain control signal. Although the gain switching width α is not particularly defined, this embodiment shows the case where α = 0.5.

First, the frequency-division-number switching signal Ncont resets the gain designating circuit 35, and the output becomes 0. Therefore, the output of the multiplier 38 also becomes 0. The initial value Init given from the outside is the frequency division number switching signal Nc.
The output P of the phase difference detector 11 at the timing of ont
Since out is 0 and the phase / gain switching signal PGcont is “H”, it is input to the correction value storage circuit 36 via the adder 41 and the selector 42. Here, it is assumed that the Y output of the selector 42 is such that the B input is selected when the S input is “H” and the A input is selected when the S input is L. By the above operation, the output of the gain setting circuit 10 becomes the initial value Init given from the outside. The value _Hos (0) of the correction value storage circuit 36 at this time is expressed by the equation (12). H _os (0) = I _nit (12)

Next, the phase difference detection ends, and the phase difference detection signal Pcont is generated. The phase difference detection signal Pcont is the timing indicating the completion of the phase difference detection. At the same time as the phase difference is determined, the gain designation circuit 35
The output of is changed to a predetermined value. Since this value depends on the convergence speed, it is not specified in particular, but is set to 1 in this embodiment for simplicity. next,
The multiplier 46 calculates the product of the output Pout of the phase difference detector 11 and the gain designating circuit 35. The subtractor 41 calculates the subtraction between the output of the multiplier 46 and the initial value Init.
The output of the subtracter 41 is input to the correction value storage circuit 36 via the selector 42, and is held in the correction value storage circuit 36 by the phase correction control signal Pget that delays the phase difference detection signal Pcont.

As a result of the above, the value H _os of the correction value storage circuit 36 is
In (1), the output P of the phase difference detector 11 from the initial value Init
The value obtained by reducing out is held and is represented by the equation (13). _{H os (1) = I nit} -Pout ... (13) On the other hand, since the phase difference between the two sawtooth wave of the sawtooth wave circuit 1 and the sawtooth wave circuit 2 does not fluctuate abruptly, input DAGC the following sample By adding the values of the correction value storage circuit 36 by the adder 39, the phase difference values are canceled and the convergence operation is started with the initial value Init set from the outside as a reference.

Next, the first gain switching will be described. First, the phase / gain switching signal PGcont changes from “H” to “L”, and the A input is selected as the Y output of the selector 42. Phase / gain switching signal PGcon
There is no problem if the timing at which t is switched is the timing after the phase correction control signal Pget for storing the phase difference detection result in the correction value storage circuit. Next, the output of the multiplier 38 is multiplied by a constant β to be calculated in the multiplier 37. The above constant β =
1-α. In this embodiment, since α = 0.5 will be described, β = 0.5 here. Multiplier 37
The output is added to the output of the correction value storage circuit 36 in the adder 40. When the gain control signal is input, the output of the selector 42 is taken into the correction value storage circuit 36 at the rising edge thereof, and the output of the gain designating circuit 35 is updated to α times. The multiplier 38 calculates the multiplication between the updated output of the gain designating circuit 35 and the input of the gain designating circuit 10. The output of the multiplier 38 is added to the output of the correction value storage circuit 36 and input to the D / A converter.

The process of the operation described above will be described using the following equation. The result of comparing the two sawtooth waves before gain switching is DAGC (0), the result of comparing the two sawtooth waves after gain switching is DAGC (1), and the initial value before gain switching is corrected. The value is H _os (1), the correction value after gain switching is H
_os (2). The output G of the multiplier 38 at this time is expressed as (14) by using the input DAGC (0) of the gain designating circuit 10.
It becomes an expression. G = DAGC (1) × α (14) Further, the feedback signal D _ac (0) before gain switching is expressed by the equation (15). D _ac (0) = H _os (1) + DAGC (0) (15) At this time, the correction value H _os (1) is calculated by the multiplier 37 and the adder 40 as shown in formula (16). It changes and a new correction value _Hos (2) is calculated. _{H os (2) = H os} (1) + (1-α) × DAGC (0) ... (16)

Next, G after the gain switching shown in the equation (14) and the correction value _Hos (2) after the gain switching shown in the equation (16) are added by the adder 39 to obtain the equation (17). Thus, the feedback signal D _ac (1) after gain switching is obtained. D _ac (1) = G + H _os (2) = H _os (1) + DAGC (0) + α × (DAGC (0) -DAGC (1)) = D _ac (0) + α × (DAGC (0) -DAGC ( 1))… (17)

Therefore, the feedback signal after D _ac (1) is (1
As shown in equation (7), maintain continuity with the value before gain change,
Moreover, the gain at the time of feedback can be increased by α.
The gain switching from the second time onward is similarly performed, and the continuity with the value before the gain change can be maintained. Therefore, the gain can be changed in the form of 1, α, α ² , α ³ , ... As shown in FIG.

FIG. 9 is a block diagram showing the configuration of an embodiment of the bit number reduction circuit 53 of FIG. Bit number reduction circuit 5
3 reduces the number of bits while maintaining the effective accuracy of the output of the gain setting circuit 10 in which the loop gain is set. The bit number reduction circuit of FIG. 9 is a circuit that uses a noise shaping circuit that uses first-order ΔΣ oversampling, and an adder 65 that adds a periodic fluctuation waveform (dither) Qn to the output DAC of the gain setting circuit 10. , A first quantizer 55 that receives the output of the adder 65 and reduces a predetermined lower bit, a delay device 56 that delays a predetermined delay amount to the output of the quantizer 55, the gain setting circuit 10 , A subtractor 57 for subtracting the output of the quantizer 55 from the output DAC, a subtractor 59 for subtracting the output of the second quantizer 61 from the output b of the subtractor 57, and an integrator 6 for integrating the output of the subtractor 59.
0, a second quantizer 61 for quantizing the output of the integrator 60,
The adder 5 for adding the output e of the quantizer 61 and the delay device 56
It is composed of 8.

Next, the operation of the bit number reduction circuit 53 will be described. Here, the operating speed of the bit number reducer 53 is set to fr / 4, which is not particularly specified, but is sufficiently shorter than the cycle of the sawtooth wave of the sawtooth wave circuit 1 or 2. The periodic fluctuation waveform Qn is called dither and serves to enhance the noise shaping effect. Since dither is added as needed, there is no problem even if it is not used. The size of the dither may be any value as long as it does not affect the signal component, but here it is set to 1/4 of the number of bits truncated by the quantizer 55. Next, the output of the adder 65 is the quantizer 55.
Reduces the number of lower bits. When the frequency variable range of the VCO is 40 MHz, the number of bits of the signal DAC requires 19 bits or more to obtain a resolution of 100 Hz or less. The number of bits reduced by the quantizer 55 is not particularly limited, but the low pass filter 54
Is limited by the ability to suppress high frequency noise. Here, the cutoff frequency of the low-pass filter 54 is set to 10 kHz and the number of bits to be reduced is set to 7 bits so that the frequency shift due to the high frequency noise is 30 Hz or less. Further, there are methods such as rounding off or rounding down, but either method may be used here.

A subtracter 57 calculates the difference between the signal y whose lower bits are reduced by the quantizer 55 and the DAC. The output b of the subtractor 57 is the quantization error of the quantizer 55. Next, the output b is input to a first-order ΔΣ type noise shaping circuit composed of a subtractor 59, an integrator 60 and a quantizer 61. The output e of the first-order ΔΣ type noise shaping circuit is expressed by the equation (18). e = bz ~ ¹ + (1-z ~ ¹ ) Nq (18) where Nq is the quantization noise generated by the quantizer 61, and z
~ ¹ represents the sampling period.

On the other hand, the output y of the first quantizer 55 is given a delay corresponding to the above sample period by the delay device 56. The output e of the first-order ΔΣ-type modulation circuit is added by the adder 58 to a signal obtained by delaying the output y of the first quantizer 55 by one sample period.
Becomes equation (19). DA = yz + e ~ ¹ = xz ~ ¹ + (1-z ~ ¹ ) Nq (19) The quantization noise Nq generated by the quantizer 61 is uniformly distributed in a band of one half of the sample period. To be distributed. The three outputs of the bit number reduction circuit 5 are converted into analog signals by the D / A converter 9. The output of the D / A converter 9 is input to the low pass filter 54. Therefore, as shown in the equation (19), noise shaping is performed in the high frequency region due to the frequency characteristic of (1-z to ¹ ), and the high frequency noise component is suppressed by the low pass filter 54 having a cutoff frequency sufficiently lower than the sample period. can do.

FIG. 10 is a block diagram showing the configuration of another embodiment of the bit number reduction circuit 53 of FIG. The present embodiment is a circuit using second-order ΔΣ oversampling. Secondary Δ
The bit number reduction circuit by Σoversampling has a periodic fluctuation waveform (dither) in the output DAC of the gain setting circuit 10.
An adder 65 for adding Qn and an output of the adder 65 are input, and a first quantizer 55 for reducing a predetermined lower bit and a delay device 56 for delaying a predetermined delay amount to the output of the quantizer 55. , A subtractor 57 for subtracting the output of the quantizer 55 from the DAC, a subtracter 59 for subtracting the output of the second quantizer 61 from the output of the subtractor 57, and a first integration for integrating the output of the subtractor 59. 60, a subtracter 64 that subtracts the output of the double gain device 63 from the output of the integrator 60, a second integrator 62 that integrates the output of the subtractor 64, and a second integrator that quantizes the output of the integrator 62. It comprises a quantizer 61, a gain device 63 that doubles the gain of the output of the quantizer 61, and an adder 58 that adds the output of the quantizer 61 and the output of the delay device 56.

Similar to the bit number reduction circuit of FIG. 9, the periodic fluctuation waveform Qn is added to the input signal DAC by the adder 65. The output of the adder 65 is input to the quantizer 55 to reduce the lower bits. The subtracter 57 calculates the difference between the signal y whose lower bits are reduced by the quantizer 55 and the input signal DAC. The output b of the subtractor 57 is the quantization error of the first quantizer 55. Next, the output b is a quadratic ΔΣ type noise shaping formed by the subtractor 59, the first integrator 60, the subtractor 64, the second integrator 62, the second quantizer 61 and the gain unit 63. Input to the circuit. The output e of the secondary ΔΣ type noise shaping circuit is (2
0) expression. ^{e = bz ~ 2 + (1} -z ~ 1) 2 Nq ... (20)

On the other hand, the output y of the first quantizer 55 is given a delay corresponding to twice the sample period by the delay device 56. Next, the output e of the quadratic ΔΣ noise shaping circuit is added by the adder 58 to the signal obtained by delaying the output y of the quantizer 55 by two sample periods, so the output DA of the bit number reduction circuit 53 is (21). It becomes an expression. ^{DA = yz ~ 2 + e =} xz ~ 2 + (1-z ~ 1) 2 Nq ... (21)

When the quadratic ΔΣ type noise shaping circuit is used, the quantization noise Nq generated by the quantizer 61 is multiplied by the quadratic frequency characteristic as shown in the equation (21), so that a low-pass characteristic is obtained. The low-frequency cutoff characteristic required for the filter 54 can be relaxed. Further, the output of the low pass filter 54 is input to the frequency control terminal of the VCO 8 as a control signal of the VCO 8. The output of the VCO 8 is branched, one of which is output as the frequency synthesizer output SYN, and the other of which is input to the prescaler 7. The prescaler 7 performs frequency division by a predetermined frequency division number (P or P + 1) by the modulus signal MOD provided from the sawtooth wave circuit 2. The output of the prescaler 7 is input to the sawtooth wave circuit 2, and this series of feedback loops makes it possible to oscillate at a predetermined oscillation frequency as a frequency synthesizer. In the above-described embodiment, the case where the prescaler 7 has two frequency division numbers has been described, but the present invention is not limited to this and can be applied even when it has a fixed frequency division number.

FIG. 11 is a diagram showing the configuration of another embodiment of the frequency synthesizer according to the present invention. The difference from the embodiment shown in FIG. 1 is that there is no control signal from the sawtooth wave circuit 2 of FIG. 1 to the prescaler 7, and the third sawtooth wave circuit 13 is given from outside to give a numerical value B inversely proportional to the frequency division number. Since the other configurations are the same except for the configuration, the description of the operation is omitted. Also, the prescaler 7 is several hundred MH
It is a circuit necessary for oscillating a signal of z or more, and can be omitted in the case of less than that.

FIG. 12 is a block diagram showing the configuration of still another embodiment of the frequency synthesizer according to the present invention.
The positional relationship between the differencers 3 and 4 and the integrator 5 is changed so that the arithmetic processing is the same as that of the embodiment of FIG. The difference circuits 3 and 4 and the integrator 5 of FIG. 1 are deleted, and the corrector 15 and the difference circuit 14 are added. The corrector 15 is inserted between the output of the subtractor 18 and the digital filter 6, and the difference circuit 14 is inserted between the output of the subtractor 18 and the frequency error corrector 12. The compensator 15 generates ± M generated by the phase difference between the sawtooth wave circuit 1 and the sawtooth wave circuit 2.
It has a function to correct the jump of. This can be easily achieved by utilizing overflow if M is selected as a power of two.

In the above-described embodiment of the frequency synthesizer, an example in which each block is individually signal-processed has been shown, but the present invention is not limited to this embodiment, and the sawtooth wave circuit 1 constituting the frequency synthesizer, Sawtooth wave circuit 2,
Difference circuit 3, difference circuit 4, integrator 5, digital filter 6, gain setting circuit 10, phase difference detector 11, frequency corrector 12, sawtooth wave generation circuit 13, difference circuit 14, corrector 15, acquisition circuit 19 Alternatively, a part or all of the integrating circuit 20 and the control signal generator 47 may be configured to share an arithmetic unit such as a DSP (digital signal processor) to perform signal processing.

13 and 14 are block diagrams showing the configuration of an embodiment of an initial value setting type frequency synthesizer capable of setting an initial value according to the present invention. The embodiment of FIG. 13 has a circuit for storing the converged value of the previous frequency synthesizer, and sets the stored converged value as an initial value when the oscillation frequency of the next frequency synthesizer is set. Shows the configuration of. The initial value setting type frequency synthesizer is the frequency synthesizer 50 of FIG. 1, FIG. 11 or FIG. 12 and the convergence result DA of the frequency synthesizer 50 with the frequency division number N as an address.
The storage circuit 48 stores C and outputs the oscillation frequency of the next frequency synthesizer 50 corresponding to the frequency division number N as an initial value.

Since the contents stored in the memory circuit 48 retains a value which has no relation to the reset or oscillation frequency of the frequency synthesizer as an initial state, it is automatically set when the power is turned on or when a long time has passed. All the frequency division numbers N of the frequency division numbers N are set, and the operation of writing the convergence result DAC of the frequency synthesizer 50 for each frequency division number N is performed. Regarding the relationship between the VCO frequency control signal and the oscillation frequency, there are slow fluctuations such as temperature fluctuations. However, since the above fluctuations are fairly slow in units of several hours, once the contents of the memory circuit 48 are determined. The stored numerical value can be used as an initial value to be set in the next frequency synthesizer 50. The initial value is input to the Init terminal of the frequency synthesizer 50.

The embodiment shown in FIG. 14 shows an embodiment using a device for calculating the relationship between the VCO frequency control signal and the oscillation frequency as a function. The second initial value setting type frequency synthesizer stores a frequency synthesizer 50 having the configuration of FIG. 1, 11 or 12, and a signal DAC indicating the convergence result of the frequency synthesizer 50 with the frequency division number N as an address. Storage circuit 48, and a calculation device 49 for calculating the initial value of the oscillation frequency of the next frequency synthesizer based on the frequency division number N and the output of the storage circuit 48.

When the linearity of the oscillation frequency with respect to the VCO frequency control signal is good, the function of the oscillation frequency with respect to the VCO frequency control signal can be approximated by at least a linear function. Therefore, two parameters (slope and offset value) of the function of the oscillation frequency with respect to the frequency control signal of the VCO can be calculated from the convergence value of the frequency synthesizer 50 for at least two types of frequency division numbers of the memory circuit 48. The output of the arithmetic unit that has performed the above calculation is set to the input terminal Init as the initial value of the oscillation frequency of the next frequency synthesizer 50. Here, the approximation function of the oscillation frequency with respect to the VCO frequency control signal is not limited to the first order, and a higher-order approximation or a second-order approximation or higher order is obtained depending on the linearity of the oscillation frequency with respect to the VCO frequency control signal. A calculation method using the correlation value of the oscillation frequency with respect to the frequency N may be used.

FIG. 15 is a block diagram showing the configuration of an embodiment of a transmission apparatus using the frequency synthesizer of the present invention. This transmission apparatus is provided with a reference signal fr, a frequency division number N, and Fco.
nt, Gain, and Init are input, and a frequency synthesizer 50 that oscillates at a specified frequency, a memory circuit 48 that stores an initial value, a received modulated wave, and a demodulator that demodulates a received signal by a signal supplied from the frequency synthesizer 50 And a modulator 52 that outputs a transmission modulation wave by using a signal supplied from the frequency synthesizer 50 for the transmission signal. The frequency synthesizer 50 oscillates an oscillation frequency of fr × N based on the reference signal fr and the frequency division number N. Therefore, the demodulator 51 and the modulator 5
2, based on the oscillation frequency of fr × N,
Modulation and demodulation are performed. The transmission device and the reception signal can be exchanged by using the same configuration in the opposite transmission device. The present embodiment is only one example using the frequency synthesizer 50. For example, the oscillation frequency of the frequency synthesizer 50 is the modulator 52.
And the demodulator 51 are different, or the modulator 52 is time-divided.
It is also applicable to an example in which the oscillation frequency of the signal supplied to the demodulator 51 changes. Further, the control signals of Fcont and Gain are not necessarily required at the same time, and are supplied when the functions corresponding to them are used.

When the bit number reduction circuit of the present invention is used,
By using a D / A converter with a small bit length of 11 bits or 12 bits, it is possible to perform substantially the same operation as a D / A converter with a precision of 19 bits, and to control the voltage controlled oscillator of the PLL type frequency synthesizer. A frequency synthesizer having a high resolution of 100 Hz or less can be realized by using it in the section.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a frequency synthesizer according to the present invention.

FIG. 2 is a block diagram showing a configuration of a capture circuit 19 shown in FIG.

FIG. 3 is a timing chart for explaining the operation of a capture circuit 19 in FIG.

4 is an output of the sawtooth wave circuit 1 and the sawtooth wave circuit 2 of FIG.
Chart showing the procedure for detecting the phase difference from the output of

5 is a block diagram showing the configuration of the frequency corrector 12 of FIG. 1 and a timing chart for explaining the operation thereof.

6 is a diagram showing a truth table of the comparator 26 of FIG.

7 is a block diagram showing a configuration of a gain setting circuit 10 in FIG.

FIG. 8 is an operation time chart of the gain setting circuit 10.

9 is a block diagram showing a configuration of an embodiment of a bit number reduction circuit 53 of FIG.

10 is a block diagram showing a configuration of an embodiment of a bit number reduction circuit 53 of FIG.

FIG. 11 is a block diagram showing the configuration of another embodiment of the frequency synthesizer according to the present invention.

FIG. 12 is a block diagram showing the configuration of still another embodiment of the frequency synthesizer according to the present invention.

FIG. 13 is a block diagram showing a configuration of an embodiment of an initial value setting type frequency synthesizer capable of setting an initial value according to the present invention.

FIG. 14 is a block diagram showing a configuration of another embodiment of an initial value setting type frequency synthesizer capable of setting an initial value according to the present invention.

FIG. 15 is a configuration diagram of a transmission device using the frequency synthesizer of the present invention.

[Explanation of symbols]

1, 2, 13 ... Sawtooth wave circuit 3, 4, 14 ... Difference circuit 5 ... Integrator 6 ... Digital filter 7 ... Prescaler 8 ... Voltage controlled oscillator (VCO) 9 ... D / A converter 10 ... Gain setting circuit 11 ... phase difference detector 12 ... frequency corrector 15 ... corrector 17 ... adder 18 ... subtractor 19 ... acquisition circuit 20 ... integration circuit 21 ... timing generation circuit 22 ... flip-flop 23 ... registers 24, 27 ... AND circuit 25 ... Delay circuit 26 ... Comparator 28, 29, 31
Register 30 ... Adder 32 ... Register 34 ... Selector 33 ... Multiplier 35 ... Gain designating circuit 36 ... Correction value storage circuit 37, 38 ... Multiplier 39 ... Multiplier 40 ... Adder 41 ... Subtractor 42 ... Selector 43 ... OR circuit 44 ... Adder 45 ... Register 46 ... Multiplier 47 ... Control signal generator 48 ... Storage circuit 49 ... Arithmetic device 50 ... Frequency synthesizer 51 ... Demodulator 52 ... Modulator 53 ... Bit number reduction circuit, 54 ... LPF 55 ... first quantizer 56 ... delay device 57 ... subtractor 58 ... adder 59 ... subtractor 60 ... first integrator 61 ... second quantizer 62 ... second integrator 63 ... gainer 64 … Subtractor 65… Adder

Claims (9)

[Claims] 1. A bit number reduction circuit for converting an input signal having a data word length of a fixed number of bits into an output signal having a bit number shorter than the data word length of the fixed number of bits, wherein the input signal is a quantum signal. A first quantizer for converting, a first subtracter for taking the difference between the output of the upper first quantizer and the input signal, and noise shaping using the output of the first subtractor as input A circuit, a delay device for delaying the output of the first quantizer, and an adder for adding the output of the delay device and the output of the noise shaping circuit to obtain the output signal. A bit number reduction circuit characterized by the above. 2. The bit number reducing circuit according to claim 1, wherein the noise shaping circuit takes a difference between the output of the first subtractor and the output of the second quantizer, A bit number reduction circuit comprising a first integrator that integrates the output of the second subtractor and the second quantizer that quantizes the output of the first integrator. . 3. The bit number reducing circuit according to claim 1, wherein the noise shaping circuit takes a difference between the output of the first subtractor and the output of the second quantizer, and A first integrator that integrates the output of the second subtractor, a third subtractor that subtracts the output of the gain device from the output of the first integrator, and an output of the third subtractor A second integrator for integrating, a second quantizer for quantizing the output of the second integrator, and an output of the second quantizer for 2
A bit number reduction circuit characterized by comprising the above-mentioned gain device for giving a double gain. 4. A bit number reducing circuit for converting an input signal having a data word length of a fixed number of bits into an output signal having a bit number shorter than the data word length of the fixed number of bits, wherein the input signal has a cycle. An adder that adds signals that change dynamically,
A first quantizer for quantizing the output of the adder; a first subtractor for taking the difference between the output of the upper first quantizer and the input signal; and a first quantizer of the first subtractor A noise shaping circuit whose output is an input, a delay device that delays the output of the first quantizer, and an adder that adds the output of the delay device and the output of the noise shaping circuit to obtain the output signal A bit number reduction circuit characterized by being configured to have. 5. A first sawtooth wave circuit for generating a sawtooth wave based on a reference signal supplied from a reference oscillator, and a sawtooth wave based on a preset frequency division number and an output of a voltage controlled oscillator. Generating a second sawtooth wave circuit, an output of the first sawtooth wave circuit, and an output of the second sawtooth wave circuit from the first and second sawtooth wave circuits. Has a digital phase comparison circuit for detecting the phase difference of the voltage control oscillator and a circuit for controlling the oscillation frequency of the voltage controlled oscillator by the output of the digital phase comparison circuit, and the oscillation frequency proportional to the product of the reference signal and the frequency division number. In the frequency synthesizer that oscillates according to claim 1, the circuit for controlling the oscillation frequency of the voltage controlled oscillator includes a bit number reduction circuit according to claim 1 or 4, and D / A conversion for converting the output of the bit number reduction circuit into an analog signal. If, frequency synthesizer, characterized in that it is configured to have a low frequency cutoff filter which receives the output of the D / A converter. 6. A digital signal processing device is used in common for part or all of the first sawtooth wave circuit, the second sawtooth wave circuit, the digital phase comparison circuit, and the bit number reduction circuit to perform signal processing. A frequency synthesizer characterized by performing. 7. The frequency synthesizer according to claim 5, further comprising: storing the input value of the bit number reduction circuit at the time of convergence of the voltage controlled oscillator, using the frequency division number as an address, and newly setting the voltage control. A frequency synthesizer comprising a memory circuit for outputting the oscillation frequency of an oscillator as an initial value. 8. The frequency synthesizer according to claim 5, further comprising a memory circuit for storing the input value of the bit number reducing circuit at the time of convergence of the voltage controlled oscillator, using the frequency division number as an address, and newly setting the memory circuit. An arithmetic unit for calculating the control signal of the voltage controlled oscillator from the input value of the bit number reduction circuit read from the storage circuit by the frequency division number and setting it as the initial value of the voltage controlled oscillator is configured. A frequency synthesizer characterized by that. 9. A transmission device having the frequency synthesizer according to claim 5, 6, 7 or 8, and a demodulator and a modulator to which a signal of an oscillation frequency from the frequency synthesizer is added.