JPH0677822A - Frequency synthesizer - Google Patents

Abstract

PURPOSE:To switch the oscillating frequency of a frequency synthesizer at a high speed. CONSTITUTION:The frequency synthesizer provided with a 1st sawtooth wave circuit 1 operated by a reference signal fr and a 2nd sawtooth wave circuit 2 operated by a predetermined frequency division number N and an output of a voltage controlled oscillator (VCO) and in which the oscillating frequency of the VCO is controlled based on a difference between an output of the sawtooth wave circuit 1 and an output of the sawtooth wave circuit 2 is provided with a control signal generator 47 detecting the revision of the frequency division number N and with a phase error detector 11 correcting an initial value given in advance based on a phase difference between the two sawtooth waves. Thus, an initial value of the frequency synthesizer is given externally and the switching convergence time is set to be within 1msec.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency / frequency synthesizer using a phase locked loop and a device using the same. In particular, the present invention relates to a method and a configuration method of a frequency synthesizer suitable for a mobile communication device that needs to switch communication frequencies at high speed.

[0002]

2. Description of the Related Art Various methods are known for constructing a frequency synthesizer (Reference: V. Manaseewitsh, "Fre
quency Synthsizer Theory and Design ", pp.0-39, J
OhnWiley & Sons, New York, 1976), especially the construction method using a phase locked loop is often used due to the development of integrated circuits.

In a mobile communication device having a large number of communication channels, a phase-locked loop (PLL) is formed by using a voltage controlled oscillator (VCO), a variable frequency divider, and a crystal oscillator, and the frequency division number of the variable frequency divider is set. A frequency synthesizer is used to select and generate the required communication channel frequency. PLL
Is a phase comparator that compares the phase of the signal obtained by dividing the output signal of the VCO with the variable frequency divider with the phase of the reference signal generated from the crystal oscillator output signal, and integrates the comparison result of the analog values with the filter. After that, a series of feedback loops are applied to the frequency control terminal of the VCO. Since the phase comparison result includes high frequency components and the like, it is necessary to increase the integral time constant of the filter in order to remove these components. Therefore, when switching the communication channel frequency by changing the frequency division number of the variable frequency divider, there is a problem that the frequency cannot be switched at high speed because it takes time to charge and discharge the capacitor.

Since this problem is caused by outputting the phase comparison output as an analog value, a method of constructing a frequency synthesizer that solves this problem has been proposed (Reference: Kajiwara,
Nakagawa "PLL Synthesizer with Fast Frequency Hopping", IEICE Transactions B-II, Vol. J73-BI
I, No. 2, pp95-102, February 1990). This proposed method is called the numerical phase comparison DC conversion frequency synthesizer method here. The above method is a method in which the phase comparison itself is performed by numerical calculation and the high frequency components included in the comparison result are removed by simple calculation. This makes it possible to eliminate the need for a filter having a large integration time constant and reduce the frequency switching time.

The operation principle of the numerical phase comparison DC conversion frequency synthesizer system will be described below.

First, one input of the phase comparator is increased by M / K in every cycle T / K (K is an arbitrary integer) in synchronization with the phase of the reference signal, and is reset in every cycle T. A sawtooth wave having a value of M is input, and the VCO output signal is divided into the other input of the phase comparator by a counter having a division number P (P is an arbitrary integer), and the frequency synthesizer is synchronized with the counter output. Is increased by a predetermined numerical value B for each output frequency. When the counter output exceeds M, a sawtooth wave having a configuration of subtracting M from the counter output is input.

Then, the phase comparator takes the difference between the two sawtooth waves and outputs the phase difference between the two sawtooth waves. If the peak values of the two sawtooth waves are out of phase with each other, a jump of ± M occurs in the output of the phase comparator. Therefore, the phase corrector absorbs this jump and converts the output of the phase comparator into a direct current. This DC conversion phase comparison value is D /
After being converted into an analog value by the A converter, it is applied to the frequency control terminal of the VCO. VCO oscillation frequency f _V at this time
Can be expressed by (Equation 1). f _V = (M × P) ÷ (B × T) (Equation 1) Since the phase comparison can be performed numerically in this way, the filter described above is not required, and high-speed frequency switching is possible.

[0008]

Since the sawtooth wave generated from the reference signal and the sawtooth wave generated from the VCO are asynchronous with each other, even if a reset signal is applied at the same time, the phases of the two sawtooth waves are increased. Cannot be an exact match. Therefore, when the initial value that approximates the oscillation frequency of the frequency synthesizer is directly added to the D / A converter to further reduce the convergence time, the oscillation frequency of the frequency synthesizer has the initial value because it has the phase difference described above. There is a point that it is not possible to obtain the expected initial oscillation frequency due to deviation from the given oscillation frequency.

In the process of converging the oscillation frequency of the frequency synthesizer, the loop gain is increased at the initial stage of the converging process in order to speed up the converging speed, and at the end stage of the converging, the loop gain is decreased to suppress the fluctuation of the oscillation frequency. In the case of the configuration, when the loop gain is changed, the input of the VCO depends on the phase difference between the two sawtooth waves described above, so that the oscillation frequency also changes at the same time, and the oscillation frequency becomes discontinuous.

Finally, the convergence point of the above frequency synthesizer is the point where the phase relationship between the two sawtooth waves has a constant value. Therefore, when there is a phase difference between the two sawtooth waves and the oscillation frequency of the frequency synthesizer deviates from the normal oscillation frequency, the frequency synthesizer waits until the phase difference between the two sawtooth waves becomes the correct phase difference. The oscillating frequency also has a deviated value, and an operation of shifting the phase difference between the two sawtooth waves is performed by the frequency difference. Therefore, since there is a frequency difference until the correct phase difference is obtained, there is a point that the convergence is delayed.

[0011]

With respect to the first point, while the initial value is being given, the feedback loop described above is released, and D /
The output of the A converter is fixed to the initial value given from the outside.
Then, after detecting the phase difference, the process of correcting the initial value given from the outside is performed.

With respect to the second point, the input value of the D / A converter controlling the VCO immediately before the gain is switched is stored, and the phase comparison result output after the gain is switched is corrected. It was configured.

Finally, for the third point, the frequency deviation component of the VCO oscillation frequency with respect to the reference frequency is detected, and when the frequency deviation is large, the direct frequency deviation component is irrelevant regardless of the phase difference between the two sawtooth waves. D / A converted to VCO
A frequency corrector for controlling the signal is provided. However, since the signal processing error with respect to the above frequency deviation is large, VC
Only when the frequency deviation between the oscillation frequency of O and the reference signal is large, the frequency deviation component becomes a feedback signal to the VCO. As a result, when the oscillation frequency of the current frequency synthesizer has a large deviation from the frequency to be oscillated, the frequency deviation is directly D / A converted and V
When the oscillation frequency of the current frequency synthesizer has a small frequency deviation from the frequency to be oscillated as a frequency control signal to the CO, the phase difference between the conventional sawtooth waves is D /
A-converted to become a VCO frequency control signal.

[0014]

The above-mentioned method of comparing the two sawtooth waves has a feature that the frequency deviation can be directly obtained. The slope of the comparison result between the two sawtooth waves is a value proportional to the frequency deviation between the VCO and the reference signal. Therefore, the frequency deviation component is integrated and converted into a phase difference signal, and VC
A signal for controlling O is obtained. Here, when the initial value is given from the outside, the constant term at the time of integration needs to match the initial value given from the outside. However, the constant term is not uniformly determined because the phase difference between the two sawtooth waves is included as an offset component. Therefore, while the initial value is being given, the feedback loop described above is released and the D / A converter output is fixed directly to the initial value given from the outside. And
After detecting the phase difference between the two sawtooth waves in the meantime, by performing the process of correcting the initial value given from the outside by the phase difference between the two sawtooth waves, the constant term at the time of integration is changed. It is possible to confirm and set the correct initial value.

Similarly, when the gain is switched, the slope of the result of the comparison between the two sawtooth waves is discontinuous before and after the gain is switched, so that the constant term at the time of integration cannot be determined.

The detailed operation at the time of gain switching will be described below by using mathematical expressions.

By switching the gain, the gain of the feedback loop becomes α
Suppose it is doubled. Also, the result of comparing the two sawtooth waves before gain switching is DAGC (0), the result of comparing the two sawtooth waves after gain switching is DAGC (1), and the initial value before gain switching. The corrected value is defined as _Hos (1), and the corrected value after gain switching is defined as _Hos (2).

First, the feedback signal D _ac (0) before gain switching is expressed by ( _Equation 2). D _ac (0) = H _os (1) + DAGC (0) (Equation 2) The result G obtained by comparing the two sawtooth waves after the gain switching is multiplied by the gain α, and thus becomes (Equation 3). G = DAGC (1) × α (Equation 3) At this time, the correction value H _os (1) is changed as in the equation (4), and the correction value H _os (2) is calculated. _{H os (2) = H os} (1) + (1-α) × DAGC (0) ... ( Equation 4) Next, gain switching shown after gain switching shown in equation (3) of the G (Equation 4) The subsequent correction value _Hos (2) is added to form the feedback signal _Dac (1) after gain switching as shown in (Equation 5). D _ac (1) = G + H _os (2) = H _os (1) + DAGC (0) + α × (DAGC (0) -DAGC (1)) = D _ac (0) + α × (DAGC (0) -DAGC ( 1)) (Equation 5) As described above, the feedback signal after D _ac (1) maintains continuity with the value before gain change as shown in (Equation 5), and
The loop gain can be set to α times.

Finally, the slope of the result obtained by comparing the two sawtooth waves is a value proportional to the frequency deviation between the VCO and the reference signal as described above. Therefore, directly set this value to V
If the configuration is such that the signal is fed back as a frequency control signal to the CO, it is not necessary to change the phase difference of the sawtooth wave as compared with the case where only the signal based on the phase difference of the sawtooth wave is fed back, so high-speed convergence is possible. Becomes Further, since the frequency corrector operates only when the frequency deviation of the VCO oscillation frequency from the reference frequency is large, it does not affect the stability after convergence.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows the configuration of an embodiment of the present invention. The frequency synthesizer includes a reference signal fr, a frequency division number N, a frequency corrector control signal Fcont, an initial value Init, and
The gain switching signal Gain is input, and a signal having a predetermined oscillation frequency is output from SYN.

The present invention comprises a first sawtooth wave circuit 1 for generating a sawtooth wave from the reference signal fr, a second sawtooth wave circuit 2 for generating a sawtooth wave from the output of the prescaler 7, and the first sawtooth wave. The first difference circuit 3 for obtaining the difference between the outputs of the linear wave circuit 1 and the second difference circuit 4 for obtaining the difference between the outputs of the second sawtooth wave circuit 2 and the output of the second difference circuit 4 are used as the reference signal fr. And a synchronizing circuit 20, a integrating circuit 20 for integrating the output of the capturing circuit 19 for a certain period, a subtracter 18 for subtracting the output of the integrating circuit 20 from the first difference circuit 3, and an output of the subtracter 18 (Fsa) The digital filter 6 for band limiting the output of the integrator 5, the frequency corrector 12 for generating a frequency error correction signal from the output (Fsa) of the subtractor 18, and the digital corrector 12 for outputting the frequency corrector 12. Adder 17 which adds the filter 6 the output (Dout), the digital filter 6 outputs (Dou
From t), a phase difference detector 11 for detecting an initial phase difference between the two sawtooth wave circuits 1 and 2 outputs, the adder 17 output (DAGC), the phase difference detector 11 output, and an externally applied initial stage A gain setting circuit 10 for setting an initial value and changing a loop gain based on a value (Init) and a control signal of the control signal generator 47, the gain setting circuit 10 output (DAC)
D / A converter 9 for converting a digital signal into an analog signal, the above D / A
Voltage controlled oscillator (V
CO) 8, a timing generation circuit 2 for dividing the reference signal fr and supplying the operation clock of the frequency synthesizer.
1 and a prescaler 7 that divides the output of the VCO 8 at a division ratio of P or P + 1, a reference signal fr and a division number N given from the outside, and the first and second sawtooth wave circuits 1 and 2. The control signal generator 47 generates a control signal from each of the peak signals.

Next, the operation of this embodiment will be described. Here, for the sake of explanation, the case where the reference signal f _r = 12.8 MHz prescaler frequency division ratio P = 128 frequency division number N = 38000 is described, but these parameters are not limited to the above-mentioned values and can be operated at any values. is there.

In the first sawtooth wave circuit 1, a sawtooth wave having an increase rate equal to the frequency division number N given from the outside is generated at every rise of the clock (CLKR1) obtained by dividing the reference signal fr by R ₁ . The output of the first sawtooth wave circuit 1 is the first
In the difference circuit 3 of the above
Of the sawtooth wave circuit 1 is taken. Therefore, the output of the first difference circuit 3 becomes N which is a constant value for each CLKR1.

Here, the maximum value M of the first and second sawtooth wave circuits 1 and 2 is given by (Equation 6). M = N × R ₂ (Equation 6) Further, the period T of each sawtooth wave can be expressed by the equation (Equation 7). _{T = R 1 × R 2 ÷} f r ... ( 7) (6) and the equation (7), R ₁ and R ₂ is an arbitrary integer.

When the operation of the first differential circuit 3 is performed, the output of the first differential circuit 3 is output at the next timing when the first sawtooth wave circuit 1 exceeds the maximum value M. NM
However, in this embodiment, a constant value N is output with M = 0 only at this timing. This can prevent ± M jumps included in the phase comparison result.

Also in the second sawtooth wave circuit 2 and the second difference circuit 4, the output of the prescaler 7 (CLK is the same as the operation by the first sawtooth wave circuit 1 and the first difference circuit 3).
P) every rising edge of the prescaler modulus signal (MO
D) P or P + 1 is output. Since the output of the second difference circuit 4 is a signal that is asynchronous with respect to the reference signal fr, the capture circuit 19 performs synchronous / asynchronous conversion.

FIG. 2 shows the configuration of the fetch circuit 19, and FIG. 3 shows an operation timing chart.

The capture circuit has a prescaler 7 output (C
Flip-flop 22 which is set by the LKP) rising edge signal (CK2E), the rising edge signal of the flip-flop 22 outputs a reference signal (f _r) (CK
1RE) register 23 for outputting to Q output, CK1R
A delay circuit 25 for delaying E by a constant delay time, an AND 24 for taking a logical product of the output of the delay circuit 25 and the output of the register 23, and the modulus signal (MOD) as CK2E.
Register 28 to be loaded at the timing
A register 29 for fetching 8 outputs by AND24 output, the register 29 output (SYMOD) and the register 23
It is composed of an AND 27 that takes a logical product with the output. The AND 27 of the output of the fetch circuit 19 is the most significant bit, the Q output of the register 23 is the least significant bit, and all other bits have a fixed value L.

In the timing chart of FIG. 3, CK1RE, CK2E, MOD which are input signals of the fetch circuit, CK1R-Delay, SYMOD which are internal signals,
(A), (b), shows the (c), and the output signal b ₀ ~b _7. Further, in order to compare the signal positions, the reference signal ( _fr )
And the prescaler 7 output (CLKP) are also shown.

[0031] CK1RE the signal synchronized with the rising edge of f _r, CK2E the signal synchronized with the rising edge of CLKP, CK1R-Delay is a signal obtained by a predetermined time delay CK2E. There is no problem if the delay time is larger than the delay time of the register 22. Also, MOD is CLKP
When the MOD is L, the prescaler frequency division number is P, and when the MOD is H, the prescaler frequency division number is P + 1.

The operation of the fetch circuit 19 will be described below.

At the rising timing of CK2E, the output Q of the flip-flop 22 becomes H. Since the fetch clock CK1RE of the register 23 to which the output Q of the flip-flop 22 is connected is a signal synchronized with f _r , in the present embodiment, the Q of the flip-flop 22 is generated every 12.8 MHz.
The output is fetched and output to the Q output of the register 23.

CK when flip-flop 22 output is H
When the rising edge of 1RE occurs, the Q output of the register 23 becomes H. Next, when the Q output of the register 23 is H, the AND 24 output is CK1R-Delay, so the Q output of the flip-flop 22 is reset to L.

When the rising edge of CK1RE occurs when the output of the flip-flop 22 is L, the Q output of the register 23 becomes L and the AND 24 output and the Q output of the flip-flop 22 hold L. The condition that the rising edge of CK1RE occurs when the output of the flip-flop 22 is L is that the rising edge of CLKP does not occur between the previous rising edge of CK1RE and the rising edge of this time.

To summarize the operation of the fetch circuit described above, when the rising edge of CLKP does not occur between the previous rising edge of CK1RE and the rising edge of this time, the Q output of the register 23 becomes L, CLK
When the rising edge of P occurs, the Q output of the register 23 becomes H. As a result, CLKP that is asynchronous with respect to the reference signal fr is converted into a synchronous signal.

On the other hand, MOD is also asynchronous with respect to the reference signal fr because it is also synchronized with CLKP. Therefore, MO
D is also converted into a signal synchronized with fr using the registers 28 and 29.

First, the MOD is input to the register 28 and fetched by the prescaler 7 output CLKP. This is because the frequency division number of the prescaler 7 is specified by the MOD before the rising edge of the prescaler 7 output CLKP, so that the delay times are matched. Next, the Q output of the register 28 is taken in the register 29 at the output timing of the AND 24. AND24 output is CK1RE
Is a signal that outputs H when the rising edge of CLKP occurs between the previous rising edge of CLKP and the rising edge of this time.
MOD can be obtained.

Finally, the output of the prescaler 7 and the signal obtained by synchronizing the MOD with the reference signal fr are used to capture the signal.
The output of 9 is generated by AND27. If the 128 frequency division number P of the prescaler as in this embodiment, when the table view of the P and P + 1 by a binary number, P only b ₇ H, 2 two bits H next to P + 1 is b ₇ and b ₀ , And the other b _{1 to} b ₆ are always L. Therefore, the output of the capture circuit 7 is 0 when the rising edge of CLKP does not occur between the previous rising edge of CK1RE and the rising edge of this time, the rising edge of CLKP occurs, and SYMOD is H. When P + 1, SYMOD
When L is L, it becomes P.

Next, the output of the fetch circuit 19 is input to the integrating circuit 20. The integrating circuit 20 integrates the output of the capturing circuit 19 for a certain period. The fixed period shown here is R ₁ in order to coincide with the output timing of the first difference circuit 3. Therefore, this integrating circuit 2
The transfer characteristic of is (Equation 8).

[0041]

[Equation 8]

The output of the integrating circuit 20 is the subtractor 18
And the difference from the output of the first difference circuit 3 is calculated. The output of the subtracter 18 is the difference between the slopes of the two sawtooth waves of the first and second sawtooth wave circuits 1 and 2.
That is, if the output of the subtracter 18 is differentiated, the reference signal fr
A value proportional to the frequency deviation between and is obtained.

Next, the output (Fsa) of the subtractor 18
Is input to the integrator 5 and the frequency error corrector 12.

First, the signal input to the integrator 5 will be described. Since the function of the integrator 5 integrates the frequency error component, the output of the integrator 5 outputs the phase difference component between the two sawtooth waves. The transfer function of the integrator 5 is expressed by equation (9).

[0045]

[Equation 9]

Next, the output of the integrator 5 is input to the digital filter 6. The digital filter 6 is for limiting the band of the phase difference component which is the output of the integrator 5, and its configuration is not particularly specified, but the phase jitter component and the frequency included in the synthesizer output signal (SYN) are not specified. It is necessary to select the optimum configuration from the relationship of synthesizer convergence speed. In this embodiment, a moving average that is easy to realize is adopted. The transfer function is shown in (Equation 10). The range of the moving average is the period T of the first and second sawtooth wave circuits 1 and 2.
I chose.

[0047]

[Equation 10]

Here, R ₂ is represented by (Equation 11).

[0049]

[Equation 11]

6 outputs of the digital filter (Dou
t) is added to the output of the frequency corrector 12 by the adder 17 and input to the gain setting circuit 10.

Next, the configuration of the frequency corrector 12 to which the other branched output of the subtracter 18 (Fsa) is input will be described. FIG. 5 shows the configuration and timing chart of the frequency corrector 12.

The frequency corrector 12 receives the input Fsa.
Adder 30 and register 31 for accumulating
A register 32 for taking in the Q output of 1, the above register 32
Of the Q output of the register 32, a selector 26 for selecting a multiplication coefficient with the Q output of the register 32, a selector 34 for selecting a desired coefficient by the output of the comparator 26, and the selector 3
Multiplier 33 that multiplies four outputs by the Q output of register 32, and adder 4 that integrates the output of multiplier 33
4 and register 45. Although not shown in the drawing of FIG. 1, the four operation clocks Reset, CK1, CK2, and CK3 shown in FIG. 5 are signals supplied from the timing generation circuit 21. Further, Fcont is a signal input from the outside for controlling the operation of the frequency corrector 12.

The operation of the frequency correction circuit 12 will be described below.

The input signal (Fsa) of the frequency correction circuit 12 is added by the Q output of the register 31 and the adder 30. The output of the adder 30 is again taken into the register 31 at the timing of CK1. Since the register 31 is reset by Reset, the number of times of CK1 included during the Reset clock is added. In addition, the register 31
The Q output of the register 31 is captured by the register 32 at a timing CK2 earlier than the resetting of. Therefore, the register 31 stores a numerical value proportional to the frequency error component for a certain period. The fixed period is not particularly specified, but here, a period that coincides with the cycle T of the sawtooth wave is selected, and the number of additions is R ₂ represented by the equation (11).

The Q output of the register 32 is input to the multiplier 33 and the comparator 26. The relationship between the frequency error and the value (X) of the register 32 is shown in (Equation 12).

[0056]

[Equation 12]

The comparator has a configuration in which the addition rate of the correction value is variable according to the magnitude of the frequency error. In this embodiment, an example is shown in which the frequency errors are ± 300 kHz and ± 150 kHz as threshold values. Numerical values to be compared using (Equation 12) are ± 24576 and ± 12288. The comparator 26 expresses these numerical values in a binary number and compares only the upper 8 bits.

FIG. 7 shows a truth table of the comparator 26. X <
When −24576 and X> +24576, the coefficient a is selected. -24576 <X <-12288 and 1228
When 8 <X <24576, the coefficient b is selected. 12
When 288 <X <12288, the coefficient c is selected.
The value of the selected coefficient depends on the convergence speed to be realized, and is not particularly specified.

A selection signal is output from the comparator 26, the coefficient selected by the selector 34 is selected, and the multiplier 33 is selected.
One of the inputs. The output of the multiplier 33 is input to the adder 44. The adder 44 and the register 45 constitute an integrator and store the frequency correction value. Further, the register 45 is reset by Fcont.

Output of frequency error corrector 12 (FHou
t) is added to the output of the digital filter 6 in the adder 17 and input to the gain setting circuit 10.

Next, the phase difference detecting method will be described.

FIG. 4 shows the procedure for detecting the phase difference between the output of the first sawtooth wave circuit 1 and the output of the second sawtooth wave circuit 2. In Figure 4, the clock K _YO1 showing a first peak timing of the sawtooth wave circuit 1, the second clock K _yo2 indicative of peak timings of the saw-tooth-wave circuit 2, the frequency division number given from the outside (N), serrated Number of divisions (Nx) inside the wave generation circuit 2, D
/ A converter input, phase difference detection signal (Pcont), phase difference detector output (Pout), frequency division switching signal (Nco
nt) and digital filter 6 output (Dout)
Indicates.

The clock K _yo2 indicating the peak timing of the second sawtooth wave circuit 2 is almost equal to the cycle T of the clock K _yo1 indicating the peak timing of the first sawtooth wave circuit 1, but an asynchronous signal. Is. Therefore, as shown in FIG. 4, when the frequency division number (N) given from the outside is changed from N0 to N1, the inclination of the sawtooth wave is changed in the middle of the sawtooth wave, resulting in discontinuous operation. There's a problem. Therefore, the frequency division number switching signal (Ncont) is generated at the next K _yo2 after the frequency division number is switched, and the frequency division number (Nx) inside the second sawtooth wave generation circuit 2 is updated. At the same time as this update timing, the D / A converter input is changed to an externally given initial value (Init), and the phase difference detector 11 output (Pout) is reset. K from this state
phase difference detection signal after two clocks _YO1 (Pcont)
To occur. During this period, the D / A converter input is fixed to the above-mentioned initial value (Init). This makes it possible to detect the phase difference during at least one cycle of the sawtooth wave. Since the phase difference between the two sawtooth waves is output from the digital filter 6 in synchronization with K _{yo 1} , the value is held in the phase difference detector 11 as the phase difference detection signal (Pcont). Therefore, the digital filter 6 output (Dou
If t) is P (0), P (1), P (2) ... From the point that the frequency division number N given from the outside is changed, P (2) is stored in the phase difference detector 11. To be The output of the phase difference detector 11 (Pout) is used to correct the input of the D / A converter. Since the circuit for obtaining the correction value is realized by the gain setting circuit 10, it will be described with reference to FIGS. 7 and 8.

FIG. 7 shows the configuration of the gain setting circuit 10, and FIG. 8 shows the loop gain setting sequence. The gain setting circuit 10 uses the phase difference detector 11 output (Pout), which is the output of the phase difference detector 11 described above, to set the initial value (In
It has two functions: a function of setting a corrected value of (it) and a function of changing the loop gain by a gain control signal (Gain) given from the outside.

The gain setting circuit 10 includes a gain designating circuit 35 for designating a gain designated by a gain control signal, a multiplier 38 for taking the product of the input signal of the gain setting circuit 10 and the gain designating circuit 35, and the multiplication. Adder 39 for adding the output of the adder 38 and the output of the correction value storage circuit 36, and the multiplier 38
A multiplier 37 for multiplying the output by the constant β, the multiplier 3
7 and the output of the correction value memory 36, an adder 40 for taking the addition, a multiplier 46 for taking the product of the output of the phase difference detector 11 (Pout) and the output of the gain designating circuit 35, an externally applied initial A subtracter 41 that takes the difference between a value (Init) and the output of the multiplier 46, a selector 42 that switches between the output of the subtractor 41 and the output of the adder 40, and a correction value storage circuit 36 that stores the output of the selector 42. OR4 for generating a timing for taking in the input of the correction value storage circuit 36 from the gain control signal (Gain), the phase correction control signal (Pget) and the frequency division number switching signal (Ncont).
It consists of 3.

The operation of the gain setting circuit 10 will be described below.

FIG. 8 shows a gain control signal (Gain), a phase correction control signal (Pget), a phase difference detection signal (Pcont), and a phase / gain switching signal (P) required for the gain control circuit 10.
Gcont), frequency division number switching signal (Ncont), phase difference detector 11 output (Pout), and loop gain. The gain control signal (Gain) is a signal indicating the timing for switching the loop gain. Gain control signal (Gai
n) is input to the gain designation circuit 35, and the output of the gain setting circuit 10 is updated according to a predetermined gain switching width α at the rising edge of the gain control signal. The gain switching width α is not particularly defined, but in this embodiment α
= 0.5 is shown.

First, since the gain designating circuit 10 is reset by the frequency division number switching signal (Ncont) and the output becomes 0, the output of the multiplier 38 also becomes 0. The initial value (Init) given from the outside is the phase difference detector 1 at the timing of the frequency division number switching signal (Ncont).
Since the 1 output (Pout) is 0 and the phase / gain switching signal is H, it is input to the correction value storage circuit 36 via the adder 41 and the selector 42. Where selector 4
It is assumed that the Y output of 2 has the B input selected when the S input is H and the A input selected when the S input is L. Through the above operation, the output of the gain setting circuit 10 becomes the initial value (Init) given from the outside.

The value H _os (0) of the correction value storage circuit 36 at this time
Is (Equation 13). H _os (0) = I _nit (Equation 13) Next, the phase difference detection ends and the phase difference detection signal (Pcon
t) occurs. The phase difference detection signal (Pcont) is the timing indicating the completion of the phase difference detection. Further, at the same time when this phase difference is determined, the gain designating circuit 35 is
The output of is changed to a predetermined value. Since this value depends on the convergence speed, it is not specified, but
In this embodiment, it is set to 1 for simplicity. Next, a gain designating circuit 35 is added to the output (Pout) of the phase difference detector 11.
The product of and is calculated by the multiplier 46. The subtractor 41 calculates the subtraction between the output of the multiplier 46 and the above-mentioned initial value (Init). The output of the subtractor 41 is input to the correction value storage circuit 36 via the selector 42, and the phase correction control signal (Pg) that delays the phase difference detection signal (Pcont) is given.
Et), and is held in the correction value storage circuit 36.

As a result of the above, the value H _os of the correction value storage circuit 36 is
A value obtained by subtracting the output (Pout) of the phase difference detector 11 from the initial value (Init) is held in (1), and is represented by (Equation 14).

[0071] _{H os (1) = I nit} -Pout ... ( number 14) on the other hand, the phase difference between the two saw-tooth wave of the first sawtooth wave circuit 1 and the second sawtooth circuit 2 rapidly Since the input of the next sample (DAGC) is added to the value of the correction value storage circuit 36 by the adder 39, the phase difference value is canceled out and the initial value set from the outside is input. The convergence operation is started based on (Init).

Next, the first gain switching will be described.

First, the phase / gain switching signal (PGcon
t) changes from H to L, and the A input is Y of the selector 42.
Selected for output. Phase / gain switching signal (PGcon
There is no problem with the timing at which t) is switched as long as it is after the phase correction control signal (Pget) for storing the phase difference detection result in the correction value storage circuit. Next, the output of the multiplier 38 is multiplied by the constant β to be calculated by the multiplier 37. The above constant β = 1−α. In this embodiment, since α = 0.5 will be described, β = 0.5 here. The output of the multiplier 37 is applied to the correction value storage circuit 3 in the adder 40.
6 and the output of 6 are added. When the gain control signal is input,
At the rising edge, the output of the selector 42 is taken into the correction value storage circuit 36, and the gain designation circuit 35
Output is updated α times. Updated gain designation circuit 3
The multiplication of the 5 outputs and the input of the gain designation circuit 10 is performed by the multiplier 38.
Is calculated in. The output of the multiplier 38 is the correction value storage circuit 3
It is added to the output of 6 and input to the D / A converter.

The process of the operation described above will be described using the following equation. The result of comparing the two sawtooth waves before gain switching is DAGC (0), the result of comparing the two sawtooth waves after gain switching is DAGC (1), and the initial value before gain switching is corrected. The obtained value is defined as _Hos (1), and the correction value after gain switching is defined as _Hos (2).

The output G of the multiplier 38 at this time is given by the following equation (3) when expressed by using the input DAGC (0) of the gain designating circuit 10. (Equation 3) is reprinted.

G = DAGC (1) × α (Equation 3) Further, the feedback signal D _ac (0) before gain switching is represented by (Equation 2). (Equation 2) is reprinted.

D _ac (0) = H _os (1) + DAGC (0) (Equation 2) At this time, the correction value H _os (1) is calculated by the multiplier 37 and the adder 40 (Equation 4 ), A new correction value H _os (2) is calculated.

H_os(2) = H_os(1) + (1-α) × DAGC (0) (Equation 4) Next, G after the gain switching shown in (Equation 3) and (Equation 4) are shown.
Correction value H after gain switching _os(2) is added by adder 39
And the feedback signal D after gain switching as shown in (Equation 5)_ac
It becomes (1).

[0079] _{D ac (1) = G +} H os (2) = H os (1) + DAGC (0) + α × (DAGC (0) -DAGC (1)) = D ac (0) + α × (DAGC (0) -DAGC (1)) (Equation 5) Therefore, the feedback signal after D _ac (1) maintains continuity with the value before gain change as shown in (Equation 5), and the gain at the time of feedback Can be multiplied by α.

The gain switching from the second time onward is similarly performed,
The continuity with the value before the gain change can be maintained. Therefore, as shown in FIG. 8, the gain is 1, α, α ² , α ³ , ...
Can be changed in the form.

Gain setting circuit 10 in which loop gain is set
Is converted into an analog signal by the D / A converter 9, and is input to the frequency control terminal of the VCO 8 as a VCO 8 control signal. The output of the VCO 8 is branched, one of which is output as a frequency synthesizer output (SYN), and the other of which is input to the prescaler 7. The prescaler 7 has a predetermined frequency division number (P or P) according to the modulus signal (MOD) given from the second sawtooth wave circuit 2.
Divide +1). The output of the prescaler 7 is input to the second sawtooth wave circuit 2, and this series of feedback loops makes it possible to oscillate at a predetermined oscillation frequency as a frequency synthesizer.

In the present embodiment, the case where the prescaler 7 has two frequency division numbers has been described. However, the prescaler 7 is not limited to this and can be applied even when it has a fixed frequency division number. An example at this time is shown in FIG. 9 is different from the configuration shown in FIG. 1 in that there is no control signal from the second sawtooth wave circuit 2 to the prescaler 7, and the third sawtooth wave circuit is provided from the outside, which is given a value B inversely proportional to the frequency division number. The other configuration is the same except that it is composed of 13, and the description of the operation is omitted. The prescaler is a circuit required for oscillating a signal of several 100 MHz or more, and can be omitted in the case of less than that.

Further, in the embodiment shown in FIGS. 1 and 9, the first and second difference circuits 3 and 4 for obtaining the difference and the integrator 5 for performing the integration.
Although the positional relationship between and is described in the embodiment in which the difference is calculated in the preceding stage, it can be realized by changing the positional relationship between the difference units 3 and 4 and the integrator 5 so that the calculation processing is the same. is there. FIG. 10 shows an embodiment in which the positional relationship between the differencers 3 and 4 and the integrator 5 is changed. The first and second difference circuits 3 and 4 and the integrator 5 in FIG. 1 are deleted, and a correction circuit 15 and a third difference circuit 14 are newly inserted. Correction circuit 15
Is inserted between the output of the subtracter 18 and the digital filter 6, and the third difference circuit 14 is inserted between the output of the subtractor 18 and the frequency error corrector 12. Correction circuit 15
Has a function of correcting a jump of ± M caused by the phase difference between the first sawtooth wave circuit 1 and the second sawtooth wave circuit 2. This can be easily realized by using M as a multiplier of 2 and utilizing it as an overflow.

In the configuration of the frequency synthesizer described above, an example in which each block is individually signal-processed has been shown in the present embodiment, but actually, the frequency synthesizer is configured without being limited to this. The first sawtooth wave circuit 1, the second sawtooth wave circuit 2, the first difference circuit 3, the second difference circuit 4, the integrator 5, the digital filter 6, and the gain setting circuit. 1
0, the phase difference detector 11, the frequency corrector 12, the third sawtooth wave generation circuit 13, the third difference circuit 1
4, a part or all of the compensator 15, the acquisition circuit 19, the integration circuit 20, and the control signal generator 47 are shared by an arithmetic unit such as a DSP (digital signal processor) for signal processing. The method of performing is also applicable.

Next, FIGS. 11 and 12 show two examples of the initial value setting type frequency synthesizer capable of setting the initial value.

FIG. 11 has a circuit for storing the converged value of the previous frequency synthesizer. When the oscillation frequency of the next frequency synthesizer is set, the stored converged value of the frequency synthesizer is set as an initial value. The structure of an initial value setting type frequency synthesizer is shown. First above
The initial value setting type frequency synthesizer of FIG. 1 stores the frequency synthesizer 50 configured as shown in FIG. 1 or 9 and the convergence result DAC of the frequency synthesizer 50 with the frequency division number N as an address and corresponds to the frequency division number N. The storage circuit 48 outputs the oscillation frequency of the next frequency synthesizer 50 as an initial value.

The contents stored in the memory circuit 48 are reset as an initial state, or a numerical value that has nothing to do with the oscillation frequency of the frequency synthesizer is held.
When the power is turned on or when a long time has passed, all the frequency division numbers N are automatically set, and each frequency division number N is set.
The operation of writing the convergence result DAC of the frequency synthesizer 50 for Regarding the relationship between the VCO frequency control signal and the oscillation frequency, there are slow fluctuations such as temperature fluctuations. However, since the above fluctuations are fairly slow in units of several hours, once the contents of the memory circuit 48 are determined. The stored numerical value can be used as an initial value to be set in the next frequency synthesizer 50. The initial value is input to the Init terminal of the frequency synthesizer 50.

FIG. 12 shows an embodiment in which a device for calculating the relationship between the VCO frequency control signal and the oscillation frequency as a function is used. The second initial value setting type frequency synthesizer stores a frequency synthesizer 50 having the configuration of FIG. 1 or 9 and a signal DAC that indicates the convergence result of the frequency synthesizer 50 with the frequency division number N as an address. Circuit 48, frequency division number N, and storage circuit 4
It is composed of a computing device 49 for computing the initial value of the oscillation frequency of the next frequency synthesizer based on the eight outputs.

When the linearity of the oscillation frequency with respect to the VCO frequency control signal is good, the function of the oscillation frequency with respect to the VCO frequency control signal can be approximated by at least a linear function. Therefore, the storage circuit 4
Two parameters (slope and offset value) of the function of the oscillation frequency with respect to the frequency control signal of the VCO can be calculated from the converged value of the frequency synthesizer 50 for at least two kinds of frequency division numbers of 8. The output of the arithmetic unit that has performed the above calculation is set to the input terminal Init as the initial value of the oscillation frequency of the next frequency synthesizer 50.

Here, the approximate function of the oscillation frequency with respect to the frequency control signal of the VCO is not limited to the first order, and is higher than the second order in accordance with the linearity of the oscillation frequency with respect to the frequency control signal of the VCO. It can also be realized by using an approximation or a calculation method using the correlation value of the oscillation frequency with respect to the frequency division number N.

Finally, FIG. 13 shows an example of the configuration of a transmission device using the above frequency synthesizer.

The present transmission apparatus uses the reference signal fr, the frequency division number N,
Fcont, Gain, and Init are input, and a frequency synthesizer 50 that oscillates at a specified frequency, a memory circuit 48 that stores an initial value, a demodulated wave that demodulates a received signal by a received modulated wave and a signal supplied from the frequency synthesizer are received. And a modulator 52 that outputs a transmission modulation wave by using a signal supplied from the frequency synthesizer for the transmission signal.

The frequency synthesizer 50 oscillates an oscillation frequency of fr × N from the reference signal fr and the frequency division number N.
Therefore, in the demodulator 51 and the modulator 52, the above f
Modulation and demodulation are performed based on the oscillation frequency of r × N. The transmission device and the reception signal can be exchanged by using the same configuration in the opposite transmission device.

In this embodiment, the frequency synthesizer 50 described above is used.
However, the oscillation frequency of the frequency synthesizer 50 is not limited to the modulator 52 and the demodulator 51.
, And the modulator 52 and the demodulator 51 in a time division manner.
It can also be applied to an example in which the oscillation frequency of the signal supplied to is changed. Further, the control signals of Fcont and Gain are not necessarily required at the same time, and are supplied when the functions corresponding to them are used.

[0095]

According to the present invention, the initial value of the frequency synthesizer can be given from the outside, and the switching time can be shortened when the oscillation frequency is switched periodically. Further, since the frequency deviation can be directly used as the feedback signal, for example, the switching convergence time of 1 mse, which has been difficult in the past, can be obtained.
It can be c or less.

Since the loop gain can be arbitrarily set, it is possible to set the convergence speed during the convergence of the frequency synthesizer at the time of switching the frequency to a large value, reduce the loop gain after the convergence, and increase the stability. It is also possible to achieve higher frequency setting accuracy of the frequency synthesizer.

[Brief description of drawings]

FIG. 1 shows the configuration of a frequency synthesizer.

FIG. 2 is a configuration of a capture circuit.

FIG. 3 is a timing chart of a capture circuit.

FIG. 4 is a phase difference detection procedure.

FIG. 5 is a configuration and operation time chart of the frequency error detector.

FIG. 6 is a truth table of a comparator.

FIG. 7 is a configuration of a gain setting circuit.

FIG. 8 is an operation time chart of the gain setting circuit.

FIG. 9 shows a second embodiment of the frequency synthesizer.

FIG. 10 shows a third embodiment of the frequency synthesizer.

FIG. 11 shows an example of a first initial value setting type frequency synthesizer.

FIG. 12 shows an example of a second initial value setting type frequency synthesizer.

FIG. 13 is a configuration of a transmission device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st sawtooth wave circuit, 2 ... 2nd sawtooth wave circuit, 3
... first difference circuit, 4 ... second difference circuit, 5 ... integrator,
6 ... Digital filter, 7 ... Prescaler, 8 ... Voltage controlled oscillator (VCO), 9 ... D / A converter, 10 ... Gain setting circuit, 11 ... Phase difference detector, 12 ... Frequency corrector,
13 ... Third sawtooth wave generating circuit, 14 ... Third difference circuit, 15 ... Corrector, 17 ... Adder, 18 ... Subtractor, 19
... Capture circuit, 20 ... Integration circuit, 21 ... Timing generation circuit, 22 ... Flip-flop, 23 ... Register, 2
4 ... AND, 25 ... Delay circuit, 26 ... Comparator, 27 ... A
ND, 28 ... Register, 29 ... Register, 30 ... Adder, 31 ... Register, 32 ... Register, 34 ... Selector, 33 ... Multiplier, 35 ... Gain designating circuit, 36 ... Correction value storage circuit, 37 ... Multiplier, 38 ... Multiplier, 39 ... Adder, 40 ... Adder, 41 ... Subtractor, 42 ... Selector, 4
3 ... OR, 44 ... Adder, 45 ... Register, 46 ... Multiplier, 47 ... Control signal generator, 48 ... Storage circuit, 49 ... Arithmetic unit, 50 ... Frequency synthesizer, 51 ... Demodulator,
52 ... Modulator.

Claims (13)

[Claims] 1. A first sawtooth wave circuit for generating a sawtooth wave based on a reference signal fr supplied from a reference oscillator, a predetermined frequency division number N, and an output of a voltage controlled oscillator (VCO). The VCO oscillation frequency control is performed from the difference between the second sawtooth wave circuit that generates the sawtooth wave, the output of the first sawtooth wave circuit, and the output of the second sawtooth wave circuit, and the reference signal is generated. In a frequency synthesizer that oscillates at an oscillation frequency that is proportional to the product of fr and the frequency division number N, the first signal based on the control signal generator detecting the change in the frequency division number N and the output of the control signal generator. Frequency synthesizer for detecting a phase difference between the sawtooth wave circuit output of the above and the second sawtooth wave circuit output, and correcting a preset initial value by the above phase difference. . 2. A first sawtooth wave circuit for generating a sawtooth wave based on a reference signal fr supplied from a reference oscillator, a preset frequency division number N, and an output of a voltage controlled oscillator (VCO). The VCO oscillation frequency control is performed from the difference between the second sawtooth wave circuit that generates the sawtooth wave, the output of the first sawtooth wave circuit, and the output of the second sawtooth wave circuit, and the reference signal is generated. In a frequency synthesizer that oscillates at an oscillation frequency proportional to the product of fr and the frequency division number N, a gain setting circuit that changes the loop gain of the series of feedback loops in response to a gain switching signal is provided. Frequency synthesizer. 3. A first sawtooth wave circuit for generating a sawtooth wave based on a reference signal fr supplied from a reference oscillator, a preset frequency division number N, and an output of a voltage controlled oscillator (VCO). The VCO oscillation frequency control is performed from the difference between the second sawtooth wave circuit that generates the sawtooth wave, the output of the first sawtooth wave circuit, and the output of the second sawtooth wave circuit, and the reference signal is generated. In a frequency synthesizer that oscillates at an oscillation frequency proportional to the product of fr and the frequency division number N, the difference between the output of the first sawtooth wave circuit and the output of the second sawtooth wave circuit in a certain period Amount (differential value)
A frequency synthesizer having a frequency error corrector for correcting a signal for controlling the oscillation frequency of the VCO based on the above. 4. The frequency synthesizer according to claim 1, wherein a method for calculating a difference between the output of the first sawtooth wave circuit and the output of the second sawtooth wave circuit is the method described above. A first difference between the outputs of the first sawtooth wave circuit
Difference circuit and a second difference circuit for taking the difference between the outputs of the second sawtooth wave circuit and a capture circuit for converting the output of the second difference circuit into a signal synchronized with the reference signal fr and the capture circuit output. A frequency synthesizer characterized by comprising an integrating circuit for integrating a predetermined period and a subtracter for subtracting the output of the first differential circuit and the output of the second differential circuit. 5. The frequency synthesizer according to any one of claims 1 to 4, wherein a frequency division number N designated in advance is used.
And a second sawtooth wave circuit for generating a sawtooth wave based on the output of a voltage controlled oscillator (VCO) controls a prescaler having one or a plurality of division ratios P and a division ratio P of the prescaler. A frequency synthesizer characterized in that the increasing rate of the output of the second sawtooth wave circuit is controlled on the basis of the control signal. 6. The frequency synthesizer according to any one of claims 1 to 4, wherein the second sawtooth wave circuit is represented by the following formula with a prescaler having a fixed frequency division number P. Numerical value BB = (M × P) ÷ (N × fr × T) inversely proportional to the frequency dividing number N (where M is the peak value of the second sawtooth wave circuit, T
Represents a period) and a frequency synthesizer characterized by having a configuration having an increasing rate. 7. The frequency synthesizer according to claim 1, 4, 5 or 6, wherein a method for detecting a phase difference is such that at least one cycle of the output of the first sawtooth wave circuit is the VCO. The control signal is fixed to the initial value, and the phase difference between the sawtooth wave of the first sawtooth wave circuit output and the sawtooth wave of the second sawtooth wave circuit output obtained during the period is detected. Then, a correction value storage circuit that holds a value corresponding to the phase difference from the initial value, and the first value after the end of the period for fixing the VCO control signal to the initial value
Of the sawtooth wave circuit output and the sawtooth wave of the second sawtooth wave circuit output are added to the difference, and the adder output is used as the VCO control signal. And a frequency synthesizer. 8. The frequency synthesizer according to claim 2, 4, 5, or 6, wherein a method for changing the loop gain is a gain designator for designating the loop gain.
A multiplier that multiplies the difference between the output of the gain designator, the output of the first sawtooth wave circuit, and the output of the second sawtooth wave circuit, and a loop gain that changes corresponding to the gain switching signal Gain. Where the change width of is a, a multiplier that multiplies the multiplier output by a constant (1-α), an adder that adds the multiplier output and the correction value storage circuit output, and the addition A frequency synthesizer characterized by comprising a correction value storage circuit for storing the output of the instrument. 9. The frequency synthesizer according to any one of claims 3 to 6, wherein the frequency corrector is configured to obtain a difference between the output of the first sawtooth wave circuit and the output of the second sawtooth wave circuit. When correcting the signal for controlling the oscillation frequency of the VCO based on the variation (differential value) in a certain period,
According to the amount of change (differential value) of the difference between the output of the first sawtooth wave circuit and the output of the second sawtooth wave circuit in a certain period, multiplication is performed by a comparator in which the weighting of the correction ratio is variable. Frequency synthesizer characterized by being composed of a container. 10. The frequency synthesizer according to claim 1, wherein the first sawtooth wave circuit, the second sawtooth wave circuit, and the first sawtooth wave circuit that constitute the frequency synthesizer. The difference circuit, the second difference circuit, the gain setting circuit, the phase difference detector, the frequency corrector, the acquisition circuit, the integrating circuit, and part or all of the control signal generator are DSP (digital). A frequency synthesizer characterized by being realized by a method of performing signal processing by sharing an arithmetic unit such as an adder or a multiplier such as a signal processing device). 11. The frequency synthesizer according to claim 1, wherein an input value of a D / A converter that generates a frequency control signal of the VCO is set to an oscillation frequency or a frequency division number N of the frequency synthesizer. A frequency synthesizer having a memory circuit for storing correspondingly, wherein when the frequency synthesizer sets the same oscillation frequency next time, a corresponding value is output from the memory circuit and used as an initial value of the frequency synthesizer. 12. The frequency synthesizer according to any one of claims 1 to 10, wherein an arithmetic unit for calculating the relational expression between the value of the frequency control signal of the VCO and the oscillation frequency, and the frequency control signal of the VCO are provided. A memory circuit that stores the generated D / A converter input in correspondence with the oscillation frequency of the frequency synthesizer, a correction circuit that corrects the coefficient of the above relational expression based on the value of the memory circuit, and a frequency synthesizer next time. A frequency synthesizer characterized by outputting a corresponding value from the above-mentioned arithmetic unit when setting the oscillation frequency of, and using it as an initial value of the frequency synthesizer. 13. A transmission device having a demodulator and a modulator, characterized in that an oscillation frequency for transmission or reception is supplied from the frequency synthesizer according to any one of claims 1 to 12. .