JP2010141519A - Phase-locked loop and communication device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase-locked loop capable of switching the processing clock frequency of processing signals, on the basis of a set operation mode and reducing power consumption, and a communication device. <P>SOLUTION: The phase-locked loop includes: an oscillation circuit for outputting the oscillation signals of an oscillation frequency, based on the oscillation control signals indicated by a digital value; a first bit shift part for inputting a frequency dividing ratio for which a carrier frequency is divided by a reference frequency and control signals, stipulating the operation mode and dividing the frequency dividing ratio by an integer value set on the basis of the control signals; a first frequency dividing part for inputting signals, based on the oscillation signals and the control signals and frequency-dividing the signals, based on the oscillation signals by the integer value which is set, on the basis of the control signals; a phase comparison part for comparing a first accumulated value, a second accumulated value and the fraction of a cumulative phase in each cycle of reference frequency signals and outputting phase comparison signals; and a data conversion part for converging the phase comparison signals to an optional convergence value, based on the control signals and outputting the oscillation control signals. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a phase synchronization circuit and a communication device.

  For example, in a communication device such as a mobile phone that can communicate with an external device wirelessly, a phase locked loop (PLL (Phase Locked Loop) circuit) is used to fix the carrier frequency of the carrier wave related to communication with the external device to an accurate frequency. Is used. In recent years, with the miniaturization of semiconductor processes, a voltage controlled oscillation circuit (Voltage Controlled Oscillator: VCO) controlled by an analog voltage is replaced with a digital controlled oscillation circuit (Digital Controlled Oscillator: DCO) controlled by a digital signal. Synchronous circuits are attracting attention.

  Under such circumstances, a technique for applying a digitally controlled oscillation circuit to a phase synchronization circuit has been developed. As a technique for applying a digitally controlled oscillation circuit to the phase synchronization circuit, for example, Non-Patent Document 1 can be cited.

R.B.Staszewski et al., “All-Digital Phase-Domain TX Frequency Synthesizer for Bluetooth Radios in 0.13um CMOS, ISSCC2004 Digest.

FIG. 1 is an explanatory diagram illustrating a configuration of a phase synchronization circuit according to a conventional technique in which a digitally controlled oscillation circuit is applied to a phase synchronization circuit. Here, FIG. 1 shows an ADPLL (All-Digital Phase Locked Loop) circuit (phase synchronization circuit) using a digitally controlled oscillation circuit (hereinafter, sometimes referred to as “DCO”) controlled by a digital signal. Show. The conventional phase-locked loop shown in FIG. 1 includes a time-to-digital converter (Time-to-Digital Converter; hereinafter sometimes referred to as “TDC”) 12, an accumulator 14, a flip-flop 16, and the like. Here, the TDC 12 detects the number of clocks of the oscillation signal output from the DCO 10 and the oscillation signal within the reference signal f _REF cycle. Therefore, TDC12, using an accumulator 14 and a flip-flop 16, to enable the phase fraction display relative to the oscillation signal in the reference signal f _REF. The conventional PLL circuit digitally controls the DCO 10 by detecting the difference between the reference phase and the above phase with a phase comparator and feeding back an integrated value of a digital value (digital signal) corresponding to the phase error. Yes.

  Here, in a communication device such as a mobile phone to which a phase synchronization circuit including a DCO (hereinafter sometimes referred to as “PLL circuit”) is applied, the PLL circuit is required to support a plurality of operation modes. May be. Examples of the request for the PLL circuit include sharing the PLL circuit for generation of the carrier frequency and generation of the clock frequency of the digital circuit included in the communication apparatus, and handling of a plurality of carrier frequencies. When the PLL circuit is used both for generation of a carrier frequency and generation of a clock frequency of a digital circuit included in the communication device, the PLL circuit needs to be operated even during a period in which the communication device does not transmit a carrier wave. Here, when the frequency of the signal processed internally by the PLL circuit is fixed, when the phase noise characteristic of the carrier wave transmission is not required for the clock of the digital circuit, the PLL circuit exceeds the required processing capability. It will be forced to operate in the over-spec state. Therefore, in the above case, the PLL circuit consumes more power than is necessary for the operation, which may lead to an increase in power consumption of the PLL circuit and thus an increase in power consumption of the communication device. Also, in the case of dealing with the generation of a plurality of carrier frequencies, the power consumption is increased as described above.

  However, a PLL circuit (hereinafter referred to as “conventional PLL circuit”) according to a conventional technique (hereinafter simply referred to as “conventional technique”) in which a digitally controlled oscillation circuit is applied to a phase-locked circuit may be described. ) Is not considered at all about the correspondence to a plurality of operation modes. More specifically, even when the operation mode is switched, the conventional PLL circuit cannot switch the processing clock frequency of the processing signal processed inside based on the operation mode. Therefore, the conventional PLL circuit may cause an increase in power consumption when processing in an operation mode other than a certain target operation mode is performed in advance. Therefore, even if the conventional technique is used, reduction of power consumption in the phase locked loop (PLL circuit) cannot be desired.

  The present invention has been made in view of the above problems, and an object of the present invention is to switch a processing clock frequency of a processing signal to be internally processed based on a set operation mode based on the operation mode. Another object of the present invention is to provide a new and improved phase synchronization circuit and communication device capable of reducing power consumption.

  In order to achieve the above object, according to a first aspect of the present invention, an oscillation circuit that receives an oscillation control signal represented by a digital value and outputs an oscillation signal having an oscillation frequency based on the oscillation control signal; A division ratio obtained by dividing a carrier frequency of a carrier wave related to communication with an external device by a reference frequency of a reference frequency signal and a control signal defining an operation mode are input, and the division ratio is calculated based on the control signal. A first bit shift unit that divides by a set integer value, a signal based on the oscillation signal, and the control signal are input, and the signal based on the oscillation signal is divided by the integer value set based on the control signal. A first frequency division unit that circulates, a first cumulative addition value obtained by cumulatively adding an output value output from the first bit shift unit in each cycle of the reference frequency signal, and an output from the first frequency division unit Minutes A second cumulative addition value obtained by cumulatively adding the number of clocks of the signal based on the generated oscillation signal, and a clock of the signal based on the clock of the reference frequency signal and the frequency-divided oscillation signal output from the first frequency divider. And a phase comparison unit that outputs a phase comparison signal that represents a comparison result, and a phase comparison signal that is used as the control signal. A phase synchronization circuit is provided that includes a data conversion unit that converges to an arbitrary convergence value based on the data and outputs an oscillation control signal based on the convergence value.

  With this configuration, the processing clock frequency of the processing signal processed internally based on the set operation mode can be switched based on the operation mode to reduce power consumption.

  Further, an offset value for correcting an error with respect to an ideal value of the conversion gain of the oscillation circuit is derived based on the phase comparison signal, and an output value output from the first bit shift unit based on the control signal May further be provided with an offset compensator that selectively compensates for the offset with the offset value.

  An accumulated clock deriving unit that outputs the second accumulated addition value and the difference value based on the signal based on the divided oscillation signal output from the first dividing unit and the reference frequency signal, respectively. The accumulated clock deriving unit may include a time-digital conversion circuit that selectively outputs the difference value based on the control signal.

  The first bit shift unit is supplied with a frequency division ratio to which the frequency modulation component is added, and a second bit shift unit that divides the frequency modulation component by an integer value set based on the control signal. Further, the data conversion unit may output the oscillation control signal based on an addition value of the convergence value and the divided frequency modulation component output from the second bit shift unit.

  In order to achieve the above object, according to a second aspect of the present invention, a reception signal having a predetermined carrier frequency transmitted from one or more external devices is received, and the received signal is transmitted to one or more external devices. The transmission that includes a communication antenna that transmits a transmission signal of a predetermined carrier frequency, a phase synchronization circuit, a reception unit that processes the reception signal received by the communication antenna, and a phase synchronization circuit that transmits to the external device A transmission unit that processes a signal and transmits the signal to the communication antenna. Each of the phase synchronization circuits included in the reception unit and the transmission unit receives an oscillation control signal represented by a digital value, and the oscillation control An oscillation circuit that outputs an oscillation signal having an oscillation frequency based on the signal, a frequency division ratio obtained by dividing the predetermined carrier frequency by the reference frequency of the reference frequency signal, and a control signal that defines an operation mode. And a bit shift unit that divides the division ratio by an integer value set based on the control signal, a signal based on the oscillation signal, and the control signal are input, and based on the control signal A first frequency dividing unit that divides the oscillation signal by a set integer value; and a first cumulative addition value obtained by cumulatively adding an output value output from the bit shift unit in each cycle of the reference frequency signal; A second cumulative addition value obtained by cumulatively adding the number of clocks of the signal based on the divided oscillation signal output from the first frequency divider, and the clock of the reference frequency signal and the output from the first frequency divider Compares the fractional part of the accumulated phase represented by the digital value detected from the time difference between each edge in the clock of the signal based on the divided oscillation signal and outputs the phase comparison signal representing the comparison result A comparing unit, the phase comparison signal is converged to any convergence value based on the control signal, the communication device and a data converting unit that outputs an oscillation control signal based on the convergence value is provided.

  With this configuration, communication that can communicate with an external device while switching the processing clock frequency of a processing signal processed internally based on the set operation mode based on the operation mode and reducing power consumption. A device is realized.

  According to the present invention, the processing clock frequency of a processing signal processed internally based on the set operation mode can be switched based on the operation mode to reduce power consumption.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the present specification and drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

In the following, description will be given in the following order.
1. 1. An example of a basic configuration of a phase locked loop according to an embodiment of the present invention 2. a phase locked loop circuit according to the first embodiment of the present invention; 3. Phase synchronization circuit according to second embodiment of the present invention 4. Phase synchronization circuit according to third embodiment of the present invention 5. Phase synchronization circuit according to the fourth embodiment of the present invention Communication apparatus according to an embodiment of the present invention

(An example of a basic configuration of the phase synchronization circuit according to the embodiment of the present invention)
Before describing the phase synchronization circuit according to the first to fourth embodiments of the present invention, an example of a basic configuration of the phase synchronization circuit according to the embodiment of the present invention will be described. Hereinafter, the phase synchronization circuit may be described as a “PLL circuit”. FIG. 2 is an explanatory diagram showing an example of a basic configuration of the PLL circuit 190 (phase synchronization circuit) according to the embodiment of the present invention.

  The PLL circuit 190 includes a reference frequency oscillation unit 102, an accumulator 104, an accumulated clock deriving unit 106, an oscillation circuit 108, a phase comparison unit 110, a data conversion unit 112 ', and a frequency dividing circuit 114.

The reference frequency oscillating unit 102 generates and outputs a reference frequency signal having a frequency of f _REF . Hereinafter, the frequency f _REF of the reference frequency signal is expressed as a reference frequency f _REF . 2 shows a configuration in which the PLL circuit 190 includes the reference frequency oscillation unit 102, the basic configuration of the phase locked loop circuit according to the embodiment of the present invention is not limited to the above. For example, the phase synchronization circuit according to the embodiment of the present invention does not include the reference frequency oscillating unit 102 and is configured so that an externally generated reference frequency signal is input to the phase synchronization circuit according to the embodiment of the present invention. Also good.

  A frequency division ratio is input to the accumulator 104, and the frequency division ratio in each cycle of the reference frequency signal is cumulatively added using the reference frequency signal as a trigger. Then, the accumulator 104 outputs the cumulatively divided frequency division ratio to the phase comparison unit 110.

Here, the frequency division ratio input to the PLL circuit 190 is, for example, a value (f _RF / f _REF ) obtained by dividing the carrier frequency f _RF of the carrier wave related to communication with the external device by the reference frequency f _REF . In the example of FIG. 2, the carrier frequency f _RF is obtained by dividing the oscillation signal output from the oscillation circuit 108 by N frequency division (N is a positive integer) by the frequency division circuit 114 (N is a positive integer). This corresponds to the oscillation frequency of the signal based on the oscillation signal. Here, the frequency division ratio N at which the frequency dividing circuit 114 performs frequency division may be fixed, for example, or may be changed according to a change in the carrier frequency (for example, a communication device including the PLL circuit 190). The frequency division ratio is switched in accordance with the frequency division control signal transmitted from the control section.) Note that when the carrier frequency f _RF is equal to the oscillation frequency of the oscillation signal, the PLL 190 may not include the frequency dividing circuit 114. In the above case, the frequency division ratio according to the embodiment of the present invention is a value (f _OSC / f _REF ) obtained by dividing the oscillation frequency f _OSC of the oscillation signal transmitted from the oscillation circuit 108 by the reference frequency f _REF. (That is, “oscillation frequency f _OSC = carrier frequency f _RF ”). In addition, the frequency division ratio according to the embodiment of the present invention is generated, for example, in a control unit (for example, configured by an MPU or the like) of a communication device (described later) provided with the PLL circuit 190, and the PLL circuit. Although it is input to 190, it is not limited to the above. For example, the frequency division ratio according to the embodiment of the present invention is recorded in advance on a recording medium such as a ROM (Read Only Memory) included in the communication device, and the control unit appropriately reads out from the recording medium and inputs the PLL circuit 190. You can also Hereinafter, the cumulatively divided frequency division ratio is described as “first cumulative addition value”.

  The accumulated clock deriving unit 106 is an oscillation signal clock obtained by dividing the time difference between the edges of the oscillation signal obtained by dividing the reference frequency and the oscillation frequency by N in the integer part and the time difference between the edges of the oscillation signal divided by N in each period of the reference frequency signal. Using the value obtained by dividing by the period as the decimal part, the cumulative addition value displayed in decimal is output.

And the second cumulative sum, min (in FIG. 2, the signal frequency is the carrier frequency f _RF)-divided oscillating signal a digital value number of clocks is cumulative addition of. That is, the second cumulative addition value is an integer of cumulative phases obtained by adding a phase based on the frequency of the _divided oscillation signal (corresponding to the carrier frequency f _RF in FIG. 2) for each reference frequency f _REF. Corresponds to the ingredients. In the phase synchronization circuit according to the embodiment of the present invention, when the output of the oscillation circuit 108 is input to the accumulated clock deriving unit 106 without being divided by N, the second accumulated addition value is the clock of the oscillation signal. It becomes a digital value in which numbers are cumulatively added.

  In addition, the time difference between the edges of the oscillation signal obtained by dividing the reference frequency and the oscillation frequency by N is detected, and further, the value divided by the oscillation signal period divided by N is calculated, so that the oscillation signal clock divided by N is calculated. The fractional part of the phase with reference to can be detected. That is, a fractional display of the accumulated phase for each cycle of the reference frequency is possible from the time difference between the edges of the oscillation signal obtained by dividing the second accumulated addition value, the reference frequency, and the oscillation frequency by N. In the phase synchronization circuit according to the embodiment of the present invention, when the output of the oscillation circuit 108 is input to the cumulative clock deriving unit 106 without being divided by N, the fractional part of the phase based on the oscillation frequency clock is used. Is detected. In the following, as illustrated in FIG. 2, an example in which the oscillation signal output from the oscillation circuit 108 is divided by N in the frequency dividing circuit 114 will be described.

[Configuration Example of Cumulative Clock Deriving Unit 106]
The cumulative clock deriving unit 106 includes an accumulator 150, flip-flops 152 and 154 (abbreviated as “FF” in each figure), and a TDC 156 (time-digital conversion circuit).

Accumulator 150 cumulatively adds “1” for each clock of the divided oscillation signal based on the divided oscillation signal (corresponding to a signal whose frequency is carrier frequency f _RF in FIG. 2). The addition result is transmitted to the flip-flop 154. That is, accumulator 150 cumulatively adds the number of clocks of the divided oscillation signal and transmits the cumulatively added number of clocks to flip-flop 154.
Yeah.

The flip-flop 152 has the reference frequency f _REF for each clock of the divided oscillation signal based on the divided oscillation signal (corresponding to a signal whose frequency is the carrier frequency f _RF in FIG. 2). Retime the reference frequency signal.

  The flip-flop 154 holds the output of the accumulator 150 using the reference frequency signal retimed by the flip-flop 152 as a trigger. Here, the output of the flip-flop 154 corresponds to the second cumulative addition value.

  The TDC 156 digitally converts the relative time difference between the edges of the clock of the reference frequency signal and the clock of the divided oscillation signal. Further, the TDC 156 outputs a value obtained by dividing the relative time difference by the period of the reference frequency signal. Here, the number of clocks accumulated and accumulated by the accumulator 150 is an integer part of the accumulated phase with reference to the divided oscillation signal period, whereas the output of the TDC 156 is a fractional part of the accumulated phase. The TDC 156 can be configured with, for example, an inverter circuit and a flip-flop, but is not limited thereto. A configuration example of the TDC according to the embodiment of the present invention will be described later with reference to FIGS. 6A and 6B.

  The accumulated clock deriving unit 106, for example, with the configuration shown in FIG. 2, based on the reference frequency signal and the divided oscillation signal, an integer part of the accumulated phase and a fractional part of the accumulated phase, which are the second accumulated addition values, Can be derived. Note that the configuration of the cumulative clock derivation unit according to the embodiment of the present invention for deriving the integral part of the cumulative phase and the fractional part of the cumulative phase, which are the second cumulative addition values, is not limited to the configuration shown in FIG. Needless to say.

  The oscillation circuit 108 is controlled by an oscillation control signal represented by an input digital value. More specifically, the oscillation circuit 108 outputs an oscillation signal having an oscillation frequency based on the input oscillation control signal. That is, the oscillation circuit 108 corresponds to a digitally controlled oscillation circuit (DCO).

  The phase comparison unit 110 calculates the integer part of the cumulative phase that is the second cumulative addition value output from the cumulative clock derivation unit 106 from the first cumulative addition value (cumulatively added division ratio) output from the accumulator 104, and The decimal part of the accumulated phase is subtracted and a phase comparison signal corresponding to the difference is output. Here, the phase comparison unit 110 can be configured by an adder or the like, but is not limited thereto.

  The data converter 112 ′ converges the input phase comparison signal to a value corresponding to the division ratio, and outputs an oscillation control signal based on the division ratio.

[Configuration Example and Operation of Data Conversion Unit 112 ′]
The data converter 112 ′ includes a variable gain amplifier circuit 160, an adder 162, a variable gain amplifier circuit 164, an adder 166, a multiplier 168, a bit shift circuit 170 ′, and a bit shift circuit 172 ′. Prepare. When the PLL circuit according to the embodiment of the present invention does not include the frequency dividing circuit 114 that divides the oscillation signal, the bit shift circuit 170 ′ and the bit shift circuit 172 ′ may not be provided. .

The data converter 112 ′ serves to switch the loop gain of the PLL circuit 190 by changing the multiplier m of the gain 1/2 ^m of each of the variable gain amplifier circuits 160 and 164 based on the gain control signal G_SW. Here, the gain control signal G_SW is, for example, a signal based on a comparison result between the signal at the point P shown in FIG. 2 (the output of the adder 166) and the frequency division ratio. By switching the gain of each of the variable gain amplifier circuits 160 and 164 based on the gain control signal G_SW, the data conversion unit 112 ′ can divide the output of the adder 166 (ie, the signal at the point P shown in FIG. 2) by the frequency division ratio. Can be operated so as to converge to a value equivalent to that of f _RF / f _REF (to be described later with reference to Equations 1 and 2). The gain control signal G_SW is generated by, for example, the control unit of the communication apparatus including the PLL circuit 190 based on the signal at the point P shown in FIG. 2, but is not limited thereto. For example, the PLL circuit according to the embodiment of the present invention further includes a detection unit (not shown) that generates the gain control signal G_SW by comparing the signal at the point P (the output of the adder 166) with the frequency division ratio. You can also.

Here, the operation in the data converter 112 ′ will be described. The phase comparison signal output from the phase comparator 110 is amplified 1/2 ^m times by the variable gain amplifier circuit 160. In the adder 162, a value obtained by dividing the output of the variable gain amplifier circuit 160 and f _OSC / f _REF in the bit shift circuit 170 ′ by a value (N) corresponding to the frequency dividing ratio in the frequency dividing circuit 114 ({f _OSC / f _REF } / N). Here, the bit shift circuit 170 ′ is configured by a divider, for example, and divides f _OSC / f _REF by a value (N) corresponding to the frequency division ratio in the frequency divider circuit 114. The variable gain amplifier circuit 164 amplifies the input set value A by 1/2 ^m times, and the adder 166 subtracts the output of the variable gain amplifier circuit 164 from the output of the adder 162. The multiplier 168 divides the output of the adder 166 and the value (f _REF / k _DCO ) obtained by dividing the reference frequency f _REF by the conversion gain k _DCO of the oscillation circuit 108 in the frequency dividing circuit 114 in the bit shift circuit 172 ′. A value amplified by a value (N) times corresponding to the ratio is multiplied, and the multiplication result is output as an oscillation control signal.

The operations in the data conversion unit 112 ′ are summarized as follows. An oscillation control signal for causing the oscillation circuit 108 to oscillate is expressed by Equation 1, for example. Here, f _OSC shown in Equation 1 represents the oscillation frequency of the oscillation signal output from the oscillation circuit 108. Further, k _DCO shown in Equation 1 represents the conversion gain of the oscillation circuit 108.

・・・（数式１）

... (Formula 1)

In the multiplier 168 of the data conversion unit 112 ′, N {f _REF / k _DCO } is multiplied. Therefore, the input of the multiplier 168 is expressed by Equation 2 below from Equation 1.

・・・（数式２）

... (Formula 2)

  As shown in Equation 2, the data conversion unit 112 ′ can converge the input of the multiplier 168, that is, the output of the adder 166 to the frequency division ratio.

  Further, the variable range of the phase comparison unit 110 is assumed to be, for example, unsigned 10 bits (unsigned 10 bits), and the set value A input to the data conversion unit 112 ′ becomes the midpoint of the variable range of the phase comparison unit 110. When “512” is set, the PLL circuit 190 can converge the output of the phase comparison unit 110 to “512”. That is, when the set value A is input to the data conversion unit 112 ′, the PLL circuit 190 can converge the output of the phase comparison unit 110 to a predetermined value corresponding to the set value A.

Therefore, the PLL circuit 190 can realize a data conversion method that allows the loop to converge stably by including the data conversion unit 112 ′. The set value A, f _OSC / f _REF and f _REF / k _{DCO input} to the data conversion unit 112 ′ are generated by, for example, a control unit of a communication apparatus including the PLL circuit 190 and the data conversion unit 112 ′. Is not limited to the above.

  For example, with the configuration shown in FIG. 2, the PLL circuit 190 controls the oscillation circuit with an oscillation control signal represented by a digital value, so that the loop is converged stably. Therefore, the PLL circuit 190 functions as a phase synchronization circuit including a digitally controlled oscillation circuit.

Here, in the PLL circuit 190, for example, each component such as the signal f _{RF obtained} by dividing the oscillation signal in the frequency dividing circuit 114, the input frequency dividing ratio, the signal processed by the cumulative clock deriving unit 106, the phase comparison signal, and the like. A signal processed in the element corresponds to a processing signal processed internally. For example, when the phase synchronization circuit according to the embodiment of the present invention is configured not to include the frequency divider circuit 114, the oscillation signal output from the oscillation circuit 108 may be regarded as a processing signal.

  Hereinafter, the phase synchronization circuit (PLL circuit) according to the first to fourth embodiments of the present invention will be described with the PLL circuit 190 shown in FIG. 2 as a basic configuration of the phase synchronization circuit according to the embodiment of the present invention. . Needless to say, the basic configuration of the phase locked loop circuit according to the embodiment of the present invention is not limited to the configuration of the PLL circuit 190 shown in FIG. Hereinafter, similarly to the PLL circuit 190 illustrated in FIG. 2, signals processed by the respective components of the phase locked loop according to the first to fourth embodiments are collectively referred to as “processed signals”. In the following, the frequency of the processing signal may be described as “processing clock frequency”.

(Phase Synchronization Circuit According to First Embodiment)
[Power consumption reduction approach according to embodiments of the present invention]
Before describing the configuration of the phase locked loop circuit according to the first embodiment of the present invention, first, a power consumption reduction approach according to the embodiment of the present invention will be described.

  As described above, when the PLL circuit is applied to a communication device or the like, the PLL circuit may be required to support a plurality of operation modes. As described above for the PLL circuit, as described above, for example, the PLL circuit is commonly used for generating the carrier frequency and generating the clock frequency of the digital circuit included in the communication device, or supporting a plurality of carrier frequencies. Can be mentioned. Here, when the processing clock frequency of the processing signal processed inside cannot be switched based on the operation mode as in the conventional PLL circuit to which the conventional technology is applied, the power consumption may increase. There is.

  Therefore, in the PLL circuit according to the embodiment of the present invention, the processing clock frequency of the processing signal processed internally corresponding to the operation mode for operating the PLL circuit is switched to the frequency corresponding to the operation mode. More specifically, the PLL circuit according to the embodiment of the present invention adjusts, for example, the frequency division ratio and the divided oscillation signal output from the frequency dividing circuit 114 based on the control signal defining the operation mode. To do. As described above, the PLL circuit according to the embodiment of the present invention can control the processing clock frequency of the processing signal to be internally processed based on the control signal. Therefore, the PLL circuit according to the embodiment of the present invention can operate with the minimum necessary power consumption corresponding to the operation mode. Therefore, the PLL circuit according to the embodiment of the present invention can reduce the power consumption by switching the processing clock frequency of the processing signal processed internally based on the set operation mode based on the operation mode.

[Configuration Example of Phase Synchronization Circuit According to First Embodiment]
Next, the configuration of the phase locked loop circuit according to the first embodiment of the present invention capable of realizing the power consumption reduction approach according to the embodiment of the present invention will be described.

  FIG. 3 is an explanatory diagram showing an example of the configuration of the PLL circuit 100 (phase synchronization circuit) according to the first embodiment of the present invention.

  The PLL circuit 100 includes a reference frequency oscillating unit 102, an accumulator 104, an accumulated clock derivation unit 106, an oscillation circuit 108, a phase comparison unit 110, a data conversion unit 112, a frequency dividing circuit 114, and a bit shift circuit 116. (First bit shift unit / bit shift unit) and a frequency divider circuit 118 (first frequency divider). Here, the reference frequency oscillating unit 102, the accumulator 104, the cumulative clock deriving unit 106, the oscillation circuit 108, the phase comparison unit 110, and the frequency dividing circuit 114 shown in FIG. 3 are the components of the PLL circuit 190 shown in FIG. Has the same function and configuration. As shown in FIGS. 2 and 3, the PLL circuit 100 according to the first embodiment has basically the same configuration as the PLL circuit 190. That is, the PLL circuit 100 can control the oscillation circuit with the oscillation control signal represented by a digital value, and can converge the loop stably. Below, the structure different from the PLL circuit 190 shown in FIG. 2 among the structures of the PLL circuit 100 is demonstrated.

The bit shift circuit 116 divides the division ratio by M (M is a positive integer), and outputs the divided division ratio ({f _RF / f _REF } / M) to the accumulator 104. Here, the value M by which the bit shift circuit 116 divides the frequency division ratio is set based on the input control signal. That is, the bit shift circuit 116 controls the bit shift amount based on the input control signal.

  The control signal input to the PLL circuit 100 is generated and transmitted to the PLL circuit 100 according to the operation mode, for example, by a control unit of a communication apparatus including the PLL circuit 100, but is not limited thereto. Here, for example, a control signal in which the set value M (M is a positive integer) is increased as the operation mode is capable of relaxing the phase noise characteristic.

  The frequency dividing circuit 118 is configured by, for example, a flip-flop, and frequency-divides the N-frequency-divided oscillation signal output from the frequency dividing circuit 114 by M in synchronization with division of the frequency dividing ratio in the bit shift circuit 116. Here, the frequency dividing ratio M by which the frequency dividing circuit 118 divides the oscillation signal divided by N is set based on a control signal for controlling the bit shift circuit 116. The frequency dividing circuit 118 can perform processing in synchronization with the division of the frequency dividing ratio in the bit shift circuit 116 by performing frequency division based on the same control signal as the control signal for controlling the bit shift circuit 116.

The data converter 112 has the same configuration as the data converter 112 ′ shown in FIG. 2 except that a control signal for controlling the bit shift circuit 116 is input to the bit shift circuits 170 and 172. When the same control signal as the control signal for controlling the bit shift circuit 116 is input to the data converter 112, the processing parameters of the bit shift circuits 170 and 172 are the division parameters (values) of the division ratio in the bit shift circuit 116, respectively. It becomes a value synchronized with M). More specifically, the bit shift circuit 170 divides f _OSC / f _REF by the value (M · N) and transmits the value ({f _OSC / f _REF } / {M · N}) to the adder 162. To do. Further, the bit shift circuit 172 amplifies f _REF / k _DCO by (M · N) times, and transmits the value (M · N {f _REF / k _DCO }) to the multiplier 168.

  Here, the operation of the data converter 112 is summarized as follows. An oscillation control signal for causing the oscillator 108 to oscillate is expressed by, for example, the above Equation 1, similarly to the PLL circuit 190 shown in FIG.

In the multiplier 168 of the data conversion unit 112, M · N {f _REF / k _DCO } is multiplied, and therefore, the input of the multiplier 168 is expressed by Equation 3 below from Equation 1.

・・・（数式３）

... (Formula 3)

As shown in Equation 3, the data conversion unit 112 divides the input of the multiplier 168, that is, the output of the adder 166, similarly to the data conversion unit 112 ′ shown in FIG. The frequency division ratio ({f _RF / f _REF } / M) can be converged. Here, the output of the bit shift circuit 116 is controlled by the input control signal because the division ratio is divided by the value M corresponding to the control signal indicating the operation mode. Therefore, the data converter 112 can converge the phase comparison signal output from the phase comparator 110 to an arbitrary convergence value based on the control signal. Further, the data converter 112 amplifies the convergence value based on the control signal by the multiplier 168 and outputs it as an oscillation control signal for controlling the oscillation circuit 108. Therefore, the data converter 112 can output an oscillation control signal based on the convergence value.

  Further, when the set value A is input to the data conversion unit 112, the PLL circuit 100 sets the output of the phase comparison unit 110 to a predetermined value corresponding to the set value A, as in the PLL circuit 190 shown in FIG. It can be converged.

As described above, the PLL circuit 100 (phase synchronization circuit) according to the first embodiment of the present invention basically has the same configuration as the PLL circuit 190 shown in FIG. And a peripheral circuit 118. In the bit shift circuit 116 and the bit shift circuits 170 and 172 constituting the data conversion unit 112, the bit shift amount (M) is controlled based on the input control signal. Further, the frequency dividing circuit 118 controls the frequency dividing ratio (M) for dividing the input signal based on the input control signal, and divides the input signal (f _RF ). Therefore, the PLL circuit 100 can adjust the processing clock frequency of the processing signal processed inside the PLL circuit 100 based on the control signal. Here, the processing clock frequency of the processing signal becomes lower as the value M (M is a positive integer) set by the control signal increases. That is, for example, when the operation mode indicated by the control signal is an operation mode in which the phase noise characteristic can be reduced, the PLL circuit 100 increases the processing clock frequency of the processing signal based on the control signal having a large set value. Can be lowered. Further, when the operation mode indicated by the control signal changes from an operation mode in which the phase noise characteristics can be relaxed to an operation mode in which higher phase noise characteristics are required, the PLL circuit 100 performs control with a small set value. The processing clock frequency of the processing signal can be increased based on the signal. Furthermore, the PLL circuit 100 can converge the processing signal to an arbitrary convergence value set based on the control signal, as shown in Equation 3. Therefore, the PLL circuit 100 can operate with a processing signal having the minimum processing clock frequency required by the operation mode indicated by the control signal based on the input control signal. It is possible to prevent the operation in a difficult state. That is, when the operation mode is switched, the PLL circuit 100 can function normally with the power consumption required for the processing of the operation mode after switching. Therefore, the PLL circuit 100 can switch the processing clock frequency of the processing signal processed internally based on the set operation mode based on the operation mode, thereby reducing power consumption.

(Phase Synchronization Circuit According to Second Embodiment)
In the above description, the PLL circuit 100 (phase synchronization circuit) capable of switching the processing clock frequency of the processing signal based on the input control signal has been described. Here, in the PLL circuit 100 shown in FIG. 3, the conversion gain _{k DCO} oscillator circuit 108 showed ideal conditions, conversion gain _{k DCO} oscillator circuit 108 may sometimes include an error. Therefore, a phase locked loop circuit according to the second embodiment of the present invention corresponding to the case where the conversion gain k _DCO of the oscillation circuit 108 is the conversion gain k ′ _DCO including an error will be described next.

[An example of a problem that may occur when the conversion gain of the oscillation circuit 108 includes an error]
FIG. 4 is an explanatory diagram for explaining a problem that may occur when the conversion gain of the oscillation circuit 108 includes an error in the PLL circuit (phase synchronization circuit) according to the embodiment of the present invention. Here, FIG. 4 shows a PLL circuit 290 having a configuration similar to that of the PLL circuit 100 shown in FIG. 3, and a value (f _REF / k) depending on the conversion gain k ′ _DCO including an error in the data conversion unit 112. ' _DCO ) is shown as an example.

Hereinafter, taking the case where the conversion gain k ′ _DCO of the oscillation circuit 108 is k ′ _DCO = k _DCO (1 + a) and the value set by the control signal is M = M ₁ , the conversion gain of the oscillation circuit 108 is An example of a problem that may occur when an error is included will be described. Here, “a” indicates a conversion gain error of the oscillation circuit 108.

  The input of the multiplier 168 of the data converter 112, that is, the convergence value is expressed by, for example, Expression 4.

・・・（数式４）

... (Formula 4)

  Further, the output of the phase comparison unit 110 is expressed by Equation 5, for example. Here, Formula 5 shows a case where the output of the phase comparison unit 110 is converged to “512” by the set value A.

・・・（数式５）

... (Formula 5)

Here, when the value set by the control signal changes from M = M ₁ to M = M ₂ , the input of the multiplier 168 of the data converter 112, that is, the convergence value, for example, from Equation 4 to Equation 6: Change.

・・・（数式６）

... (Formula 6)

  At this time, a target convergence value that is a target to be finally converged in the data conversion unit 112 is expressed by Expression 7 from Expression 1.

・・・（数式７）

... (Formula 7)

  As shown in Equations 6 and 7, when the conversion gain of the oscillation circuit 108 includes an error, a difference occurs between the target convergence value and the convergence value. When a difference occurs between the target convergence value and the convergence value as described above, the difference between the target convergence value and the convergence value becomes discontinuous and appears in the output (oscillation signal) of the oscillation circuit 108.

  As described above, when the conversion gain of the oscillation circuit 108 includes an error, for example, the difference between the target convergence value and the convergence value becomes discontinuous and appears in the output of the oscillation circuit 108. Time can be long.

[Configuration Example of Phase Synchronization Circuit According to Second Embodiment]
Therefore, the configuration of the phase locked loop circuit according to the second embodiment of the present invention that can deal with a problem that may occur when the conversion gain of the oscillation circuit 108 includes an error will be described next.

  FIG. 5 is an explanatory diagram showing an example of the configuration of a PLL circuit 200 (phase synchronization circuit) according to the second embodiment of the present invention.

  The PLL circuit 200 includes a reference frequency oscillating unit 102, an accumulator 104, an accumulated clock deriving unit 106, an oscillation circuit 108, a phase comparing unit 110, a data converting unit 112, a frequency dividing circuit 114, and a bit shift circuit 116. And a frequency divider 118 and an offset compensator 202. Here, the reference frequency oscillation unit 102, the accumulator 104, the cumulative clock derivation unit 106, the oscillation circuit 108, the phase comparison unit 110, the data conversion unit 112, the frequency divider 114, the bit shift circuit 116, and the frequency divider shown in FIG. 118 has the same function and configuration as each component of the PLL circuit 100 shown in FIG. Since the PLL circuit 200 basically has the same configuration as the PLL circuit 100 according to the first embodiment, the same effects as the PLL 100 according to the first embodiment can be obtained. Below, the structure different from the PLL circuit 100 shown in FIG. 3 among the structures of the PLL circuit 200 is demonstrated.

  The offset compensation unit 202 detects an error (offset value) between the target convergence value and the convergence value based on the phase comparison signal output from the phase comparison unit 110, and is output from the bit shift circuit 116 based on the detection result. The division ratio divided based on the control signal is selectively corrected.

[Configuration Example of Offset Compensation Unit 202]
The offset compensation unit 202 includes an adder 210, a conversion circuit 212, an edge detection circuit 214, a switching circuit 218, and an adder 220.

The adder 210 subtracts the set value A from the phase comparison signal output from the phase comparison unit 110. Here, the processing in the adder 210 corresponds to, for example, subtracting “512” from Equation 5 to detect (f _RF · a · 2 ^m ) / (M ₁ · f _REF ) as an error component. .

For example, the conversion circuit 212 performs an operation shown in Formula 8. Here, when the value M set by the control signal is switched from, for example, M = M ₁ to M = M ₂ (M ₂ > M ₁ ), the conversion circuit 212 sets the error of the phase comparison signal to ( _FRF · a · 2 ^m ) / (M ₁ · f _REF ) to (f _RF · a · 2 ^m ) / (M ₂ · f _REF ) is instantaneously switched.

・・・（数式８）

... (Formula 8)

The edge detection circuit 214 detects the timing at which the value M switches from M = M ₁ to M = M ₂ (M ₂ > M ₁ ), that is, the timing at which the operation mode switches, based on the control signal. The edge detection circuit 214 transmits a detection signal corresponding to the detection result of the operation mode switching based on the control signal to the switching circuit 218. Here, the edge detection circuit 214 outputs, for example, a detection signal in which whether or not it is detected is represented by a signal level (low level / high level), but is not limited thereto.

  Based on the detection signal transmitted from the edge detection circuit 214, the switching circuit 218 selectively outputs a signal representing error compensation of the phase comparison signal transmitted from the conversion circuit 212 at the timing when the operation mode is switched. Here, the switching circuit 218 is configured by, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto. Note that the switching circuit 218 outputs a signal representing “0”, for example, when a detection signal indicating detection from the edge detection circuit 214 is not transmitted.

  The adder 220 subtracts the signal output from the switching circuit 218 from the division ratio divided based on the control signal output from the bit shift circuit 116.

  For example, with the above-described configuration, the offset compensation unit 202 detects the timing at which the operation mode is switched based on the control signal, and subtracts a value corresponding to the difference shown in Formula 8 from the output of the bit shift circuit 116 at the timing. . Therefore, the offset compensation unit 202 detects an error between the target convergence value and the actual convergence value based on the phase comparison signal output from the phase comparison unit 110, and outputs the output of the bit shift circuit 116 based on the detection result. It can be corrected.

  Note that the configuration of the offset compensator according to the embodiment of the present invention is not limited to the configuration shown in FIG. For example, the offset compensation unit according to the embodiment of the present invention further includes an average value deriving circuit that derives an average value in a certain finite period from the output of the adder 210, and the conversion circuit 212 outputs the output of the average value deriving circuit. It can also be configured to process. With the above configuration, the offset compensator according to the embodiment of the present invention can further increase the accuracy of detecting an error between the target convergence value and the actual convergence value.

As described above, the PLL circuit 200 (phase synchronization circuit) according to the second embodiment of the present invention further includes offset compensation in addition to the configuration of the PLL circuit 100 according to the first embodiment, as shown in FIG. The unit 202 is provided. Here, the PLL circuit 200 detects the switching of the operation mode based on the control signal, and calculates an error of the phase comparison signal output from the phase comparison unit 110 according to the switching of the operation mode (f _RF · a · 2 ^m ) / (M ₂ · f _REF ). Therefore, the PLL circuit 200 enables stable convergence, and can reduce discontinuity of the oscillation signal output from the oscillation circuit 108.

  Further, since the PLL circuit 200 basically has the same configuration as the PLL circuit 100 according to the first embodiment shown in FIG. 3, the same effects as the PLL circuit 100 according to the first embodiment can be obtained. it can.

(Phase Synchronization Circuit According to Third Embodiment)
The phase synchronization circuit according to the first and second embodiments has been described above as the phase synchronization circuit according to the embodiment of the present invention. However, the configuration of the phase synchronization circuit according to the embodiment of the present invention is not limited to the phase synchronization circuit according to the first and second embodiments described above. Therefore, a phase synchronization circuit according to a third embodiment that can further reduce power consumption than the phase synchronization circuit according to the first and second embodiments will be described next.

[Power consumption reduction approach of phase locked loop according to third embodiment]
Before describing the configuration of the phase locked loop circuit according to the third embodiment of the present invention, a power consumption reduction approach in the phase locked loop circuit according to the third embodiment will be described.

  The phase synchronization circuit according to the embodiment of the present invention includes the TDC 156 as shown in the basic configuration of FIG. 6A and 6B are explanatory diagrams showing an example of the configuration of the TDC 156 (time-digital conversion circuit) according to the embodiment of the present invention. Here, FIG. 6A illustrates an example in which the frequency-divided oscillation signal output from the frequency divider circuit 114 is input, that is, the configuration of the TDC 156 included in the PLL circuit 190 illustrated in FIG.

As shown in FIGS. 6A and 6B, the TDC 156 includes, for example, an inverter circuit, and uses a delay time of the inverter circuit to make a connection between the edges of the clock of the reference frequency signal and the clock of the divided oscillation signal. Digitally convert the relative time difference. Here, the digital value of the time difference between the rising edge and the rising edge of the oscillation signal clock output D _R is the reference frequency signal shown in FIG. 6B, between the falling edge of the rising edge of the output D _F is the reference frequency signal and the oscillation signal clock The digital value of the time difference is shown.

  Here, the resolution of the TDC 156 is governed by the delay time of the inverter circuit included in the TDC 156. In order to reduce the influence of the quantization error due to the resolution of the TDC 156 on the oscillation circuit 108, it is necessary to increase the processing clock frequency of the processing signal of the phase synchronization circuit according to the embodiment of the present invention. However, as described above, when the processing clock frequency of the processing signal is increased in the operation mode in which high phase noise characteristics are not required, the power consumption increases.

  In the PLL circuit 100 according to the first embodiment described above, the frequency of the signal input to the TDC 156 is adjusted according to the operation mode by dividing the frequency by M (frequency division based on the control signal) by the frequency dividing circuit 118. On the other hand, the phase locked loop according to the third embodiment of the present invention selectively switches whether to operate the TDC based on the control signal. As described above, the phase locked loop according to the third embodiment can selectively reduce the power consumption in the TDC according to the set operation mode to 0 (zero), thereby further reducing the power consumption. Can be achieved.

[Configuration Example of Phase Synchronization Circuit According to Third Embodiment]
Therefore, the configuration of the phase locked loop circuit according to the third embodiment of the present invention capable of realizing the power consumption reduction approach according to the third embodiment will be described next.

  FIG. 7 is an explanatory diagram showing an example of the configuration of a PLL circuit 300 (phase synchronization circuit) according to the third embodiment of the present invention.

  The PLL circuit 300 includes a reference frequency oscillating unit 102, an accumulator 104, an accumulated clock deriving unit 302, an oscillation circuit 108, a phase comparing unit 110, a data converting unit 112, a frequency dividing circuit 114, and a bit shift circuit 116. And a frequency dividing circuit 118. Here, the reference frequency oscillator 102, the accumulator 104, the oscillator circuit 108, the phase comparator 110, the data converter 112, the frequency divider 114, the bit shift circuit 116, and the frequency divider 118 shown in FIG. Have the same functions and configurations as the components of the PLL circuit 100 shown in FIG. Since the PLL circuit 300 basically has the same configuration as the PLL circuit 100 according to the first embodiment, the same effects as the PLL 100 according to the first embodiment can be obtained. Hereinafter, a configuration different from the PLL circuit 100 illustrated in FIG. 3 among the configurations of the PLL circuit 300 will be described.

  The accumulated clock deriving unit 302 has basically the same configuration as the accumulated clock deriving unit 106 shown in FIG. 3 except that it includes a TDC 304 that is power-on / down controlled based on an input control signal. Here, although TDC304 takes the structure provided with the switching element which switches based on a control signal for every input terminal, for example, it is not restricted above. For example, the TDC 304 can take any configuration that enables power on / down control of the TDC 304 based on the control signal.

  With the above configuration, the accumulated clock deriving unit 302 can power down the TDC 304 in an operation mode in which, for example, high phase noise characteristics are not required. Therefore, the current consumption and power consumption consumed by the accumulated clock deriving unit 302 can be further increased. Can be reduced.

  As described above, the PLL circuit 300 (phase synchronization circuit) according to the third embodiment of the present invention includes the TDC 304 that is power-on / down-controlled based on the control signal. Therefore, since the PLL circuit 300 can selectively power down the TDC 304 based on the set operation mode, the power consumption can be further reduced as compared with the phase synchronization circuits according to the first and second embodiments. be able to.

  Since the PLL circuit 300 basically has the same configuration as the PLL circuit 100 according to the first embodiment shown in FIG. 3, the same effects as the PLL circuit 100 according to the first embodiment can be obtained. it can.

[Modification of Phase Synchronous Circuit According to Third Embodiment]
In the above description, the PLL circuit 300 having basically the same configuration as the PLL circuit 100 according to the first embodiment shown in FIG. 3 is shown as the phase synchronization circuit according to the third embodiment of the present invention. However, the configuration of the phase locked loop according to the third embodiment of the present invention is not limited to the configuration shown in FIG.

  FIG. 8 is an explanatory diagram showing an example of the configuration of a PLL circuit 350 (phase synchronization circuit) according to a modification of the third embodiment of the present invention. As illustrated in FIG. 8, a PLL 350 according to the modification of the third embodiment further includes an offset compensation unit 202 according to the second embodiment in addition to the configuration of the PLL circuit 300 illustrated in FIG. 7.

  By providing the offset compensation unit 202, the PLL circuit 350 according to the modification of the third embodiment can further achieve the same effects as the PLL circuit 200 according to the second embodiment.

(Phase Synchronization Circuit According to Fourth Embodiment)
The phase synchronization circuit according to the first to third embodiments has been described above as the phase synchronization circuit according to the embodiment of the present invention. However, the configuration of the phase synchronization circuit according to the embodiment of the present invention is not limited to the phase synchronization circuit according to the first to third embodiments described above. Therefore, next, a phase locked loop circuit according to a fourth embodiment that can cope with a case where a frequency modulation component is further input will be described.

  FIG. 9 is an explanatory diagram showing an example of the configuration of a PLL circuit 400 (phase synchronization circuit) according to the fourth embodiment of the present invention.

  The PLL circuit 400 includes a reference frequency oscillation unit 102, an adder 402, an accumulator 104, an accumulated clock derivation unit 106, an oscillation circuit 108, a phase comparison unit 110, and a bit shift circuit 404 (second bit shift unit). A data converter 406, a frequency divider 114, a bit shift circuit 116, and a frequency divider 118. Here, the reference frequency oscillating unit 102, the accumulator 104, the accumulated clock deriving unit 106, the oscillation circuit 108, the phase comparing unit 110, the frequency dividing circuit 114, the bit shift circuit 116, and the frequency dividing circuit 118 shown in FIG. 3 has the same function and configuration as each component of the PLL circuit 100 shown in FIG. Since the PLL circuit 400 basically has the same configuration as the PLL circuit 100 according to the first embodiment, the same effects as the PLL 100 according to the first embodiment can be obtained. Hereinafter, a configuration different from the PLL circuit 100 illustrated in FIG. 3 in the configuration of the PLL circuit 400 will be described.

  Adder 402 adds the input frequency modulation component and the frequency division ratio, and outputs the addition result to bit shift circuit 116. Here, the frequency modulation component input to the PLL circuit 400 is input from, for example, a control unit of a communication apparatus including the PLL circuit 400, but is not limited thereto.

  The bit shift circuit 404 has the same function and configuration as the bit shift circuit 116, and divides the input frequency modulation component by a value M set by the control signal based on the control signal. Then, the bit shift circuit 404 outputs the frequency modulation component divided based on the control signal to the data conversion unit 406. By providing the bit shift circuit 404, the PLL circuit 400 can convert the input frequency modulation component into a processing signal corresponding to the set operation mode.

  The data conversion unit 406 has basically the same configuration as the data 112 according to the first embodiment shown in FIG. 3, but the output (convergence value) of the adder 166 is interposed between the adder 166 and the multiplier 168. ) And the output of the bit shift circuit 404 are further provided. With the above configuration, the input of the multiplier 408 is obtained by adding a frequency modulation component to the convergence value. Therefore, the data converter 406 can output an oscillation control signal that reflects the frequency modulation component.

  As described above, the PLL circuit 400 (phase synchronization circuit) according to the fourth embodiment of the present invention oscillates the oscillation control signal reflecting the frequency modulation component based on the input frequency modulation component and the control signal. Output to the circuit 108. Therefore, the PLL circuit 400 can directly perform frequency modulation on the oscillation circuit 108.

  Since the PLL circuit 400 basically has the same configuration as that of the PLL circuit 100 according to the first embodiment shown in FIG. 3, the same effects as the PLL circuit 100 according to the first embodiment can be obtained. it can.

[Modification of Phase Synchronous Circuit According to Fourth Embodiment]
In the above description, the PLL circuit 400 having basically the same configuration as the PLL circuit 300 according to the first embodiment shown in FIG. 3 is shown as the phase synchronization circuit according to the fourth embodiment of the present invention. However, the configuration of the phase locked loop circuit according to the fourth embodiment of the present invention is not limited to the configuration shown in FIG.

  FIG. 10 is an explanatory diagram showing an example of the configuration of a PLL circuit 450 (phase synchronization circuit) according to a modification of the fourth embodiment of the present invention. As illustrated in FIG. 10, a PLL 450 according to the modification of the fourth embodiment further includes an offset compensation unit 202 according to the second embodiment in addition to the configuration of the PLL circuit 400 illustrated in FIG. 9.

  By providing the offset compensator 202, the PLL circuit 450 according to the modification of the fourth embodiment can further exhibit the same effects as the PLL circuit 200 according to the second embodiment.

  Moreover, the phase locked loop circuit according to the fourth embodiment of the present invention combines the configuration of the PLL circuit 400 shown in FIG. 9 with the configuration of the PLL circuit 300 shown in FIG. 7, the PLL circuit 350 shown in FIG. You can also.

  The phase synchronization circuit according to the embodiment of the present invention has been described above by taking the phase synchronization circuit according to the first to fourth embodiments as an example. Here, the phase synchronization circuit according to the embodiment of the present invention can be applied to various devices such as a mobile phone, a computer such as a PC (Personal Computer), and a game machine such as a PlayStation (registered trademark) series. it can. Therefore, next, as an application example of the phase synchronization circuit according to the embodiment of the present invention, a case where the phase synchronization circuit according to the embodiment of the present invention is applied to a communication device will be described.

(Communication apparatus according to an embodiment of the present invention)
Next, a communication apparatus to which the phase synchronization circuit according to the embodiment of the present invention is applied will be described. FIG. 11 is an explanatory diagram illustrating an example of a configuration of the communication device 500 according to the embodiment of the present invention. 11 is an embodiment of the communication apparatus according to the embodiment of the present invention, and the configuration of the communication apparatus according to the embodiment of the present invention is not limited to the configuration of FIG. It goes without saying that there is nothing.

  The communication unit 500 includes a signal processing unit 502, a transmission unit 504, a reception unit 506, an antenna duplexer 508, and a communication antenna 510. When the communication unit 500 is adapted to a time division multiplexing system, an antenna switch may be used instead of the antenna duplexer 508.

  The communication device 500 may include, for example, a control unit (not shown), a ROM (not shown), a RAM (Random Access Memory; not shown), and the like. The communication apparatus 500 can connect each component by a bus as a data transmission path, for example.

  Here, the control unit (not shown) includes, for example, an MPU (Micro Processing Unit), an integrated circuit in which various processing circuits are integrated, and the like, and controls the communication device 500 as a whole. In addition, the control unit (not shown) receives various control signals that specify an operation mode, PLL ratios, and the like that are input to the phase synchronization circuit according to the embodiment of the present invention with respect to PLL circuits 520 and 530 described later. Enter the input value. In the communication apparatus according to the embodiment of the present invention, the signal processing unit 502 can also serve as a control unit (not shown). Hereinafter, a case where the signal processing unit 502 inputs the frequency division ratio to the PLL circuits 520 and 530 will be described as an example.

  A ROM (not shown) stores control data such as programs and operation parameters used by a control unit (not shown). A RAM (not shown) primarily stores programs executed by a control unit (not shown).

  The signal processing unit 502 includes, for example, a circuit that processes a baseband signal, and performs processing related to signal transmission and reception between the transmission unit 504 and the reception unit 506. Examples of the processing performed by the signal processing unit 502 include processing related to transmission of a transmission signal transmitted to an external device, processing of a reception signal transmitted from the external device transmitted from the reception unit 506 and received by the communication antenna 510, and the like. However, it is not limited to the above.

  Based on the signal transmitted from the signal processing unit 502, the transmission unit 504 processes the transmission signal to be transmitted to the external device, and transmits the processed transmission signal to the communication antenna 510 via the antenna duplexer 508.

  The transmission unit 504 includes a PLL circuit 520 and an amplifier 522. Here, the PLL circuit 520 includes a phase synchronization circuit according to the embodiment of the present invention, such as the phase synchronization circuit according to the first to fourth embodiments. Therefore, the PLL circuit 520 exhibits the above-described effects related to the phase locked loop circuit according to the embodiment of the present invention, such as reduction of power consumption. Although FIG. 11 shows an example in which the reference clock is input from the outside of the PLL circuit 520, it is not limited to the above. For example, the communication apparatus according to the embodiment of the present invention may include the reference frequency oscillation unit 102 according to the embodiment of the present invention inside the PLL circuit 520. Moreover, the structure of the transmission part with which the communication apparatus which concerns on embodiment of this invention is provided is not restricted to the structure of FIG.

  The reception unit 506 processes the reception signal transmitted from the antenna duplexer 508 and transmits the processed reception signal to the signal processing unit 502.

  The receiving unit 506 includes a PLL circuit 530, a low noise amplifier 532, a down converter 534, a low pass filter 536, and a variable gain amplifier circuit 538. Here, the PLL circuit 530 includes, for example, a phase synchronization circuit according to an embodiment of the present invention, such as a phase synchronization circuit according to the first to fourth embodiments. Therefore, the PLL circuit 530 has the above-described effects related to the phase synchronization circuit according to the embodiment of the present invention, such as reduction of power consumption. Although FIG. 11 shows an example in which the reference clock is input from the outside of the PLL circuit 530, it is not limited to the above. For example, the communication apparatus according to the embodiment of the present invention may include the reference frequency oscillation unit 102 according to the embodiment of the present invention inside the PLL circuit 530. Further, the configuration of the receiving unit included in the communication apparatus according to the embodiment of the present invention is not limited to the configuration of FIG.

  The antenna duplexer 508 mediates transmission of signals (transmission signals / reception signals) between the transmission unit 504 and the communication antenna 510, and between the communication antenna 510 and the reception unit 506. Note that an antenna switch may be used instead of the antenna duplexer 508 when supporting the time division multiplexing method.

  Communication antenna 510 transmits a transmission signal to one or more external devices and receives a signal (reception signal) transmitted from the external device.

  The communication device 500 communicates with an external device, for example, with the configuration shown in FIG. The communication device 500 includes a PLL circuit, and the PLL circuit includes a phase synchronization circuit according to the embodiment of the present invention. Therefore, the communication apparatus 500 can reduce power consumption, and can exhibit effects according to the applied phase synchronization circuit according to the embodiment of the present invention. In addition, the communication apparatus according to the embodiment of the present invention can cope with a case where the carrier frequency related to the transmission signal and the carrier frequency related to the reception signal are different by controlling the PLLs 520 and 530, respectively.

  Note that the configuration of the communication apparatus according to the embodiment of the present invention is not limited to the configuration shown in FIG. For example, the communication apparatus according to the embodiment of the present invention can include the transmission unit 504 and the reception unit 506 illustrated in FIG. 11 as one communication module (transmission / reception unit).

  As described above, the communication apparatus 500 has been described as an embodiment of the present invention, but the embodiment of the present invention is not limited to such a form. Embodiments of the present invention include various communication functions such as a computer such as an UMPC (Ultra Mobile Personal Computer), a portable communication device such as a mobile phone, and a portable game machine such as a PlayStation Portable (registered trademark). It can be applied to equipment.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  For example, in the above description, the phase synchronization circuit according to the embodiment of the present invention has been described using the PLL circuit 190 illustrated in FIG. 2 as a basic configuration. For example, the phase synchronization circuit according to the embodiment of the present invention includes a digitally controlled oscillation circuit, and can adjust any processing clock frequency of the processing signal based on a control signal that defines an operation mode (functions as a PLL circuit). Configuration can be taken. Even with the above configuration, the phase synchronization circuit according to the embodiment of the present invention can adjust the processing clock of the processing signal in accordance with the set operation mode, and thus can reduce power consumption. .

  The configuration described above shows an example of the embodiment of the present invention, and naturally belongs to the technical scope of the present invention.

It is explanatory drawing which shows the structure of the phase synchronous circuit which concerns on the prior art which applies a digitally controlled oscillation circuit to a phase synchronous circuit. It is explanatory drawing which shows an example of the fundamental structure of the PLL circuit (phase synchronous circuit) which concerns on embodiment of this invention. It is explanatory drawing which shows an example of a structure of the PLL circuit (phase synchronous circuit) which concerns on the 1st Embodiment of this invention. FIG. 5 is an explanatory diagram for explaining a problem that may occur when the conversion gain of the oscillation circuit includes an error in the PLL circuit (phase synchronization circuit) according to the embodiment of the present invention. It is explanatory drawing which shows an example of a structure of the PLL circuit (phase synchronous circuit) which concerns on the 2nd Embodiment of this invention. It is explanatory drawing which shows an example of a structure of TDC (time-digital conversion circuit) which concerns on embodiment of this invention. It is explanatory drawing which shows an example of a structure of TDC (time-digital conversion circuit) which concerns on embodiment of this invention. It is explanatory drawing which shows an example of a structure of the PLL circuit (phase synchronous circuit) which concerns on the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of a structure of the PLL circuit (phase synchronous circuit) which concerns on the modification of the 3rd Embodiment of this invention. It is explanatory drawing which shows an example of a structure of the PLL circuit (phase synchronous circuit) which concerns on the 4th Embodiment of this invention. It is explanatory drawing which shows an example of a structure of the PLL circuit (phase synchronous circuit) which concerns on the modification of the 4th Embodiment of this invention. It is explanatory drawing which shows an example of a structure of the communication apparatus which concerns on embodiment of this invention.

Explanation of symbols

100, 190, 200, 290, 300, 350, 400, 450, 520, 530 PLL circuit 102 Reference frequency oscillation unit 106, 302 Cumulative clock deriving unit 108 Oscillation circuit 110 Phase comparison unit 112, 112 ′, 406 Data conversion unit 114 , 118 Divider circuit 116, 170, 170 ', 172, 172', 404 Bit shift circuit 12, 156, 304 TDC
202 Offset Compensator 500 Communication Device 502 Signal Processor 504 Transmitter 506 Receiver 508 Antenna Duplexer 510 Communication Antenna 522 Amplifier 532 Low Noise Amplifier 534 Down Converter 536 Low Pass Filter 538 Variable Gain Amplifier Circuit

Claims (5)

An oscillation circuit that receives an oscillation control signal represented by a digital value and outputs an oscillation signal having an oscillation frequency based on the oscillation control signal;
A division ratio obtained by dividing a carrier frequency of a carrier wave related to communication with an external device by a reference frequency of a reference frequency signal and a control signal defining an operation mode are input, and the division ratio is determined based on the control signal. A first bit shift unit for dividing by a set integer value;
A first frequency divider that receives the signal based on the oscillation signal and the control signal, and divides the signal based on the oscillation signal by an integer value set based on the control signal;
In each cycle of the reference frequency signal, the first cumulative addition value obtained by cumulatively adding the output value output from the first bit shift unit and the divided oscillation signal output from the first frequency division unit A second cumulative addition value obtained by cumulatively adding the number of clocks of the signal based on the interval between edges of the clock of the reference frequency signal and the clock of the signal based on the divided oscillation signal output from the first frequency divider. A phase comparison unit that compares a fractional portion of the accumulated phase represented by a digital value detected from the time difference between the two and outputs a phase comparison signal representing the comparison result;
A data converter that converges the phase comparison signal to an arbitrary convergence value based on the control signal and outputs an oscillation control signal based on the convergence value;
A phase synchronization circuit.   An offset value for correcting an error with respect to an ideal value of the conversion gain of the oscillation circuit is derived based on the phase comparison signal, and an output value output from the first bit shift unit is calculated based on the control signal. The phase synchronization circuit according to claim 1, further comprising an offset compensation unit that selectively compensates with an offset value. Accumulated clock derivation for outputting the second cumulative addition value and the fractional part of the cumulative phase based on the signal based on the divided oscillation signal output from the first frequency divider and the reference frequency signal, respectively. Further comprising
The phase synchronization circuit according to claim 1, wherein the cumulative clock deriving unit includes a time-digital conversion circuit that selectively outputs a fractional part of the cumulative phase based on the control signal. The first bit shift unit receives a frequency division ratio obtained by adding a frequency modulation component;
A second bit shift unit for dividing the frequency modulation component by an integer value set based on the control signal;
2. The phase synchronization circuit according to claim 1, wherein the data conversion unit outputs the oscillation control signal based on an addition value of the convergence value and the divided frequency modulation component output from the second bit shift unit. . A communication antenna that receives a reception signal of a predetermined carrier frequency transmitted from one or more external devices and transmits the transmission signal of the predetermined carrier frequency to one or more external devices;
A receiver that includes a phase synchronization circuit and processes the received signal received by the communication antenna;
A transmission unit that includes a phase synchronization circuit, processes the transmission signal to be transmitted to the external device, and transmits the signal to the communication antenna;
With
Each of the phase synchronization circuits included in the reception unit and the transmission unit,
An oscillation circuit that receives an oscillation control signal represented by a digital value and outputs an oscillation signal having an oscillation frequency based on the oscillation control signal;
A division ratio obtained by dividing the predetermined carrier frequency by a reference frequency of a reference frequency signal and a control signal that defines an operation mode are input, and the division ratio is an integer value set based on the control signal. A bit shift part to divide;
A first frequency divider that receives the signal based on the oscillation signal and the control signal and divides the oscillation signal by an integer value set based on the control signal;
In each cycle of the reference frequency signal, a signal based on a first cumulative addition value obtained by cumulatively adding output values output from the bit shift unit and a frequency-divided oscillation signal output from the first frequency division unit And the time difference between the edges of the clock of the reference frequency signal and the clock of the signal based on the divided oscillation signal output from the first frequency divider. A phase comparison unit that compares the fractional part of the accumulated phase represented by the digital value detected from the signal and outputs a phase comparison signal representing the comparison result;
A data converter that converges the phase comparison signal to an arbitrary convergence value based on the control signal and outputs an oscillation control signal based on the convergence value;
A communication device comprising:

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