JPH0542814B2 - - Google Patents

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Publication number
JPH0542814B2
JPH0542814B2 JP57026284A JP2628482A JPH0542814B2 JP H0542814 B2 JPH0542814 B2 JP H0542814B2 JP 57026284 A JP57026284 A JP 57026284A JP 2628482 A JP2628482 A JP 2628482A JP H0542814 B2 JPH0542814 B2 JP H0542814B2
Authority
JP
Japan
Prior art keywords
type
diffusion region
wiring
layer
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57026284A
Other languages
Japanese (ja)
Other versions
JPS58143565A (en
Inventor
Norihide Kinugasa
Shigeru Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP57026284A priority Critical patent/JPS58143565A/en
Publication of JPS58143565A publication Critical patent/JPS58143565A/en
Publication of JPH0542814B2 publication Critical patent/JPH0542814B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は、半導体回路配線体、とりわけ、半導
体基板との間の接合容量の小さいクロス配線の構
成に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor circuit wiring body, and particularly to a structure of a cross wiring having a small junction capacitance with a semiconductor substrate.

通常、I2L（インテグレーテツド・インジエクシ
ヨン・ロジツク）で構成されるロジツク回路で
は、埋込み拡散層を有する１つのＮ型エピタキシ
ヤル島内に多数のI2Lゲートを配設し、I2Lゲート
間を相互に結線して、ロジツク回路を構成する。
そして、I2Lゲートの接地電位となるＮ型エピタ
キシヤル層の電位の上昇、I2Lゲート間の寄生ト
ランジスタ、等によつてI2Lゲートが誤動作しや
すいことから、I2Lゲートを除外したＮ型エピタ
キシヤル島の全域にＮ型コレクタウオール層を配
設して、基板を低インピーダンスにし、I2Lゲー
トの動作の安定化を図つている。また、I2Lゲー
トを数多く集積化すると、I2Lゲート間の相互配
線が複雑なものとなり、立体的に交差して配線で
きるクロス配線の構成が必要不可欠となり、I2L
を構成する島内に集積化できるクロス配線が望ま
れる。 Normally, in a logic circuit composed of I 2 L (integrated injection logic), a large number of I 2 L gates are arranged within one N-type epitaxial island with a buried diffusion layer . A logic circuit is constructed by interconnecting them.
The I 2 L gate is likely to malfunction due to an increase in the potential of the N-type epitaxial layer, which becomes the ground potential of the I 2 L gate, and parasitic transistors between the I 2 L gates. An N-type collector all layer is provided over the entire area of the excluded N-type epitaxial islands to make the substrate low impedance and stabilize the operation of the I 2 L gate. In addition, when a large number of I 2 L gates are integrated, the mutual wiring between the I 2 L gates becomes complicated , and a cross wiring configuration that can intersect three-dimensionally is essential.
It is desirable to have cross wiring that can be integrated within the islands that make up the circuit.

ここで、従来のI2Lの相互配線で用いられるク
ロス配線について、第１図、第２図を参照しなが
ら説明する。 Here, cross wiring used in conventional I 2 L mutual wiring will be explained with reference to FIGS. 1 and 2.

第１図の従来例の要部断面図に示されるよう
に、Ｎ型エピタキシヤル層１は、Ｎ型埋込み拡散
層６上に形成され、基板の主面から前記Ｎ型埋込
み拡散層６まで達成するＮ型コレクタウオール層
７で側面が包囲される。そして、Ｎ型エピタキシ
ヤル層１内にＰ型の第１拡散領域２が形成され、
さらに第１拡散領域２内にＮ型の第２拡散領域３
が形成される。そして、半導体基板の表面に形成
された絶縁膜５の所定箇所に開口部８−１，８−
２，８−３が設けられ、Ｎ型の第２拡散領域３の
両端部に配線導体４−１，４−２が接続されると
共に、配線導体４−４とＮ型の第２拡散領域３と
が絶縁された状態で立体交差し、回路構成のため
のクロス配線をなす。Ｐ型の第１拡散領域２は、
開口部８−３と配線導体４−３を介して接地さ
れ、Ｐ型の第１拡散領域２とＮ型の第２拡散領域
３とのPN接合に逆バイアスを与える。 As shown in the main part cross-sectional view of the conventional example in FIG. The sides are surrounded by an N-type collector all layer 7. Then, a P-type first diffusion region 2 is formed in the N-type epitaxial layer 1,
Furthermore, an N-type second diffusion region 3 is provided within the first diffusion region 2.
is formed. Openings 8-1, 8- are formed at predetermined locations in the insulating film 5 formed on the surface of the semiconductor substrate.
2 and 8-3 are provided, and wiring conductors 4-1 and 4-2 are connected to both ends of the N-type second diffusion region 3, and the wiring conductor 4-4 and the N-type second diffusion region 3 They cross over each other in an insulated state to form cross wiring for circuit configuration. The P-type first diffusion region 2 is
It is grounded through the opening 8-3 and the wiring conductor 4-3, and applies a reverse bias to the PN junction between the P-type first diffusion region 2 and the N-type second diffusion region 3.

第２図は第１図の平面図を示すものであり、第
１図は第２図のＡ−Ａの断面図である。数多くの
クロス配線を用いる場合、第２図に示されるよう
に、Ｐ型の第１拡散領域２内に複数の第２拡散領
域３を設けて、Ｐ型の第１拡散領域２やＮ型エピ
タキシヤル層１の面積が必要以上に大きくならな
いようにするのが、一般的である。このような状
態でＰ型の第１拡散領域２をバイアスしない場
合、第２図及び第３図に示されるように、Ｐ型の
第１拡散領域２内に併設されたＮ型の第２拡散領
域３と３とが接合容量C0（横方向）で容量結合さ
れ、１つの第２拡散領域３の電位変動が隣の他の
第２拡散領域３に電位変動を及ぼす。その等価回
路は第３図のように考えられ、第１拡散領域２を
接地することで、隣同士の第２拡散領域３と３と
の結合容量C0（横方向）による結合の防止を図ら
れるが、第２拡散領域３直下のＰ型の第１拡散領
域２がスクイズ抵抗と等価になり、容量結合を十
分に押さえることができない。また、第２拡散領
域３と第１拡散領域２（接地電位）との間に接合
容量C1（縦方向）が付随し、この接合容量C1は、
信号を伝達する過程で同信号波形を鈍らせるた
め、できるだけ小さな値が望ましい。 FIG. 2 shows a plan view of FIG. 1, and FIG. 1 is a sectional view taken along line A-A in FIG. When using a large number of cross interconnections, as shown in FIG. Generally, the area of the shell layer 1 is prevented from becoming larger than necessary. If the P-type first diffusion region 2 is not biased in this state, as shown in FIGS. 2 and 3, the N-type second diffusion region 2 adjacent to the P-type first diffusion region 2 The regions 3 and 3 are capacitively coupled by a junction capacitance C 0 (in the lateral direction), and potential fluctuations in one second diffusion region 3 exert potential fluctuations on other adjacent second diffusion regions 3 . The equivalent circuit can be considered as shown in Figure 3, and by grounding the first diffusion region 2, it is possible to prevent coupling due to the coupling capacitance C 0 (lateral direction) between the adjacent second diffusion regions 3 and 3. However, the P-type first diffusion region 2 directly under the second diffusion region 3 becomes equivalent to a squeeze resistor, and capacitive coupling cannot be suppressed sufficiently. Further, a junction capacitance C 1 (vertical direction) is attached between the second diffusion region 3 and the first diffusion region 2 (ground potential), and this junction capacitance C 1 is
It is desirable that the value be as small as possible because the signal waveform will be blunted during the process of transmitting the signal.

本発明は、上記の問題点を解消することを目的
とするものであり、クロス配線体に付随する容量
を削減すると同時に、同一構成のクロス配線体を
併設したときのクロストークが問題とならない半
導体回路配線体を提供するものである。 The present invention aims to solve the above-mentioned problems, and at the same time reduces the capacitance associated with cross wiring bodies, and at the same time provides a semiconductor in which crosstalk does not become a problem when cross wiring bodies of the same configuration are installed together. A circuit wiring body is provided.

以下、本発明による半導体回路配線体の一実施
例について、第４図に示す半導体回路配線体の一
実施例の要部断面図と、第５図に示す半導体回路
配線体の一実施例の平面図を用いて説明する。な
お、第１図から第３図迄の従来例と同一箇所には
同一番号を付している。 Hereinafter, regarding one embodiment of the semiconductor circuit wiring body according to the present invention, a sectional view of a main part of one embodiment of the semiconductor circuit wiring body shown in FIG. 4, and a plane view of one embodiment of the semiconductor circuit wiring body shown in FIG. This will be explained using figures. In addition, the same numbers are given to the same parts as in the conventional example from FIGS. 1 to 3.

本発明が従来例と異なる点は、接地電位にバイ
アスされたＮ型エピタキシヤル層１内にＰ型の第
１拡散領域２が形成され、さらに第１拡散領域２
内にＮ型の第２拡散領域３が１つだけ形成され、
Ｐ型の第１拡散領域２がフローテイング状態（バ
イアスされていない状態）としている点である。 The present invention differs from the conventional example in that a P-type first diffusion region 2 is formed in an N-type epitaxial layer 1 biased to a ground potential, and the first diffusion region 2
Only one N-type second diffusion region 3 is formed within the
The point is that the P-type first diffusion region 2 is in a floating state (non-biased state).

以上の構成の一実施例によれば、フローテイン
グ状態のＰ型の第１拡散領域２内にＮ型の第２拡
散領域３を単数に限つて設けることより、従来装
置に見られる併設されたＮ型の拡散領域３と３間
の接合容量C0による結合が避けられると共に、
Ｎ型の第２拡散領域３（クロス配線体）に付随す
る接合容量（縦方向）が、Ｐ型の第１拡散領域２
とＮ型の第２拡散領域３との間の接合容量と、Ｐ
型の第１拡散領域２とＮ型エピタキシヤル層との
間の接合容量とが直列接続になり、第２拡散領域
３（クロス配線体）と接地間の合成容量Ｃが従来
装置に比べて極めて小さくできる。 According to one embodiment of the above configuration, by providing only a single N-type second diffusion region 3 within the P-type first diffusion region 2 in a floating state, it is possible to avoid the simultaneous installation as seen in conventional devices. Coupling due to the junction capacitance C 0 between the N-type diffusion regions 3 and 3 is avoided, and
The junction capacitance (vertical direction) associated with the N-type second diffusion region 3 (cross wiring body) is different from that of the P-type first diffusion region 2.
and the N-type second diffusion region 3, and the junction capacitance between P
The junction capacitance between the first diffusion region 2 of the type and the N-type epitaxial layer is connected in series, and the combined capacitance C between the second diffusion region 3 (cross wiring body) and the ground is extremely large compared to the conventional device. Can be made smaller.

さらに詳述すれば、第４図に示されるように、
Ｐ型の第１拡散領域２とＮ型の第２拡散領域３と
の間の接合容量をC1とし、Ｐ型の第１拡散領域
２とＮ型エピタキシヤル層との間の接合容量を
C2とし、第２拡散領域３（クロス配線体）と接
地間の合成容量をＣとすると、合成容量Ｃは次式
で与えられる。 More specifically, as shown in Figure 4,
Let C1 be the junction capacitance between the P-type first diffusion region 2 and the N-type second diffusion region 3, and let C1 be the junction capacitance between the P-type first diffusion region 2 and the N-type epitaxial layer.
C 2 and the combined capacitance between the second diffusion region 3 (cross wiring body) and the ground is C, the combined capacitance C is given by the following equation.

Ｃ＝１／１／C1＋１／C2 ……(1) (1)式は、C1とC2を直列接続することで、C1の
みの場合に比べて、容量値が小さくなることを示
しており、高濃度の拡散領域同士の接合である、
Ｐ型の第１拡散領域２とＮ型の第２拡散領域３と
の接合容量C1は1000PF／mm2程度で、Ｐ型の第１
拡散領域２と低濃度のＮ型エピタキシヤル層との
接合容量C2は200PF／mm2程度であり、Ｎ型の第２
拡散領域３の接合面積をＡとし、Ｐ型の第１拡散
領域２がＮ型の第２拡散領域３に比べて３倍の面
積を持つものと仮定して、(1)式に代入すると Ｃ＝１／１／1000×Ａ＋１／200×３×Ａ＝375×Ａ（PF
）
……(2) となり、従来例の接合容量C11000×Ａ（PF）の
みの場合に比べ、第２拡散領域３（クロス配線
体）に付随する容量が１／2.5倍にすることがで
きる。C = 1/1/C 1 + 1/C 2 ...(1) Equation (1) shows that by connecting C 1 and C 2 in series, the capacitance value becomes smaller than when only C 1 is used. , which is a junction between highly concentrated diffusion regions.
The junction capacitance C 1 between the P-type first diffusion region 2 and the N-type second diffusion region 3 is about 1000PF/mm 2 .
The junction capacitance C 2 between the diffusion region 2 and the lightly doped N-type epitaxial layer is approximately 200PF/mm 2 .
Assuming that the junction area of the diffusion region 3 is A, and that the P-type first diffusion region 2 has an area three times that of the N-type second diffusion region 3, substituting it into equation (1) yields C. =1/1/1000×A+1/200×3×A=375×A(PF
)
...(2), and the capacitance associated with the second diffusion region 3 (cross wiring body) can be increased to 1/2.5 times compared to the case of only the conventional junction capacitance C 1 1000 × A (PF). .

以上説明したように本発明は、I2Lの相互配線
で用いられるクロス配線用の配線体であつて、Ｎ
型埋込み拡散層６上に形成され、かつ基板の主面
から前記Ｎ型埋込み拡散層６に達するＮ型コレク
タウオール層７で側面が包囲されると共に、接地
電位にバイアスされたＮ型エピタキシヤル層１
と、前記Ｎ型エピタキシヤル層１内に形成される
と共に、フローテイング状態にされた単一のPP
型の第１拡散領域２と、前記第１拡散領域２内に
形成された単一のＮ型の第２拡散領域３と、前記
第２拡散領域３に接続された複数の配線導体４−
１，４−２とを備えた半導体回路配線体であり、 この構成により、Ｎ型の第２拡散領域３（クロ
ス配線体）に付随する接合容量（縦方向）が直列
接続になり、第２拡散領域３（クロス配線体）と
接地間の合成容量Ｃが小さくできる。また、Ｎ型
コレクタウオール層とＮ型埋込み層が基板を低イ
ンピーダンスで接地するため、基板電位の変動が
少なくなり、同様の構成の半導体回路配線体を併
設した場合、隣接したＮ型の第２拡散領域３と３
間の容量結合が避けられる。加えて、I2Lを形成
する同一島内に配設することが可能であり、I2L
の相互配線に好適である。 As explained above, the present invention is a wiring body for cross wiring used in I 2 L mutual wiring, and
An N-type epitaxial layer formed on the type buried diffusion layer 6 and surrounded by an N-type collector all layer 7 extending from the main surface of the substrate to the N-type buried diffusion layer 6, and biased to a ground potential. 1
and a single PP formed in the N-type epitaxial layer 1 and placed in a floating state.
a single N-type second diffusion region 3 formed within the first diffusion region 2, and a plurality of wiring conductors 4- connected to the second diffusion region 3.
1 and 4-2. With this configuration, the junction capacitance (vertical direction) associated with the N-type second diffusion region 3 (cross wiring body) is connected in series, and the second The combined capacitance C between the diffusion region 3 (cross wiring body) and ground can be reduced. In addition, since the N-type collector all layer and the N-type buried layer ground the substrate with low impedance, fluctuations in the substrate potential are reduced. Diffusion areas 3 and 3
Capacitive coupling between the two is avoided. In addition, it is possible to arrange within the same island forming I 2 L, and I 2 L
Suitable for mutual wiring.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来例の半導体回路配線体の要部断面
図（第２図Ａ−Ａの断面を示す）、第２図は第１
図の平面図、第３図は従来例の寄生効果を説明す
るための等価回路図、第４図は本発明の半導体回
路配線体にかかる一実施例の要部断面図（第５図
Ｂ−Ｂの断面を示す）、第５図は第４図の平面図、
第３図は本発明の寄生効果を説明するための等価
回路図である。 １……Ｎ型エピタキシヤル層、２……Ｐ型の第
１拡散領域、３……Ｎ型の第２拡散領域、４−１
〜４−４……配線導体、５……絶縁膜、６……Ｎ
型埋込み拡散層、７……Ｎ型コレクタウオール
層、８−１〜８−３……絶縁膜の開口部。 Figure 1 is a cross-sectional view of the main part of a conventional semiconductor circuit wiring body (showing the cross section taken along line A-A in Figure 2).
3 is an equivalent circuit diagram for explaining the parasitic effect of the conventional example, and FIG. 4 is a sectional view of essential parts of an embodiment of the semiconductor circuit wiring body of the present invention (FIG. 5B- B), FIG. 5 is a plan view of FIG. 4,
FIG. 3 is an equivalent circuit diagram for explaining the parasitic effect of the present invention. DESCRIPTION OF SYMBOLS 1... N-type epitaxial layer, 2... P-type first diffusion region, 3... N-type second diffusion region, 4-1
~4-4...Wiring conductor, 5...Insulating film, 6...N
Type buried diffusion layer, 7...N-type collector all layer, 8-1 to 8-3... Opening of insulating film.

Claims (1)

【特許請求の範囲】 １ I2Lの相互配線で用いられるクロス配線用の
配線体であつて、 Ｎ型埋込み拡散層上に形成され、かつ基板の主
面から前記Ｎ型埋込み拡散層に達するＮ型コレク
タウオール層で側面が包囲されると共に、接地電
位にバイアスされたＮ型エピタキシヤル層と、 前記Ｎ型エピタキシヤル層内に形成されると共
に、フローテイング状態にされた単一のＰ型の第
１拡散領域と、 前記第１拡散領域内に形成された単一のＮ型の
第２拡散領域と、 前記第２拡散領域に接続された複数の配線導体
とを備えた半導体回路配線体。[Claims] A wiring body for cross wiring used in 1 I 2 L mutual wiring, which is formed on an N-type buried diffusion layer and reaches the N-type buried diffusion layer from the main surface of the substrate. an N-type epitaxial layer whose sides are surrounded by an N-type collector all layer and biased to a ground potential; and a single P-type epitaxial layer formed within the N-type epitaxial layer and placed in a floating state. a single N-type second diffusion region formed within the first diffusion region; and a plurality of wiring conductors connected to the second diffusion region. .
JP57026284A 1982-02-19 1982-02-19 Semiconductor circuit wiring body Granted JPS58143565A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57026284A JPS58143565A (en) 1982-02-19 1982-02-19 Semiconductor circuit wiring body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57026284A JPS58143565A (en) 1982-02-19 1982-02-19 Semiconductor circuit wiring body

Publications (2)

Publication Number Publication Date
JPS58143565A JPS58143565A (en) 1983-08-26
JPH0542814B2 true JPH0542814B2 (en) 1993-06-29

Family

ID=12188985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57026284A Granted JPS58143565A (en) 1982-02-19 1982-02-19 Semiconductor circuit wiring body

Country Status (1)

Country Link
JP (1) JPS58143565A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6095939A (en) * 1983-10-31 1985-05-29 Matsushita Electronics Corp Manufacture of semiconductor integrated circuit
JPH036853A (en) * 1989-06-05 1991-01-14 Hitachi Ltd Semiconductor integrated circuit device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552240A (en) * 1978-10-11 1980-04-16 Nec Corp Semiconductor integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5552240A (en) * 1978-10-11 1980-04-16 Nec Corp Semiconductor integrated circuit device

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JPS58143565A (en) 1983-08-26

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