JPS6095939A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the breakdown of an insulating film due to surge voltage by making the thickness of an inter-layer insulating film on a first conducting path utilizing a diffusion layer the same at that of the insulating film on an epitaxial layer for forming a semiconductor element. CONSTITUTION:An N epitaxial layer 3 is deposited on a P type Si substrate 1 into which N layers 2, 21 are buried, and isolated into insular regions 30, 31 by P layers 4. Openings are bored to an SiO2 film 11 as the surface in approximately the whole region of the region 30 and one part of the region 31, and P is diffused to form N<+> layers 12, 13. An SiO2 film 10 is shaped newly, and a base layer 14 and an emitter layer 15 are formed in the region 31. Stepped sections are formed in the film 10 in the process. Openings are bored on both sides of the N<+> layer 12 and on the layers 13, 14, 15, and Al electrodes 7, 71, 16 and a second conducting path 8, which crosses at right angles with a first conducting part (7-12-71) and is insulated by SiO2 10, are attached. According to the constitution, inter-layer dielectric breakdown due to surge voltage can be prevented because the inter-layer insulating film 10 can be formed thickly in the same manner as the upper section of the N epitaxial layer.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention provides an insulating film on a first conductive path formed in a semiconductor substrate, further forms a second conductive path on this, and connects both. This invention relates to a method for manufacturing semiconductor integrated circuits that can prevent surge breakdown of insulating films when they intersect three-dimensionally, and that can make conductive paths formed in semiconductor substrates have low resistance. be.

Conventional configurations and their problems In semiconductor integrated circuits, two conductive paths often intersect, and when they cross three-dimensionally, one conductive path is formed in the silicon substrate at the same time as the emitter of the transistor. The other conductive path is formed by an n-swelled diffusion layer, and the other conductive path is
A widely used method is to form a wiring layer on a silicon oxide film covering the swelling diffusion layer so that the two intersect three-dimensionally.

FIG. 1 is a cross-sectional view showing an example of the structure of a three-dimensional intersection of two conductive paths formed by this method. layer 3 is grown, after which the n-type silicon epitaxial layer 3 is passed through the p-type single crystal silicon substrate 1.
In the process of forming a p-type isolation layer 4 with a depth reaching up to In the step of forming the emitter region of the transistor in this p-swelled diffusion layer, a highly concentrated n-swelled diffusion layer 6 is formed at the same time, and finally contact windows are formed on both sides of the n-swelled diffusion layer 6. One end of the wiring layers 7 and 71 are connected to each other with a gap between them, and a wiring layer 8 is formed on the insulating film 9 located on the n-swelled diffusion layer 6 in a relationship perpendicular to the n-swelled diffusion layer 6. As a result, a structure is obtained in which the conductive path formed by the wiring layer 7, the n-swelled diffusion layer 6, and the wiring layer 71 intersects the conductive path formed by the wiring layer 8 in three dimensions.

By the way, in this manufacturing method, when forming the n-swelled diffusion layer 6, the silicon oxide film covering the silicon surface thereon is removed, and the silicon oxide film 9 is formed in the process of forming the n-swelled diffusion layer 6. Therefore, compared to the silicon oxide film 10 (thickness approximately 1 μm) on the n-type silicon epitaxial layer 3, the silicon oxide film 9 (thickness 0.1 μm) covering the n-swelled diffusion layer 6 is
~0.6/J m) becomes thinner. Therefore, when a surge voltage is applied between the two conductive paths insulated by the silicon oxide film 9, the silicon oxide film 9 insulating the two conductive paths is inconveniently damaged.

Object of the Invention The present invention provides a method for manufacturing a semiconductor integrated circuit that can eliminate the above-mentioned disadvantages, that is, the thickness of the silicon oxide film on the diffusion layer related to the three-dimensional intersection of two conductive paths is destroyed by surge damage. It can be made to a thickness that is unlikely to occur, and furthermore,
The present invention provides a method for manufacturing a semiconductor integrated circuit that can reduce the resistance value of a semiconductor formed in a silicon substrate.

Structure of the Invention The method for manufacturing a semiconductor integrated circuit of the present invention includes dividing an epitaxial layer of a conductivity type opposite to that formed on a semiconductor substrate of a -conductivity type into a plurality of island regions, and at least one of the island regions.
Using an insulating film as a mask, a high concentration region of the same conductivity type as this is formed in the island, and after removing all of the above insulating film, a new insulating film is formed over the entire surface, and then a new insulating film is formed on the entire surface. A base region and an emitter region are formed in the island region for transistor formation, and then the insulating film on both sides of the high concentration region and on the emitter, base, and collector regions of the transistor is removed at the same time and selectively. A three-dimensional intersection of two conductive paths is created through the steps of forming a contact window, and forming an electrode within the contact window and on an insulating film between the contact windows in a high concentration region.

According to this method, the thickness of the insulating film between two intersecting conductive paths can be increased without changing the conventional process of forming a transistor, and this insulating film can be protected from surge damage.

DESCRIPTION OF EMBODIMENTS An embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described below with reference to FIGS. 2 to 5.1. I will explain.

First, an n-type buried layer is formed by selectively doping antimony (sb) or arsenic (88) into a p-type single crystal silicon substrate 1 using a silicon oxide film as a mask using a spin-on method, ion implantation method, or capsule method. 2 and 21, and then remove all the silicon oxide film on the surface.
Subsequently, an n-type silicon layer 3 having a resistivity of 0.5 to 10 Ω is epitaxially grown over the entire surface surface to a thickness of 0.5 to 10 μm.

Next, a silicon oxide film 11 having a thickness of 0.3 to 2 μm is formed over the entire surface of the n-type silicon epitaxial layer.

The 7 silicon oxide film 11 is selectively removed surrounding the n-type buried layers 2 and 21, and boron (B) is injected into the exposed n-type epitaxial layer by thermal diffusion or ion implantation. A p-type isolation region 4 is formed by doping, and the n-type silicon epitaxial layer 3 is separated into island regions 3o and 3.
1 (Figure 2).

Next, almost the entire area of the n-type silicon epitaxial island region 30 forming the three-dimensional intersection of the conductive paths and the n-type silicon epitaxial region forming the transistor are doped with phosphorus (P), and the n-type buried layers 2 and 21 are doped with phosphorus (P). Phosphorus is diffused to the depth to form high concentration n-shaded regions 12 and 13. Note that the n-shaded region 13 is a collector all diffusion region connected to the n-type buried layer 21 when forming a transistor (FIG. 3).

Next, after removing the entire silicon oxide film 11, a new silicon oxide film 1o having a thickness of 0.8 to 2 μm is formed on the surface. Then, a base region 14 and an emitter region 15 are formed in the n-type silicon epitaxial island region 31 for forming a transistor.

This process creates a gap in the silicon oxide film (Figure 4)
.

After this, contact windows are formed on both sides of the highly concentrated n-shadow region 12 and on the emitter, base, and collector regions of the transistor, and high-purity aluminum (CAl) or By forming the electrodes 7, 71, 16 and the wiring layer 8 using aluminum containing 1 to 2% silicon by weight, the electrode 7, the n shadow area 1, as shown in FIG.
A semiconductor integrated circuit having a structure in which a first conductive path formed by 2 and electrode 71 and a second conductive path formed by wiring layer 8 intersect and are insulated by thick silicon oxide film 10 is formed.

Effects of the Invention According to the present invention, a first conductive path formed by using a diffusion layer in a silicon substrate and a second conductive path formed by a wiring layer located above the diffusion layer are connected. In between, the thickness of the insulating film that insulates the two is equal to the thickness of the insulating film covering the n-type silicon epitaxial layer9, and because it is much thicker than the insulating film formed by conventional methods, it is difficult to break down due to surge voltage. This has the effect of eliminating this problem.

In addition, the diffusion layer that forms the conductive path has a high impurity concentration and a deep diffusion depth, so the sheet resistance is 5 to 16Ω.
The present invention also has the effect of realizing an intersection with a lower resistance value of the conductive path compared to the conventional method in which the conductive path is an emitter diffusion layer having a sheet resistance of 16 to 20 Ω/port.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structure diagram of a three-dimensional intersection of two conductive paths using a conventional emitter diffusion layer as a conductive path, and FIGS. 2 to 5 are
FIG. 3 is a cross-sectional view of a three-dimensional intersection of two conductive paths and a manufacturing process of a transistor according to an embodiment of the present invention. 1...P-type single crystal silicon substrate, 2, 21...
...N-type buried layer, 3,30.31...
n-type silicon epitaxial layer, 4...p-type isolation region, 5...p-swelling diffusion layer, 6...n
Swelling diffusion layer, 7, 71...-conducting path, 8...
・Other conductive paths, 9... Silicon oxide film on the n-swelled diffusion layer, 10... Silicon oxide film on the n-type epitaxial layer, 11... Silicon oxide membrane, 1
2...High density n shadow area, 13...Collector all, 14...Base area, 16...
...Emitter region, 16...Transistor electrode. 1st ■ 1

Claims (2)

[Claims] (1) - An epitaxial layer of a conductivity type opposite to that formed on a silicon substrate of a conductivity type is separated into a plurality of island regions, and an insulating film is used as a mask in at least one of the regions of the same height. a step of forming a high concentration region of the same conductivity type as the insulating film, a step of forming a new insulating film over the entire surface after removing all of the insulating film, and a step of forming a base region and an emitter in the island region for forming a transistor in the island region. a step of forming a region;
both sides of the high concentration region and the emitter of the transistor;
(2) A method for manufacturing a semiconductor integrated circuit, comprising the step of simultaneously forming an insulating film on the base and collector regions and forming an electrode on the insulating film. (2) The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein a buried layer of a conductivity type opposite to that of the semiconductor substrate is formed directly under the island region.