JP2834186B2 - Semiconductor device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology effective when applied to a semiconductor device, for example, a semiconductor device having an input / output circuit in which a latch-up phenomenon may occur. It relates to technology that is effective to use.

[Prior art] After performing a master process such as a gate forming process, a diffusion layer forming process, an insulating film forming process, etc., a slicing process such as a contact hole forming process, a wiring layer forming process, a through hole forming process, etc. according to user specifications. A semiconductor device of a semi-custom type obtained by performing the above is known. In this semiconductor device, a semiconductor chip is divided into an internal area and an external area, and the external area is provided with an input / output circuit formed by connecting a number of input / output circuit blocks in an array. ing.

FIG. 5 shows an example of this semi-custom type semiconductor device.

In the figure, reference numeral 1 denotes a semiconductor chip,
The semiconductor chip 1 is divided into an internal region 2 and an external region 8 each composed of a gate array and a wiring channel. The external area 8 includes a number of input / output circuit blocks 4
An input / output circuit 4 formed by connecting a, 4a, to 4a in an array is provided along each of four sides of the chip 1. In this conventional example, the input / output circuit 4 includes an ECL. Blocks such as input / output circuits and TTL input / output circuits
A large number of L input / output circuits and TTL input / output circuits are formed including those adjacent to each other. Vcc, Vee, which are connected to the input / output circuit blocks 4a, 4a, to 4a, as shown in an enlarged manner in FIG.
Power supply trunk lines 7, 7 to 7 such as Vss are provided. Along the edge of the semiconductor chip 1 outside the input / output circuit 4, a large number of external pads 3 corresponding to the input / output circuit blocks 4a are provided one by one, and the external pads 3 are connected to inner leads (not shown). Have been. The exchange of electrical signals between the outside of the chip 1 and the internal area 2 is performed via the external pad 3 and the input / output circuit 4.

Next, the structure of the boundary between the input / output circuit blocks 4a, 4a will be described with reference to FIG. 7 (a sectional view taken along line BB in FIG. 6).

In this figure, a substantially central portion of the figure is a boundary between the input / output circuit blocks 4a, 4a, and in the input / output circuit blocks 4a, 4a, for example, bipolar transistors are formed on both sides. Have been. In the figure, reference numeral 10 denotes a P-type semiconductor substrate connected to the lowest potential Vee, and an N-type buried layer 11 is formed on one main surface of the P-type semiconductor substrate 10. On this N-type buried layer 11, an N well 12 is formed by epitaxial growth, and an N ⁺ diffusion layer 13 for extracting a collector is formed.
A P well 14 is formed between the N ⁺ diffusion layers 13 for extracting the collector, and a field insulating film 15 for element isolation is formed on the P well 14.

Reference numeral 15a denotes a field insulating film for making the transistor function normally.

[Problems to be Solved by the Invention] However, the semiconductor device including the input / output circuit 4 has the following problems.

That is, when a substrate current flows due to the circuit operation of the input / output circuit block 4a, the potential of the P-type semiconductor substrate 10 rises and the parasitic lateral NPN transistor operates at the boundary between the input / output circuit blocks 4a and 4a, and the latch There is a problem that an up phenomenon is caused. In particular, as described above, when the ECL input / output circuit and the TTL input / output circuit are mixed in the input / output circuit 4, the applied voltage is set to one of the ECL input / output circuit and the TTL input / output circuit. This is about twice as large (−5.2 V to 5 V) as that of a semiconductor device using only the semiconductor device, and there is a fear that the latch-up phenomenon is further promoted. This latch-up phenomenon occurs in the input / output circuit block 4.
This does not occur only when the bipolar transistors are formed on both of the transistors a and 4a, but may similarly occur when the CMOS transistors are formed on both of them.

Also, since the low-side power supply of the internal region 2 is normally set to the same power supply as the semiconductor substrate 10, that is, the lowest potential Vee, the substrate current generated by the circuit operation of the input / output circuit block 4a flows into the internal region. Then, there is also a problem that the substrate potential rises and the semiconductor device malfunctions.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device with improved latch-up strength and improved reliability that can prevent malfunction.

[Means for Solving the Problems] The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, between the input / output circuit block and between the input / output circuit block and the internal region, or on the surface of either one of the semiconductor body in the input / output circuit block and between the input / output circuit block and the internal region, A diffusion layer for flowing out a substrate current is formed.

[Operation] According to the above-mentioned means, either between the input / output circuit block and between the input / output circuit block and the internal area, or both within the input / output circuit block and between the input / output circuit block and the internal area. Since the diffusion layer for allowing the substrate current to flow out is formed on one of the semiconductor body surfaces, even if the substrate current flows by the circuit operation of the input / output circuit block, the substrate current can flow out by the diffusion layer, By preventing the operation of the parasitic lateral transistor in the input / output circuit and preventing the substrate potential from rising in the internal region, the latch-up strength is improved, malfunction is prevented, and the reliability of the semiconductor device is improved. The above-mentioned object is achieved.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a semiconductor device according to the present invention.

The semiconductor device of this embodiment is a semi-custom type semiconductor device formed by a gate array. In this semiconductor device, a semiconductor chip 1 is provided in an inner region 2 and an outer region 8 formed by a gate array and a wiring channel. The external area 8 is provided with input / output circuits 4 formed by connecting a large number of input / output circuit blocks 4a, 4a, to 4a in an array along the four sides of the chip 1. Vcc and Ve connected to the input / output circuit blocks 4a, 4a to 4a are located at positions traversing above the input / output circuit 4.
Power supply mains such as e and Vss are disposed so as to sandwich the power supply mains Vee therebetween. Along the edge of the semiconductor chip 1 outside the input / output circuit 4, one-to-one
Are provided, and the external pads 3 are connected to inner leads (not shown).

In this embodiment, the input / output circuit 4 includes blocks such as an ECL input / output circuit and a TTL input / output circuit.
A large number of ECL I / O circuits and TTL I / O circuits are formed, including adjacent ones.
Diffusion layers 5 for flowing out the substrate current are formed at the boundaries between 4a, 4a, and 4a. This diffusion layer 5
As shown in FIG. 3, it is formed on the surface (semiconductor body surface) 20 of the P well 14 exposed by opening the field insulating film 15 described in the conventional example of FIG. It is a P ⁺ diffusion layer of the same conductivity type. As shown in FIGS. 2 and 3, the length of the diffusion layer 5 in the longitudinal direction (the left-right direction in FIG. 2 and the direction perpendicular to the plane of FIG. 3) is equal to that of the diffusion layer 5. The same first aluminum wiring layer 5a is in contact, and this aluminum wiring layer 5a is, as shown in FIG.
It is connected to one of the lowest potential power supply trunk lines Vee in the second aluminum wiring layer through a number of through holes 6.
As described above, the potential of the diffusion layer 5 is set to the lowest potential Vee as in the case of the substrate potential.

In FIG. 3, the same components as those in the conventional example in FIG. 7 are denoted by the same reference numerals, and the description thereof is omitted because they are duplicated.

As described above, in the present embodiment, the diffusion layer 5 having the same potential as the lowest potential Vee is formed on the surface (semiconductor body surface) 20 of the P well 14 at the boundary between the input / output circuit blocks 4a, 4a, to 4a. Since the substrate current flows through the diffusion layer 5 even if the substrate current flows due to the circuit operation of the input / output circuit block 4a, the operation of the parasitic lateral NPN transistor in the input / output circuit 4 is prevented. Thus, it is possible to improve the latch-up strength.

Further, in the present embodiment, since the power supply main line Vee having the lowest potential and the most stable is disposed between the power supply main lines Vcc and Vss, it is possible to prevent crosstalk between the power supply main lines. Is also possible.

FIG. 4 shows a main part of another embodiment of the semiconductor device according to the present invention.

The semiconductor device of this embodiment is different from that of the previous embodiment in that a diffusion layer 5 for draining a substrate current provided at a boundary between input / output circuit blocks 4a, 4a, to 4a is provided by an input / output circuit. This is a point formed also between the blocks 4a, 4a, to 4a and the internal area 2. The potential of the newly formed diffusion layer 5 is also set to the lowest potential Vee, similarly to the potential of the diffusion layer 5 provided at the boundary between the input / output circuit blocks 4a, 4a, to 4a.

Even with this configuration, the same effect as in the previous embodiment, that is, even if a substrate current flows due to the circuit operation of the input / output circuit block 4a, it is provided at the boundary between the input / output circuit blocks 4a, 4a, to 4a. Since the substrate current flows out through the diffusion layer 5, the operation of the parasitic lateral NPN transistor in the input / output circuit 4 is prevented, and the effect of improving the latch-up strength can be achieved. Needless to say, in this embodiment, the input / output circuit blocks 4a, 4a,
Since the diffusion layer 5 for allowing the substrate current to flow out is formed also on the semiconductor body surface 20 between the internal region 2 and the internal region 2, the substrate current generated by the circuit operation of the input / output circuit block 4 a Since the substrate current flows out through the diffusion layer 5 even if it tries to flow into the semiconductor device, a rise in the substrate potential in the internal region 2 can be prevented, and a new effect of preventing malfunction can be obtained. It has become.

In each of the above embodiments, the diffusion layer for preventing the operation of the parasitic lateral NPN transistor in the input / output circuit 4 is provided at the boundary between the input / output circuit blocks 4a, 4a, to 4a. The diffusion layer 5 may be provided in the input / output circuit block 4a. Needless to say, even with such a configuration, the substrate current can flow out.

According to the semiconductor device in the above embodiment, the following main effects can be obtained.

That is, both between the input / output circuit blocks 4a, 4a, to 4a and between the input / output circuit blocks 4a, 4a, to 4a and the internal area 2,
Or, for flowing substrate current to one of the semiconductor body surfaces 20 in both the input / output circuit blocks 4a, 4a, to 4a and between the input / output circuit blocks 4a, 4a, to 4a and the internal region 2. Since the diffusion layer 5 is formed, even if a substrate current flows due to the circuit operation of the input / output circuit block 4a, the substrate current can flow out by the diffusion layer 5, and the operation of the parasitic lateral NPN transistor in the input / output circuit 4 can be improved. This prevents the substrate potential in the internal region 2 from rising, thereby improving the latch-up strength and preventing a malfunction, thereby improving the reliability.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor.

Further, in the above embodiment, the input / output circuit block 4
An application example in which a bipolar transistor is formed in each of both a and 4a is described.
Even when CMOS transistors are formed on both sides, there is a fear that a latch-up phenomenon may occur. Therefore, the present invention can be similarly applied. In this case, the diffusion layer 5 for allowing the substrate current to flow out is provided on the substrate as the surface of the semiconductor body. It will be formed on the surface.

Further, in the second embodiment, the diffusion layer 5 is formed between the input / output circuit blocks 4a, 4a, to 4a and the internal region 2, but the diffusion layer 5 is formed so as to surround the input / output circuit 4. It is also possible to form a layer 5.

In the above embodiment, only an example of application to a semiconductor device of a semi-custom type constituted by a gate array is described. However, the present invention is divided into an internal region and an external region. The present invention can be applied to all semiconductor devices having an input / output circuit formed by connecting the input / output circuit blocks in an array.

[Effects of the Invention] The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

In other words, an external area is provided with an input / output circuit formed by connecting blocks such as an ECL input / output circuit and a TTL input / output circuit in an array, and an electric signal between the internal area and the outside is provided through the input / output circuit. In the semiconductor device, the communication between the input / output circuit blocks and between the input / output circuit blocks and the internal area, or between the input / output circuit blocks and between the input / output circuit blocks and the internal area is performed. Since a diffusion layer for allowing substrate current to flow out is formed on one of the surfaces of the semiconductor body, even if the substrate current flows due to the circuit operation of the input / output circuit block, the substrate current can be flowed out by the diffusion layer. In addition, the operation of the parasitic lateral transistor in the input / output circuit is prevented, and the rise of the substrate potential in the internal region is prevented. As a result, the latch-up strength is improved and malfunction is prevented, so that the reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a plan view of an embodiment of a semiconductor device according to the present invention, FIG. 2 is an enlarged view of a main part of the embodiment, FIG. 3 is a cross-sectional view taken along line AA in FIG. FIG. 5 is an enlarged view of a main part of another embodiment of the semiconductor device according to the present invention, FIG. 5 is a plan view of the semiconductor device according to the prior art, FIG. FIG. 7 is a sectional view taken along the line BB in FIG. 2 internal region, 4 input / output circuit, 4a input / output circuit block, 5 diffusion layer for flowing out substrate current,
8 ... external area, 20 ... semiconductor body surface.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-240668 (JP, A) JP-A-55-85039 (JP, A) JP-A-61-144846 (JP, A) JP-A-2- 154446 (JP, A) JP-A-61-117467 (JP, A) JP-A-61-194846 (JP, A) JP-A-62-128544 (JP, A) JP-A-47-47085 (JP, A) JP-A-59-61046 (JP, A) JP-A-51-48944 (JP, A) JP-A-3-6853 (JP, A) JP-A-63-170951 (JP, A) JP-A-1-108743 (JP, A) JP-A-51-115783 (JP, A) JP-A-52-36482 (JP, A) JP-A-52-79787 (JP, A) JP-A-56-49560 (JP, A) ( 58) Surveyed field (Int.Cl. ⁶ , DB name) H01L 21/822 H01L 27/04

Claims (2)

(57) [Claims] An internal region defined by partitioning a P-type semiconductor substrate, an external region surrounding the internal region, and an ECL
An input / output circuit for exchanging electric signals between an external region and the internal region provided including a circuit and a TTL circuit adjacent thereto, and Vcc, Vee, which have different potentials from each other and are provided on the input / output circuit. And a power supply main line of Vss, the input / output circuit is formed on the N-type buried layer formed on the P-type semiconductor substrate, and formed on the N-type buried layer and formed on the P-type semiconductor substrate. A plurality of circuit blocks each having an N-type well surrounded by a P-type well are arranged in an array along a boundary between the internal region and the external region, and the power supply main line is provided in each of the plurality of circuit blocks. And the power supply main line Ve having the lowest potential among the power supply main lines.
e is located between the power supply trunk lines Vcc and Vss, and a P ⁺ type electrically connected to the power supply trunk line Vee is provided between the circuit blocks and between the circuit blocks and the internal region in a P-type well. A semiconductor device having a diffusion layer formed thereon. Wherein in the above P ⁺ -type diffusion layer aluminum wiring is contact in the longitudinal direction of the P ⁺ -type diffusion layer, and that said aluminum wiring is connected to said power supply wiring Vee formed on aluminum wiring The semiconductor device according to claim 1, wherein: