JPH0451836B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display synchronization circuit for a microcomputer, which is applied when output data from a microcomputer is displayed on a CRT display.

It is widely used to display output data from a microcomputer on a CRT display. Conventionally, it has been common practice to generate a display synchronizing signal for this display from the output of a crystal oscillator. Therefore, it has not been possible to superimpose output video signals from other microcomputers and external video signals such as broadcasting signals and display them on a CRT display.

The present invention solves the above-mentioned problems by making it possible to generate a display synchronization signal that is synchronized with an external video signal.

Prior to explaining the present invention, we will introduce a display synchronization signal generation circuit proposed by the applicant, which generates a plurality of display synchronization signals required when encoding output data of a microcomputer into an NTSC color video signal. The following describes the circuit. This circuit divides the output of the reference oscillator to obtain the color subcarrier frequency sc and the dot clock frequency dot, and also provides improved display synchronization to prevent color shifts and color unevenness from occurring in each display dot. This signal generator has the feature of selecting the value of each frequency as described below.

When the color subcarrier frequency is sc, the horizontal scanning frequency is H, and the dot clock frequency of display dots is dot, dot=n/msc dot=lH, where l, m, and n satisfy the relationship of integers, and the above dot Dot above so that frequency values that are integral multiples of do not fall within the range near sc above
Select.

The above frequency relationship will be explained in more detail. First, the frequency (highest frequency) of the output of the reference oscillator is set to n times the color subcarrier frequency sc (n=1,
2, 3, ...), divide this frequency to generate sc, and divide it by m (m = 1, 2, 3, ...).
), it is necessary to satisfy the relational expression dot=n/msc... to obtain the dot clock frequency dot.

Each dot must be arranged vertically on the screen, and one dot on the screen and the dot immediately above (or below) it are one horizontal scanning period (1H period).
Since it is displayed with a timing difference of , the relational expression dot=lH...where l=1, 2, 3,... can be obtained. Furthermore, the above dot is
When in the vicinity of sc, for example within the range of sc±Δsc, mutual interference occurs between these dots and sc, causing problems such as coloring of white dots. Furthermore, for example, when displaying (lighting up) and non-displaying (turning off) every 2 dots,
It is necessary that 1/2 dot does not fall within the above range of sc±Δsc, and in the case of a 3-dot period display, 1/3
dot is..., and generally it is necessary to prevent 1/kdot (k=1, 2, 3,...) from falling within the range of sc±Δsc. here,
In the standard color television signal of NTSC system, the above sc is approximately 3.58MHz, and the above Δsc is approximately 3.58MHz.
may be set to about 0.5MHz, for example. From this point of view, the specific numbers of frequency bands that can be used are 4.08 to 6.16 (MHz), 8.16 to 9.24 (MHz),
There are three bands from 12.24 to 12.32 (MHz).

Also, if the number of dots in the horizontal direction of one displayed pixel is d, then the number l of dots on one line is this d.
The value divided by is the number of characters displayed on one line, so
If the character clock frequency is c, then dc=dot... Also, if the number of displayed characters on one line is c, then c=CH... However, c, d=1, 2, 3, . . .

Specific numerical examples of each frequency in the NTSC system will be explained under the conditions of these formulas.

First, the above sc and H have the following relationship: sc=455/2H =5・7・13/2H... Using this formula and the above formula, dot=5・7・13・n/2・mH... The formula is obtained. In order for the coefficient term of H in this equation to be an integer, n must be an even number and m must be 5, 7, 13,
Or it needs to be a factor of n/2.
Furthermore, by substituting this equation into the above equation, it is necessary to satisfy the following equation: c=5.7.13.n/2.d.mH...

Hereinafter, one embodiment of the present invention will be described. In FIG. 1, 1 indicates a synchronizing signal generation circuit, and the above-mentioned relationship is applied to each of the output terminals indicated by 2, 3, 4, 5, 6, and 7. Satisfied sc, H, 2H,
Synchronizing signals for display at each frequency of V, dot, and c are taken out, and other clock or timing signals required by the microcomputer are taken out at the output terminal 8. That is, in this embodiment, the synchronizing signal generating circuit 1 functions as a timing signal generator for the entire microcomputer system. Further, 9 indicates a VCO (voltage controlled oscillator), 10 indicates a crystal oscillator, the center frequency of the VCO 9 and the oscillation frequency of the crystal oscillator 10 are made equal, and the output of either one is selected by the switch circuit 11. and is supplied to the synchronizing signal generating circuit 1.

Further, 12 indicates an input terminal to which an external video signal is supplied, and by being supplied to the synchronization separation circuit 13, a vertical synchronization signal VSY and a horizontal synchronization signal HSY are input.
are separated. This horizontal synchronization signal HSY is supplied to the phase comparison circuit 14, where it is compared with the signal of horizontal scanning frequency H generated by the synchronization signal generation circuit 1,
The comparison output is passed through the low-pass filter 15.
It is supplied to the VCO 9 as a control signal. In addition, the vertical synchronization signal VSY from the synchronization separation circuit 13
is sent to the synchronizing signal generating circuit 1 via the switch circuit 16.
This vertical synchronizing signal VSY is synchronized with the generated V signal. The switch circuit 11 selects the output of the crystal oscillator 10 when there is no need to synchronize the output of the synchronizing signal generating circuit 1 with an external video signal, and in this case, the switch circuit 16 is turned off.

FIG. 2 shows an example of the above-mentioned synchronization signal generation circuit 1, which is for displaying 80 characters on one line with (d=6) and (m=7) (n=24). The center frequency of VCO9 is set to 4sc. 1/4 frequency divider 1 for the output of this VCO9
7. A frequency divider 18 of 1/455 and a frequency divider 19 of 1/7 are connected, and a frequency divider 20 of 1/2 and a frequency divider 21 of 1/525 are connected to the frequency divider 18. It is connected.
The sc signal obtained from the frequency divider 17 is taken out to the output terminal 2, the 2H signal from the frequency divider 18 is taken out to the output terminal 4, and the 2H signal from the frequency divider 21 is taken out to the output terminal 4.
A signal of V is taken out to the output terminal 5. A vertical synchronizing signal VSY via a switch circuit 16 is supplied to a reset terminal 22 of this frequency divider 21.
Further, the H signal obtained at the output terminal 3 is fed back to the phase comparator circuit 14. Furthermore,
Other timing signals or clocks are generated by a frequency divider circuit 23 connected to the VCO 9 and taken out to the output terminal 8. And the second
In the configuration shown in the figure, the dot signal is generated by a PLL circuit.

That is, 24 indicates a VCO (voltage controlled oscillator), whose center frequency is dot. VCO
24 is a phase comparator circuit 25 and a low-pass filter 2
6 constitutes a PLL circuit, and the output of the VCO 24 is supplied to a phase comparator circuit 25 via a 1/6 frequency divider 27, where the phase is compared with the output of the frequency divider 19. Therefore, both the dot clock signal obtained at the output of the VCO 24 and the character clock signal obtained at the output of the frequency divider 27 are synchronized with the output of the VCO 9.

As shown in the configuration shown in Fig. 2, the PLL circuit forms the dot clock signal and character clock signal synchronized with the output of the VCO 9 by lowering the oscillation frequency of the VCO 9 as much as possible and preventing the generation of unnecessary radiation. This is to facilitate frequency division.

FIG. 3 shows the configuration of another example of the synchronization signal generation circuit 1, which is for displaying 40 characters on one line with (d=6) and (m=7) (n=12). It is said that Also, unlike the configuration shown in Figure 2,
The VCO 9 has a center frequency of 12sc (=42.95MHz), and the output of this VCO 9 is divided to form a signal of the required frequency.
In other words, a 1/7 frequency divider 28 is connected to the output of the VCO 9 to form a dot (=6.14MHz) dot clock signal, which is then divided into 1/6 by the frequency divider 27 to obtain A character clock signal of c (=1.02MHz) is formed. Also, by supplying the output of the VCO 9 to the 1/3 frequency divider 29,
Since it is possible to generate a signal with a frequency of 4sc in the output, by using the same configuration as in Fig. 2,
It is possible to generate signals of H, 2H, and V frequencies. Further, other timing signals or clocks are generated by a frequency divider circuit 23 connected to the VCO 9.

As understood from the description of one embodiment above,
According to the present invention, a video signal generated by a microcomputer using a display synchronization signal generated by a display synchronization signal generation circuit and an external video signal such as a television broadcast signal, an output signal of another microcomputer, or a VTR are combined. Both can be synchronized with the output signal of. Therefore, these two
When switching between two video signals and displaying them on the CRT display of a microcomputer, there are benefits such as reducing image disturbance when switching. Furthermore, by using the display synchronization signal generating circuit shown in Figure 2 or 3, the output data from the microcomputer can be colored.
It can be displayed well on a CRT display. Further, the present invention provides for alternatively selecting an internal oscillator (crystal oscillator 10) and an oscillator (voltage controlled oscillator 9) synchronized by an external video signal, and when the internal oscillator is selected,
By preventing the influence of external video signals from reaching the synchronization signal generation circuit of the CPU, etc., whether the computer is used in synchronization with external video signals or asynchronously, It has the advantage of always being able to operate stably. Further, by synchronizing not only the display synchronization signal but also the basic clock oscillator of the microcomputer system with the external video signal, timing control when displaying the external video signal can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams of one example and other examples of synchronizing signal generating circuits that can be used in the present invention. 1...Synchronization signal generation circuit, 9, 24...VCO,
12...Input terminal for external video signal, 13...Synchronization separation circuit.

Claims (1)

[Scope of Claims] 1. A sync separation circuit that separates a sync signal from an external video signal; a crystal oscillator; a voltage-controlled oscillator having the same center frequency as the oscillation frequency of the crystal oscillator; and oscillation of the crystal oscillator. a switch circuit that selectively selects the frequency and the oscillation frequency of the voltage-controlled oscillator; and a synchronization signal generation circuit that is supplied with the output of the switch circuit and outputs at least a plurality of video synchronization signals and color subcarrier signals. and a phase comparison circuit that compares the phase of the output synchronization signal of the synchronization signal generation circuit and the separated synchronization signal of the synchronization separation circuit, and the comparison output of the phase comparison circuit is used as a control signal for the voltage-controlled oscillator. A display synchronization circuit for a microcomputer, characterized in that it is supplied.