JPS58102980A - Display synchronization circuit for microcomputer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] This inventor has OR'ed output data from a microcomputer? The present invention relates to a display synchronization circuit for a microcomputer applied to a pigeon coop displayed on a display.

Displaying output data from a microcomputer using an ORT display is widely practiced. Conventionally, it has been common practice to generate a display synchronization signal for rounding the display from the output of a crystal oscillator. Therefore, it has been impossible to superimpose output video signals from other microcontrollers and external video signals such as broadcasting signals and display them on the ORT display.

Jin's invention solves the above-mentioned problems by making it possible to generate a display synchronization signal that is synchronized with an external video signal.

Before explaining Hitoshi's invention, we will explain the display synchronization signal generation circuit proposed by the applicant, and the multiple display synchronizations required when encoding the output data of a microcomputer into a color video signal of the 80 format. A circuit that generates a signal will be explained.

This circuit divides the output of the reference oscillator to generate the color subcarrier frequency ftre and the Pt clock frequency □number f
It is a display synchronization signal generator that has been improved to avoid color shift and color unevenness in each display point, and the value of each frequency is selected as shown below. It has characteristics.

The color subcarrier frequency is fmo, the horizontal scanning frequency is fm, and the dot clock frequency of display dots is faot.
When faot=”faO fdat=tfH, t, ffl, and n satisfy the relationship of integers, and the above faot
Select.

The above frequency relationship will be explained in more detail. First, the frequency (highest frequency) of the output of the reference oscillator is set to n times the color subcarrier frequency fso (n=1.2.:L...), this frequency is divided to generate fga, and m
To obtain the dot clock frequency faot by frequency division (ya = 112 g 3 +...), fdot = -! ! -fsc ・-・
It is necessary to satisfy the relational expression −・−・−−−−−・・■.

Each dot must be aligned vertically on the screen,
The / dot on the screen and the dot just above (or below) it are displayed with a timing difference of l horizontal scanning period (/H same period, so fdot = Lf H river...
・・・・・・・・・■ However, k=1.2, 3. . Furthermore, for example, it is displayed (lit) in a -dot cycle,
When hiding the display (turning off the light), the f
It is required that it not fall within the range of ma±Δfsa,
In the display of the 3r dot period, Tfdot becomes..., and it is generally necessary to set K so that 1fdot (k=1, 2, 3...) does not fall within the above range of fsa±ΔfBQ. Ru. Here, in the standard color television signal of the NTSO system, the above fsc is lYJ, A
! l MHz, and the above △fs c is, for example, O, S
It may be about MHK. From this point of view, the specific numerical values of the frequency band that can be used are y, θg ~ 1--
/ A (MHz), g-/ A ~ 9.24 (MH
s).

There are three bands: /2.2 Hiroshi~lko and 3ko (MH-).

Also, if the number of dots in the horizontal direction of the / pixel to be displayed is d, then the 9 value dividing the number t of dots on the / line by this d is /
This is the number of characters displayed on the line, so if the character clock frequency is fC, afa = f4ot
・・・・・・・・・・・・・・・■ Also, /
If the number of characters displayed on a line is C, then f = = cfH・
・・・・・・・・・・・・・・・■ However, Q + 11
”=I H2+ 3 H...

Specific numerical examples of each frequency in the 1iTso system will be explained under the conditions of these 0 to 0 formulas.

First, the above fsa and fm have the relationship of f8゜=1roku-c=1 and 13fH・・・・・・・・・・・・■. Using the above formulas ■ and ■, faot:"2,, -fH...
......The formula ■ is obtained. In order for the coefficient term of fit in this equation 0 to be an integer, n must be an even number and m must be 5.7
．． 13. Alternatively, it needs to be a factor of r1/2. Furthermore, by substituting this 0 formula into the above 0 formula, f, == 5"?'13"n f)I
・・・・・・・・・・・・・・・■2・d@fertilization formula must be satisfied.

An embodiment of Jin's invention will be described below. In FIG. 1, 1 indicates a synchronization signal generation circuit, 2.3.4,
Each of the output terminals shown in 5 and 6.7 is connected to the above-mentioned
Satisfies fga, fH, 2fH, fv.

Display synchronization signals of faot and fa frequencies are taken out, and other clock or timing signals required by the microcomputer are also taken out to an output terminal 8. In this embodiment, the synchronizing signal generating circuit 1 functions as a timing signal generator for the entire microcomputer system. Also, 9
indicates voo (voltage controlled oscillator), 10 indicates a crystal oscillator, the center frequency of VOO 9 and the oscillation frequency of crystal oscillator 10 are assumed to be equal, and the output of either one is selected by switch circuit 11. and is supplied to the synchronization signal generation circuit 1.

Further, 12 indicates an input terminal to which an external video signal is supplied, and is supplied to the synchronization separation circuit 13 to separate the vertical synchronization signal vsy and the horizontal synchronization signal H8Y. This horizontal synchronization signal H8Y is supplied to the phase comparator circuit 14, where it is compared with the signal of the horizontal scanning frequency fH generated by the synchronization signal generation circuit 1, and the comparison output is sent to the VOO 9 as a control signal via the low-pass filter 15. Supplied as.

Further, the vertical synchronization signal 'vsy from the synchronization separation circuit 13 is supplied to the synchronization signal generation circuit 1 via the switch circuit 16, so that the vertical synchronization signal VSY and the generated fv signal are synchronized. The switch circuit 11 selects the output of the crystal oscillator 10 when there is no need to synchronize the output of the synchronization signal generation circuit 1 with an external video signal, and in this case, the switch circuit 16 is turned off.

FIG. 2 shows an example of the above-mentioned synchronization signal generation circuit 1, which is used to display the / line go character at (a=6) and (m=7) (n=24). , vco
The center frequency of 9 is 4fsa. This va
For the output of o9, a τ divider 17° and a frequency divider 18
An upper division divider 20 and an upper frequency divider 21 are connected to the input terminal. The fmo signal obtained from the divider 25 17 is taken out to the output terminal 2, the zfH signal from the frequency divider 18 is taken out to the output terminal 4, and the fv signal from the divider 21 is taken out to the output terminal 5. It is taken out. The vertical synchronizing signal VBY is supplied to the reset terminal 22 of the branching unit 21 via the switch circuit 16, and the fH signal obtained at the output terminal 3 is fed back to the phase comparator circuit 14. Furthermore, va
Other timing signals or clocks are generated by the frequency divider circuit 23 connected to o9, and output to the output terminal 8.
It is taken out. In the configuration shown in Figure 2, fd
The Ot signal is generated by a PLL circuit.

The knob 24 indicates a VaO (voltage controlled token), the center frequency of which is fdat. vao24 is
Phase comparison circuit 25. PLL with low pass filter 26
The output of the VAO 24 is supplied to the phase comparator circuit 25 via the upper branch divider 27, and the phase is compared with the output of the branch divider 19. (It is assumed that both the fdOt dot clock signal obtained at the output of VOO 24C and the character clock signal obtained at the output of the divider 2T are synchronized with the output of VAO9.

As shown in the configuration shown in FIG. 2, the PLL circuit allows v
The purpose of forming the dot clock signal and character clock signal synchronized with the output of the ao9 is to lower the oscillation frequency of the woo9 as much as possible to prevent unnecessary radiation.
This is to facilitate branching.

FIG. 3 shows the configuration of another example of the synchronization signal generation circuit 1. This is for displaying the character /line II0 at (a=o@), (m=7) (n=12 ). In addition, a configuration different from that shown in Fig. 2, 12fsc (='
I, q j; MHz) center frequency is vao 9
A signal of the required frequency is formed by dividing the output of the woo 9, which has the following characteristics:

In other words, the factory divider 28 is connected to the output of the VAO 9, and a dot clock signal of faot (= 1/9 MH2) is formed. A character clock signal of (7.02 MHz) is formed. Also, vao9
By supplying the output of 1 to the branching unit 29, it is possible to generate a signal tube with a frequency of 4 faa at the output.

Signals of each frequency of 2fH and fv can be generated. Furthermore, other timing signals or clocks are generated by the frequency divider circuit 23 connected to the vao9.

As understood from the description of the above embodiment, according to the present invention, a video signal generated by a microcomputer using a display synchronization signal generated by a display synchronization signal generation circuit and an external video signal, e.g. television broadcast signal,
Both the output signal of another microcomputer or the output signal of a VTR can be synchronized. therefore,
When this one video signal is switched and displayed on a CRT display of a microcomputer, there are advantages such as reducing the disturbance in image quality at the time of switching. Further, by using a display synchronization signal generating circuit having the configuration shown in FIG. 2 or 3, output data from a microcomputer can be displayed satisfactorily on a color CRT display.

Further, by synchronizing not only the display synchronization signal but also the basic clock oscillator of the microcomputer system with the external video signal, timing control when displaying the external video signal can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIGS. 2 and 3 are block diagrams of one example and another example of a synchronizing signal generating circuit that can be used in the present invention. FIG. 1......Synchronization signal generation circuit, 9, 24...
......VOO112......Input terminal for external video signal, 13......Synchronization separation circuit. Figure 1 Figure 3 Figure 2

Claims (1)

[Claims] A display synchronization circuit for a microcomputer in which a clock oscillator for generating a display synchronization signal of the microcomputer is synchronized with an external synchronization signal.