JPH06133327A - Picture processor unit - Google Patents

Abstract

PURPOSE:To provide a composite color video signal not generating a dot clock while satisfying a relation of a frequency interleave with a horizontal synchronizing signal HD and a subcarrier. CONSTITUTION:In a picture processing unit in which a signal processing circuit 12 operated synchronously with a clock of a dot clock oscillation circuit 20 and a D/A converter circuit 14 lead a color signal to an encoder 16 and composite synchronizing signals HD, VD synchronously with the clock signal and a subcarrier of a subcarrier oscillation circuit 30 are led and the encoder 16 is used to synthesize the subcarrier modulated by the color signal, the signals HD, VD and a luminance signal are synthesized and a composite color video signal is outputted, the subcarrier oscillation circuit 30 is formed by a PLL circuit locked with the HD synchronously with the clock signal outputted from a dot clock oscillating circuit 20 and satisfying the relation of frequency interleave with the HD.

Description

Detailed Description of the Invention

[0001]

The present invention relates to digital R (red), G (green), B (blue) signals (that is, image data) processed by a signal processing circuit, that is, D / A (digital / analog). The present invention relates to an image processing device which is converted into an analog signal by a conversion circuit and then converted into a composite color video signal by an encoder (for example, a color encoder).

[0002]

2. Description of the Related Art Conventionally, this type of image processing apparatus has been constructed as shown in FIG. That is, V of personal computer
A digital R, G, B signal of a multi-bit data string recorded in a RAM (video RAM) 10 is processed by a signal processing circuit 12 (for example, horizontal frequency conversion, image enlargement / reduction processing, etc.), and then D A / A conversion circuit 14 converts the analog signal into an NTSC (National Television)
sion System Committee) encoder 16.

The display control circuit 18 has an address synchronizing with a clock output from the dot clock oscillating circuit 20.
The VRAM 10 and the signal processing circuit 12 receive timing signals such as a clock, an operation clock, and a composite synchronizing signal, respectively.
And output to the D / A conversion circuit 14 and the NTSC encoder 16. The subcarrier oscillator circuit 22 has a frequency of Fs.
c (about 3.58 MHz) subcarrier (color subcarrier)
Is output to the NTSC encoder 16. This NTS
The C encoder 16 outputs an NTSC composite color video signal in which a subcarrier modulated by a color signal, a composite sync signal and a luminance signal are combined.

[0004]

However, in the conventional example shown in FIG. 2, the dot clock oscillation circuit 20 and the subcarrier oscillation circuit 22 are independent of each other, and the clock and the subcarrier output from the dot clock oscillation circuit 20 are separated from each other. The subcarrier output from the oscillator circuit 22 is not synchronized. The composite sync signal (horizontal sync signal HD and vertical sync signal VD) of the NTSC composite color video signal is created based on the clock output from the dot clock oscillation circuit 20.

As a result, the frequency interleave relationship between the horizontal synchronizing signal HD and the subcarriers is broken, and there is a problem in that dot-like interference (dot crawl) occurs on the TV screen. Frequency interleaving means that a subcarrier is selected in the band of the luminance signal so as not to expand the bandwidth, and the subcarrier and the horizontal synchronizing signal H are selected.
D is synchronized, and the frequency Fsc of the subcarrier and the frequency Fh of the horizontal synchronizing signal HD have a predetermined relationship (for example, F
It means that sc = (455/2) × Fh) is set so that the energy components of the luminance signal and the color signal can be transmitted without overlapping.

The present invention has been made in view of the above-mentioned problems, and satisfies the frequency interleave relationship between the horizontal synchronizing signal HD and the subcarriers regardless of the frequency of the clock output from the dot clock oscillator circuit, and displays on the TV screen. An object of the present invention is to provide an image processing device capable of obtaining a high-quality composite color video signal without causing dot crawl.

[0007]

According to the present invention, a signal processing circuit and a D / A conversion circuit that operate in synchronization with a clock output from a dot clock oscillator circuit are used to process digital R, G, B signals. And lead to the encoder by performing conversion to an analog signal, lead the composite sync signal synchronized with the clock output from the dot clock oscillator circuit and the subcarrier output from the subcarrier oscillator circuit to the encoder, by the encoder, In an image processing device configured to combine a subcarrier modulated by a color signal, the composite synchronizing signal, and a luminance signal to output a composite color video signal, outputting the subcarrier oscillation circuit from the dot clock oscillation circuit Lock to the horizontal sync signal synchronized with the clock, and the horizontal sync signal and frequency Satisfy the interleave relationship is characterized in that obtained by forming a PLL circuit for outputting a sub-carrier.

[0008]

The signal processing circuit and the D / A conversion circuit operate in synchronism with the clock output from the dot clock oscillation circuit to perform digital signal processing of R, G and B signals and conversion into analog signals. Encoder (eg NTS
C encoder). Further, the composite sync signal synchronized with the clock output from the dot clock oscillator circuit and the subcarrier output from the subcarrier oscillator circuit are guided to the encoder. Therefore, the encoder synthesizes the subcarrier modulated by the color signal, the composite synchronizing signal, and the luminance signal, and outputs the composite color video signal.

At this time, the subcarrier oscillating circuit which outputs the subcarrier to the encoder is locked to the horizontal synchronizing signal which is synchronized with the clock output from the dot clock oscillating circuit, and which satisfies the frequency interleave relationship with the horizontal synchronizing signal. Since it is formed of a PLL circuit that outputs a carrier, the subcarrier guided to the encoder is
It synchronizes with the horizontal synchronizing signal synchronized with the clock output from the dot clock oscillation circuit, and satisfies the frequency interleaving relationship with this horizontal synchronizing signal. Therefore, the frequency interleave relationship between the horizontal sync signal and the subcarrier can be satisfied regardless of the frequency of the clock output from the dot clock oscillator circuit, and a high-quality composite color that does not cause dot crawl on the TV screen. Video signal can be obtained

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the image processing apparatus according to the present invention will be described below with reference to FIG. In FIG. 1, the same parts as those in FIG. In FIG. 1, reference numeral 10 is a VRAM of a personal computer or the like. A signal processing circuit 12 is connected to the VRAM 10, and a D / A conversion circuit 14 and an NTSC encoder 16 are sequentially connected to the output side of the signal processing circuit 12. . Reference numeral 18 is a display control circuit, 20 is a dot clock oscillation circuit, and the display control circuit 18 is an address clock synchronized with a clock output from the dot clock oscillation circuit 20, an operation clock, a composite synchronization signal (horizontal synchronization signal HD And a vertical synchronizing signal VD) and other timing signals are output to the VRAM 10, the signal processing circuit 12, the D / A conversion circuit 14, and the NTSC encoder 16, respectively.

Reference numeral 30 denotes a PLL (Phase Locked)
Loop) circuit, and this subcarrier oscillation circuit 30 includes a phase comparison circuit 3
2 and the LPF sequentially coupled to the output side of the phase comparison circuit 32
(Low-pass filter) 34, VCO (voltage controlled oscillator)
36 and a frequency dividing counter 38, the phase comparing circuit 32 compares the phase of the signal output from the frequency dividing counter 38 with the phase of the horizontal synchronizing signal HD output from the display control circuit 18, and outputs the comparison output to the LPF 34 and VCO36
Output to the frequency division counter 38 to lock the horizontal synchronizing signal HD and to output the horizontal synchronizing signal HD.
And subcarriers satisfying the frequency interleaving relationship are output to the NTSC encoder 16.

The VCO 36 oscillates at a frequency (n × Fsc) proportional to the output voltage from the LPF 34 (n
Is a positive integer), and outputs the oscillation signal to the NTSC encoder 16 as a subcarrier. The frequency dividing counter 38 outputs the oscillation signal output from the VCO 36 by (n ×
(455/2)) frequency-divided and output to one input side of the phase comparison circuit 32, and the horizontal synchronization signal HD output from the display control circuit 18 is input to the other input side of the phase comparison circuit 32. is doing.

Next, the operation of the above embodiment will be described with reference to FIG. (A) The display control circuit 18 uses the address clock synchronized with the clock output from the dot clock oscillation circuit 20, the operation clock, and the composite synchronization signal (horizontal synchronization signal HD and vertical synchronization signal VD) as timing signals, respectively. VRAM 10, signal processing circuit 12 and D / A
The horizontal synchronizing signal HD is output to the conversion circuit 14 and the NTSC encoder 16 and is also output to one input side of the phase comparison circuit 32 of the subcarrier oscillation circuit 30.

(B) The subcarrier oscillating circuit 30 formed by the PLL circuit outputs to the NTSC encoder 16 subcarriers locked to the horizontal synchronizing signal HD and satisfying the frequency interleaving relationship with the horizontal synchronizing signal HD. That is, the phase comparison circuit 32 compares the phase of the signal output from the frequency division counter 38 with the horizontal synchronization signal HD output from the display control circuit 18, and a voltage proportional to the phase difference is output from the LPF 34, and An oscillation signal having an oscillation frequency proportional to the output voltage is output from the VCO 36 to the frequency division counter 38, and the frequency division counter 38 outputs (n
× (455/2)) The divided signal is the phase comparison circuit 32.
VCO36 to NT by feeding back to
Subcarriers locked to the horizontal synchronizing signal HD and satisfying the frequency interleave relationship with the horizontal synchronizing signal HD are output to the SC encoder.

(C) On the other hand, the digital R, G, B signals are read from the VRAM 10 based on the address clock and the like from the display control circuit 18, and then the signal processing circuit 12 performs signal processing (for example, horizontal frequency conversion). And image enlargement / reduction processing), and then the D / A conversion circuit 14
Is converted into an analog signal and input to the NTSC encoder 16. For this reason, the NTSC encoder 16 synthesizes the subcarrier, the composite synchronizing signal (HD and VD) and the luminance signal modulated by the color signal, and the synthesized NTS.
C Outputs a composite color video signal.

In the above embodiments, the present invention has been described for the case of image processing of NTSC color television signals adopted in Japan and the United States, but the present invention is not limited to this and is adopted in, for example, Western Europe. The PA
It goes without saying that it can also be used in the case of image processing of color television signals of the L (Phase Alternate Line) system. In the case of this PAL system, the frequencies of the horizontal synchronizing signal and the vertical synchronizing signal are PAL.
The frequency Fs of the subcarriers
c to about 4.43 MHz and the frequency division ratio of the frequency division counter to n ×
(1135/4).

[0017]

As described above, the image processing apparatus according to the present invention locks the subcarrier oscillation circuit for outputting the subcarrier to the encoder to the horizontal synchronization signal synchronized with the clock output from the dot clock oscillation circuit, In addition, a subcarrier that is formed by a PLL circuit that outputs a subcarrier that satisfies the frequency interleave relationship with the horizontal synchronization signal and that is modulated by the encoder by the color signal, and a composite synchronization signal that is synchronized with the clock output from the dot clock oscillation circuit , And the luminance signal is combined and output as a composite color video signal, so that the frequency interleave relationship between the horizontal synchronization signal and the subcarriers can be satisfied regardless of the frequency of the clock output from the dot clock oscillation circuit. Good quality without dot crawl on TV screen It is possible to obtain a composite color video signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

12 ... Signal processing circuit, 14 ... D / A conversion circuit, 16 ...
NTSC encoder (an example of encoder), 18 ... Display control circuit, 20 ... Dot clock oscillation circuit, 30 ... Subcarrier oscillation circuit, 32 ... Phase comparison circuit, 34 ... L
PF, 36 ... VCO, 38 ... Dividing counter, HD ...
Horizontal sync signal, VD ... Vertical sync signal.

Claims (1)

[Claims] 1. A signal processing circuit and a D / A conversion circuit, which operate in synchronization with a clock output from a dot clock oscillator circuit, perform signal processing of digital R, G, B signals and conversion into analog signals. To the encoder, the composite sync signal synchronized with the clock output from the dot clock oscillator circuit and the subcarrier output from the subcarrier oscillator circuit to the encoder, and the subcarrier modulated with the color signal by the encoder. In the image processing device configured to combine the composite sync signal and the luminance signal to output a composite color video signal, a horizontal sync signal in which the subcarrier oscillation circuit is synchronized with a clock output from the dot clock oscillation circuit. Locked to and satisfy the frequency interleave relationship with the horizontal sync signal. The image processing apparatus characterized by being formed by a PLL circuit for outputting a subcarrier.