JPH04360194A - Display memory controller - Google Patents

Abstract

PURPOSE:To freely vary the size of a small-screen or multi-screen display without decreasing the amount of display data information. CONSTITUTION:The clock signal 110 from a synchronizing signal generating circuit 1 or the video synchronizing signal 210 from a synchronous separating means 2 is selected as a reference signal 220 by a switch 3a. The phase of this reference signal 220 is compared with the phase of a reference signal 420 by a phase comparing circuit 4b. A voltage-controlled oscillator 4d generates a reference display clock 400 according to the phase comparison result from the phase comparing circuit 4b. This reference display clock 400 is inputted to a horizontal counter 4a. The horizontal counter 4a is optionally set to a frequency division ratio (n) with the frequency division ratio setting signal of a data bus DB. The horizontal counter 4a performs frequency division by the set frequency division ratio (n) to generate a horizontal display area signal 410 and generates a reference signal 420 of constant frequency regardless of the setting of the frequency division ratio (n). Display data are read out of a display memory 6 according to those reference display clock 500, horizontal display area signal 410, and vertical display area signal 430 to make the small- screen or multi-screen display.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display memory control device for controlling display memory for teletext broadcasting, videotex, computers, and the like.

0003

2. Description of the Related Art Conventionally, in display systems for teletext receivers, videotex, computers, etc., data to be displayed is stored in a display memory, and the stored data is converted into, for example, a video signal, and characters are displayed on the display device.・Display as an image of a figure, etc. Such a system uses a display memory control device that controls writing of display data to the display memory or controls reading of data from the display memory.

In such a display system, when the display memory control device performs small-screen or multi-screen display, the following has conventionally been done. That is, the first display method for small screen or multiscreen display uses a dedicated reduced character generator for small screens or multiscreens, and uses display data from the dedicated reduced character generator when performing the display. It is used to display information.

The second display method is to compress and rewrite the display data stored in the display memory, and display the rewritten display data.

[0006] The third display method is to read display data from a display memory and use an RGB decoder to
There is a method that increases the frequency of the basic display clock until outputting the GB signal.

[0007] Furthermore, as a display method for displaying only a small screen, text can be displayed on a small screen by using picture-in-picture (PIP), which incorporates the video image of the small screen into the video image of the main screen. There is a fourth display method.

However, the first display method, the second
When displaying data on a display device using the display method or the fourth display method, no matter which method is adopted, the amount of information in the display data must be reduced, resulting in missing text. , the text display becomes very difficult to read.

In addition, in the case of the third display method described above, although it is possible to display on a small screen or multiple screens without reducing the amount of information in the text display data, it is difficult to freely set the screen size. It is.

FIG. 4 is a block diagram showing an example of the configuration of a display memory control device that implements the third display method. Now, the display memory control device shown in FIG. 4 will be explained using an NTSC video signal as an example.

In the display memory control device shown in FIG. 4, a B-mode display is performed using a synchronized clock 150 based on a clock 100 from an independently provided oscillator 10, or a B-mode display is performed using a synchronized clock 150 based on a clock 100 from an independently provided oscillator 10. There are two display modes: A-mode display using the synchronized clock 210;

In FIG. 4, the output clock 100 of oscillator 10 is introduced into the B-mode terminal of switch 30a. Further, the video signal 200 from the outside is transmitted to the synchronization separation circuit 2.
0, the synchronizing signal 210 is extracted and introduced into the A mode terminal of the switch 30b, and the phase locked loop (PL
L) introduced in 40. The switch 30b outputs the synchronization signal 210 from the synchronization separation circuit 20 in the A mode, and outputs the synchronization signal 150 as the synchronization signal 300 in the B mode.

The PLL 40 includes a horizontal counter 4 that divides the input signal 410 at a constant frequency division ratio (1/1456).
0a, a phase comparator (PD) 40b that performs a phase comparison between the output signal from the counter 40a and the synchronization signal 210 from the synchronization separation circuit 20, and a It is composed of a loop filter (LF) 40c that passes through the loop filter (LF) 40c, and a voltage controlled oscillator (VCO) 40d that oscillates a fundamental frequency clock 400 according to the DC component from the LF 40c.

Frequency signal 400 from the VCO 40d
is supplied to the A mode terminal of the switch 30a. When the switch 30a is in the A mode, the VCO
40d or the frequency signal 400 from the oscillator 10
The output clock 100 is selected as the clock signal 450 and is supplied to the horizontal counter 40a as well as to the RGB decoder 80. The output signal 410 of the horizontal counter 40a is supplied to the memory interface 70 and the RGB decoder 80. A display memory 60 is connected to this memory interface 70, and the read data 600 is provided to the RGB decoder 80 as data 610. This allows R
GB decoder 80 outputs an RGB signal 620. Another output signal 420 of the horizontal counter 40a is supplied to the vertical counter 50, and its output signal 130 is supplied to the synchronization signal generation circuit 90. The synchronization signal generation circuit 90 generates a synchronization signal 150 based on the signal 130 and the signal 140 from the vertical counter 50. The vertical counter 50 also forms a synchronization signal 430 and supplies it to the memory interface 70 and the RGB decoder 80.

The operation of such a display memory control device will be explained. The modes that can be selected by the switches 30a and 30b will be explained based on Table 1.

[0016]

[Table 1]

In Table 1, mode A is a mode used when displaying a text screen in a reduced size, such as in a superimposed display mode in a video image, and mode B is a mode used when displaying a text screen in a reduced size, such as a superimposed display mode on a video image, and mode B is a mode used when displaying text in a reduced size, such as in a text fixed display mode. This mode is used when only the screen is displayed.

PLL 40 operates as follows. That is, the horizontal synchronization component of the video synchronization signal 210 is synchronized with the decoded output reference signal 420 of the horizontal counter 40a and the PD
The phases are compared at 40b. The comparison result is converted into a voltage according to the comparison result by passing through a loop filter (LF) 40c, and is input to the VCO 40d. This V
The CO 40d outputs a mode A basic display clock 400 according to its input voltage.

On the other hand, in the NTSC video signal, the following relationship exists between the horizontal synchronization frequency fH and the color subcarrier frequency fsc.

fsc=(455/2)fH
…(1
) Here, assuming that the basic display clock is also (32/5) fsc, the above equation (1) becomes as follows. That is,
(32/5)fsc=(455/2)fH
...There is the relationship (2). Therefore, the horizontal counter 40a is set to (1/1456)
If the frequency division ratio is set to , the VCO 40d will output 32/5 fsc when the PLL 40 is phase locked. Horizontal counter 40a outputs horizontal display area signal 410, and vertical counter 50 outputs vertical display area signal 430. These two area signals and the basic display clock 450 of mode A or B are connected to the memory interface 70 and RG.
The signal is supplied to the B decoder 80. Memory interface 7
0 reads the display data 600 from the display memory 60 at the timing according to the basic display clock 450 within the horizontal and vertical display areas and outputs it to the RGB decoder 80. RGB decoder 80 outputs RGB signal 620 according to the timing by basic display clock 450.

Here, for example, in order to display a 1/4 small screen, the RGB signal output timing of the RGB decoder is set to (3
2/5) fsc, 1/2 small screen display is (16/
5) fsc, 1/1 standard screen display is (8/5) fsc.

(32/5) fsc basic display clock 4
When dividing 50 to obtain the RGB timing clock of the RGB decoder, the frequency is determined by the division ratio of the horizontal counter 4a, so it is possible to display a small screen or multiple screens of any size by setting the frequency freely. I couldn't do it.

[0023]

[Problem to be Solved by the Invention] As mentioned above, when displaying on a small screen or multiple screens without reducing the amount of text display data information, it is possible to make the frequency of the display clock variable. It is difficult to vary the size of the screen with the configuration shown in FIG. 4, and the size of the small screen or multiscreen cannot be freely set.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a display memory control device that can freely change the size of a small screen or multiscreen display without reducing the amount of text display data information.

[Configuration of the invention]

[0026]

Means for Solving the Problems To achieve the above object, the invention as set forth in claim 1 provides a synchronization signal forming means for forming a clock signal of a constant frequency, and a synchronization separation means for extracting a synchronization signal from a video signal. and a phase comparison circuit that uses the clock signal from the synchronization signal forming circuit or the video synchronization signal from the synchronization separation means as a reference signal and compares the phase of this reference signal with a reference signal, and a reference display according to the result of the phase comparison. A voltage controlled oscillator that generates a clock divides this reference display clock by a division ratio set by a division ratio setting signal to form a horizontal display area signal, and regardless of the setting of the division ratio. A phase-locked loop means including a horizontal counter that forms a reference signal having a constant frequency.

The invention according to claim 2 further provides a vertical display formed based on the reference display clock, horizontal display area signal and reference signal from the phase-locked loop means. The present invention is characterized by comprising display means for reading data from the display memory based on the area signal and forming a television signal that can be displayed on a small screen or on multiple screens.

[0028]

[Operation] According to the above configuration, the frequency of the basic display clock from reading display data from the display memory to outputting the television signal (RGB signal) by the RGB decoder can be freely varied, so the amount of text display data information can be reduced. You can freely set the horizontal size of a small screen or multiple screens without having to do so.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below with reference to the illustrated embodiments. FIG. 1 is a block diagram showing an embodiment of a display memory control device of the present invention.

In the display memory control device shown in FIG.
There are two display modes: A mode display in which the display is performed using the synchronized clock 210 extracted from 0.

In FIG. 1, a synchronizing signal forming circuit 1 includes an oscillator 1a, a horizontal counter 1b, a vertical counter 1c, and a synchronizing signal generator 1d. That is, in the synchronizing signal forming circuit 1, the oscillator 1a generates a clock 100 having a frequency of (8/5)fsc, and inputs it to the horizontal counter 1b. In the horizontal counter 1b, three clock signals 110, 120, 130 are formed, and the clock signal 110
to the B mode terminal of switch 3a, clock signal 120
is input to the vertical counter 1c, and the clock signal 130 is input to the synchronization signal generator 1d. The vertical counter 1c counts the clock signal 120 to form a clock signal 140, which is input to the synchronization signal generator 1d. The synchronization signal generator 1d forms a synchronization signal 150 from the clock signals 130 and 140, and inputs it to the B mode terminal of the switch 3b.

Furthermore, the input video signal 200 extracts a synchronization signal 210 by the synchronization separation circuit 2, and the extracted synchronization signal 210 is introduced into the A mode terminals of the switches 3a and 3b. switch 3a
Then, in the A mode, the synchronization signal 210 from the synchronization separation circuit 2 is transmitted, and in the B mode, the clock signal 11 is transmitted.
0 as the PLL reference signal 220, and select this as the PLL reference signal 220.
Enter 4. Further, the switch 30b receives the synchronization signal 210 from the synchronization separation circuit 2 when in the A mode, and receives the synchronization signal 150 from the synchronization signal 30 when in the B mode.
Select and output as 0.

The PLL 4 includes a horizontal counter 4a, a phase comparator (PD) 4b, a loop filter (LF) 4c,
It includes a voltage controlled oscillator (VCO) 4d and is configured as follows. The frequency division ratio (1/n) of the horizontal counter 4a can be arbitrarily set using the data bus DB. This horizontal counter 4a divides the frequency signal 400 at a set frequency division ratio, and divides the frequency signal 400 into a horizontal display area signal 410 and a reference signal 4.
Form 20. The reference signal 420 from the counter 4a is input to the PD 4b. PD4b has
The PLL reference signal 220 selected by the switch 3a is input. The PD 4b compares the phases of the PLL reference signal 220 and the reference signal 420 from the horizontal counter 4a,
The comparison result 230 is input to the LF4c. The LF4c forms a voltage 240 according to the comparison result 230 and inputs this to the VCO4d. The VCO 4d oscillates a basic frequency clock 400 according to the input voltage 240. This basic frequency clock 400 is supplied to the memory interface 7 and the RGB decoder 8. A display memory 6 is connected to this memory interface 7, and the read data 600 is provided to the RGB decoder 8 as data 610. This allows RGB
Decoder 8 outputs RGB signals 620. Another output signal 420 of the horizontal counter 4a is supplied to the vertical counter 5. Output signal 43 from this vertical counter 5
0 is supplied to the memory interface 7 and the RGB decoder 8.

The operation of the embodiment configured as described above will be explained. Table 2 below describes two operation modes (A mode A and B mode) by the switches 3a and 3b.

[0035]

[Table 2]

As can be seen from Table 2, in the A mode, the PLL reference signal 220 of the PLL 4 becomes the video synchronization signal 210 from the sync separation circuit 2, and in the B mode, the PLL reference signal 220 becomes the video synchronization signal 210 from the synchronization separation circuit 2.
The PLL reference signal 220 of LL4 becomes the clock signal 110 from the horizontal counter 1b of the synchronization signal forming circuit 1.

[0037] In both A mode and B mode,
The frequency division ratio n of the horizontal counter 4a can be set by the data n of the data bus DB.
The frequency of the O4d clock can be freely set.

FIG. 2 shows a state in which the PLL reference signal 220 and the reference signal 420 are locked.
At this time, the horizontal display area signal 410 and the reference display lock 4
00 can be freely varied by the frequency division ratio n of the horizontal counter 4a.

FIG. 3 is an explanatory diagram showing the relationship between the horizontal display area signal 410 and the horizontal size of the small screen.

In FIG. 2, the frequency division ratio n is, for example, n1=364.
, n2=546, n3=728, n4=1456, PLL reference signal 220, reference signal 42
0, horizontal display area signal 410, basic frequency clock 40
A state of 0 is shown.

Now, assume that the A mode is set and the frequency division ratio n is set to n1=364, for example. The horizontal synchronization component of the video synchronization signal 210 is
It is selected by switch 3a and inputted as PLL reference signal 220 to PD 4b. This PLL reference signal 220
is compared in phase with the reference signal 420 from the horizontal counter 4a in the PD 4b. The comparison result 230 from the PD 4b is converted into a voltage 240 according to the comparison result by passing through the LF 4c, and is input to the VCO 4d. As shown in FIG. 2(n1), this VCO 4d outputs a basic display clock 400 (see FIG. 2) having a frequency of (8/5)fsc according to its input voltage 240. As a result, the horizontal counter 4a outputs a horizontal display area signal 410 of 1T (T is unit time), and the vertical counter 5 outputs a vertical display area signal 430. These two area signals and the basic display clock 400 are supplied to the memory interface 7 and the RGB decoder 8. The memory interface 7 reads display data 600 from the display memory 6 at the timing according to the basic display clock 45 within the horizontal and vertical display areas, and outputs it to the RGB decoder 8. RGB decoder 8 outputs RGB signal 620 according to the timing based on basic display clock 400. As a result, the image is displayed on the entire screen as shown in FIG. 3(a).

[0042] Also, in the data bus DB, the frequency division ratio n is set to n2
= 546, when phase locked, n in Figure 2
As shown in 2, from VCO4d (12/5)fsc
A basic display clock 400 is output. As a result, the horizontal counter 4a outputs a horizontal display area signal 410 of (2/3)T, and the vertical counter 5 outputs a vertical display area signal 430. These two area signals,
A basic display clock 400 is supplied to the memory interface 7 and the RGB decoder 8. The memory interface 7 reads display data 600 from the display memory 6 at the timing according to the basic display clock 45 within the horizontal and vertical display areas, and outputs it to the RGB decoder 8. R
GB decoder 8 outputs RGB signals 620 in accordance with the timing based on basic display clock 400. As a result, the screen is displayed on the 2/3 screen as shown in FIG. 3(b).

Furthermore, the frequency division ratio n is set to n3 on the data bus DB.
= 728, when phase locked, n in Figure 2
As shown in 3, from VCO4d (16/5)fsc
A basic display clock 400 is output. As a result, the horizontal counter 4a outputs a horizontal display area signal 410 of (1/2)T, and the vertical counter 5 outputs a vertical display area signal 430. These two area signals,
A basic display clock 400 is supplied to the memory interface 7 and the RGB decoder 8. The memory interface 7 reads display data 600 from the display memory 6 at the timing according to the basic display clock 45 within the horizontal and vertical display areas, and outputs it to the RGB decoder 8. R
GB decoder 8 outputs RGB signals 620 in accordance with the timing based on basic display clock 400. As a result, the image is displayed on a 1/2 screen as shown in FIG. 3(c).

In addition, the frequency division ratio n is set to n4 on the data bus DB.
= 1456, when the phase is locked, (32/5) fs is output from VCO4d, as shown in n4 in Figure 2.
A basic display clock 400 of c is output. As a result, the horizontal counter 4a outputs a horizontal display area signal 410 of (1/4)T, and the vertical counter 5 outputs a vertical display area signal 430. These two area signals and the basic display clock 400 are connected to the memory interface 7.
and is supplied to the RGB decoder 8. The memory interface 7 reads display data 600 from the display memory 6 at the timing according to the basic display clock 45 within the horizontal and vertical display areas, and outputs it to the RGB decoder 8. RGB decoder 8 outputs RGB signal 620 according to the timing based on basic display clock 400. Thereby, as shown in FIG. 3(d), the image is displayed on the 1/4 screen.

As can be seen from the above, in this embodiment, even if the basic display clock signal 410 changes, the reference signal 420 has a constant frequency. As a result, in this embodiment, even if the horizontal display area signal 410 and the basic display clock 400 change, the PLL reference signal 22 always remains unchanged.
Can be locked to 0. In addition, in the above example,
Although the frequency division ratio n has been described using four examples, it is not limited to this and can be set arbitrarily. Therefore, according to the above embodiment, the size of the small screen can be arbitrarily set in the teletext receiving apparatus.

[0046]

As described above, according to the invention as set forth in claim 1, it is possible to obtain a basic display clock and a horizontal display area signal of any frequency, as well as a reference signal.

Further, according to the invention as claimed in claim 2, there is an effect that the horizontal size of the small screen or multi-screen can be arbitrarily set without reducing the amount of display data information. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a display memory control device according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an example of a small screen display obtained by an embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional display memory control device.

[Explanation of symbols]

1 Synchronous signal formation circuit 2 Synchronous separation circuit 3a Switch 3b Switch 4 PLL 4a Horizontal counter 4b PD 4c LF 4d VCO 5 Vertical counter 6 Timing generation circuit 7 Memory interface 8 RGB decoder

Claims (2)

[Claims] 1. Synchronization signal forming means for forming a clock signal of a constant frequency; synchronization separation means for extracting a synchronization signal from a video signal; and video synchronization from the clock signal from the synchronization signal formation circuit or from the synchronization separation means. A phase comparison circuit that uses the signal as a reference signal and compares the phase of this reference signal with a reference signal, a voltage controlled oscillator that generates a reference display clock according to the phase comparison result, and a frequency division ratio setting signal that uses this reference display clock as a reference signal. phase-locked loop means including a horizontal counter that divides the frequency at a frequency division ratio set to form a horizontal display area signal and forms a reference signal whose frequency remains constant regardless of the setting of the frequency division ratio; A display memory control device comprising: 2. Synchronization signal forming means for forming a clock signal of a constant frequency, synchronization separation means for extracting a synchronization signal from a video signal, and video synchronization from the clock signal from the synchronization signal formation circuit or from the synchronization separation means. A phase comparison circuit that uses the signal as a reference signal and compares the phase of this reference signal with a reference signal, a voltage controlled oscillator that generates a reference display clock according to the phase comparison result, and a frequency division ratio setting signal that uses this reference display clock as a reference signal. phase-locked loop means including a horizontal counter that divides the frequency at a frequency division ratio set to form a horizontal display area signal and forms a reference signal whose frequency remains constant regardless of the setting of the frequency division ratio; a reference display clock from said phase-locked loop means;
A display means for reading data from a display memory based on a horizontal display area signal and a vertical display area signal formed based on a reference signal to form a television signal that can be displayed on a small screen or multiple screens. A display memory control device.