JPH04171835A - Resin sealed semiconductor device - Google Patents

Resin sealed semiconductor device

Info

Publication number
JPH04171835A
JPH04171835A JP2299315A JP29931590A JPH04171835A JP H04171835 A JPH04171835 A JP H04171835A JP 2299315 A JP2299315 A JP 2299315A JP 29931590 A JP29931590 A JP 29931590A JP H04171835 A JPH04171835 A JP H04171835A
Authority
JP
Japan
Prior art keywords
film
silicon
bonding pad
opening
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2299315A
Other languages
Japanese (ja)
Inventor
Koichi Higuchi
樋口　孝一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2299315A priority Critical patent/JPH04171835A/en
Publication of JPH04171835A publication Critical patent/JPH04171835A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01007—Nitrogen [N]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To avoid the corrosion of a metallic wiring starting from a bonding pad part without deteriorating the reliability upon a wiring part by a method wherein silicon is led in the bonding pad part of the metallic wiring to partially augment the concentration thereof. CONSTITUTION:An aluminum wiring 13 is formed on a semiconductor substrate 11 covered with an insulating film 12 having an opening 12a and then the whole surface is coated with a silicon nitride film 14 while another opening part 14a is made in a bonding pad part 15. Furthermore, a photoresist film 19 is formed to form a photoresist pattern having an opening in almost the same size as that of the opening 14a in the bonding pad part 15. Later, the whole surface of the substrate 11 is coated with a silicon film 17 by sputtering step. Next, the photoresist film 19 is melted down using an organic solvent; the silicon film 17 on the surface and side surfaces of the film 19 are simultaneously removed; and after the formation of a silicon film 17a in almost the same size as that of the opening part 14a of the silicon nitride film 14 in the pad part 15, the whole body is heat-treated at 450 deg.C for 30 minutes in nitrogen atmosphere so as to diffuse the silicon film 17a in an aluminum film.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a resin-sealed semiconductor device.

〔従来の技術〕[Conventional technology]

第３図（ａ）は従来の樹脂封止型半導体装置を示す平面
図、第３図（ｂ）は第３図（ａ）のＸ−Ｘ線断面図であ
る。シリコンなどの半導体基板２１は所定のＰ−Ｎ接合
（図示せず）を有し、開口部２２ａを有する絶縁膜２２
で表面を被われている。絶縁膜２２上にアルミニウム配
線２３が延在しており、開口部２２ａにおいて半導体素
子とのコンタクトを取り、ボンディングパッド部２５を
除いてプラズマＣＶＤ法で形成した窒化シリコン膜２４
の保護膜で被われている。ボンディングパッド部２５に
ボンディングされたボンディング用金線２６が設けられ
ており、全体を例えばエポキシ樹脂（図示せず）の封止
によりパッケージされている。FIG. 3(a) is a plan view showing a conventional resin-sealed semiconductor device, and FIG. 3(b) is a sectional view taken along the line X--X in FIG. 3(a). A semiconductor substrate 21 made of silicon or the like has a predetermined PN junction (not shown), and an insulating film 22 having an opening 22a.
The surface is covered with An aluminum wiring 23 extends on the insulating film 22, makes contact with the semiconductor element at the opening 22a, and a silicon nitride film 24 formed by plasma CVD except for the bonding pad part 25.
covered with a protective film. A bonding gold wire 26 bonded to the bonding pad portion 25 is provided, and the entire structure is packaged by sealing with, for example, epoxy resin (not shown).

この稲の樹脂封止型半導体装置は、エポキシ樹脂の量産
性に基づいてコストダウンが図られている。The cost of this rice resin-encapsulated semiconductor device is reduced based on the mass productivity of epoxy resin.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、従来の樹脂封止型半導体装置によれば封止樹脂
として、例えば、エポキシ樹脂を使用すると、エポキシ
樹脂を通して水分が侵入するため、保護膜（２４）で被
われていないボンディングパッド部２５を起点としてア
ルミニウム配線の腐蝕が進行し、腐蝕層２７が生じる６ 〔課題を解決するための手段〕 本発明の樹脂封止型半導体装置は、上記に鑑みてなされ
たものであり、半導体基板の一生面上に設けられた絶縁
膜の開口部を通して半導体素子とコンタクトをとられ、
保護膜の開口部のボンディングパッド部において外部リ
ードと接続される金属配線を有し、前記金属配線に含ま
れるシリコン濃度を、前記ボンディングパッド部で他の
配線部分より高めたものである。However, in conventional resin-sealed semiconductor devices, when epoxy resin, for example, is used as the sealing resin, moisture enters through the epoxy resin, so the bonding pad portion 25 that is not covered with the protective film (24) is Corrosion of the aluminum wiring progresses as a starting point, and a corroded layer 27 is generated. Contact is made with the semiconductor element through an opening in an insulating film provided on the surface,
It has a metal wiring connected to an external lead at a bonding pad portion in an opening of the protective film, and the silicon concentration contained in the metal wiring is higher in the bonding pad portion than in other wiring portions.

〔実施例〕〔Example〕

第１図（ａ）は本発明の一実施例を示す半導体チップの
平面図、第１図（ｂ）は第１図（ａ）のＸ−Ｘ線断面図
である。FIG. 1(a) is a plan view of a semiconductor chip showing an embodiment of the present invention, and FIG. 1(b) is a sectional view taken along the line X--X in FIG. 1(a).

この実施例の従来例との相違は、アルミニウム配線１３
のボンディングパッド部１５に高濃度シリコン層１８が
設けられていることである。The difference between this embodiment and the conventional example is that the aluminum wiring 13
A high concentration silicon layer 18 is provided in the bonding pad portion 15 of the semiconductor device.

第２図（ａ）、（ｂ）はこの実施例の製造方法の工程順
断面図である。FIGS. 2(a) and 2(b) are cross-sectional views in order of steps of the manufacturing method of this embodiment.

はじめに所望のＰ−Ｎ接合を有し、開口部１２ａを有す
る絶縁膜１２で覆われた半導体基板１１上に厚さ１．０
μｍのアルミニウム膜を被着し、パターニングしてアル
ミニウム配線１３を形成する。次にプラズマＣＶＤ法に
より窒化シリコン膜１４を全面に卑皮着した後、ボンデ
ィングパッド部１５に開口１４ａを設ける（第１図（ａ
））。さらにフォトレジスト膜１９を形成し、前記ボン
ディングパッド部の開口１４ａとほぼ同サイズの開口を
有するフォトレジストパターンを形成する。First, a film with a thickness of 1.0 mm is placed on a semiconductor substrate 11 having a desired P-N junction and covered with an insulating film 12 having an opening 12a.
A μm thick aluminum film is deposited and patterned to form aluminum wiring 13. Next, after a silicon nitride film 14 is deposited on the entire surface by plasma CVD, an opening 14a is provided in the bonding pad portion 15 (see FIG. 1(a).
)). Furthermore, a photoresist film 19 is formed, and a photoresist pattern having an opening approximately the same size as the opening 14a of the bonding pad portion is formed.

このフォトレジスト膜の厚さは少なくとも２．０μｍが
望ましい。しかる後、基板全面にシリコン膜１７を厚さ
約３００Ａスパツタ法にて破着する（第１図（ｂ））、
次に有機溶剤にてフォトレジスト膜１６を溶かし、その
上面・側面のシリコン膜も同時にはぎとる。この様にし
てボンディングパッド部に窒化シリコン膜の開口部１４
ａとほぼ同サイズのシリコン膜１７ａを得た後、４５０
’Ｃ，３０分の熱処理を窒素雰囲気中で行い、シリコン
膜１７ａをアルミニウム膜中に拡散させ、目視てシリコ
ン色が消える様にする。最後に、エポキシ樹脂でパッケ
ージングされて製品を完成する。上述の実施例中、フォ
トレジスト１１１９は、ボンディングパッド部形成のみ
ではなく、配線の短絡を引き起こさない位置でスリット
を設ける方がシリコン膜のリフトオフ性が良好となり望
ましい。The thickness of this photoresist film is preferably at least 2.0 μm. Thereafter, a silicon film 17 with a thickness of about 300 Å is sputtered onto the entire surface of the substrate (FIG. 1(b)).
Next, the photoresist film 16 is dissolved with an organic solvent, and the silicon film on the top and side surfaces of the photoresist film 16 is also stripped off at the same time. In this way, the opening 14 of the silicon nitride film is formed in the bonding pad area.
After obtaining the silicon film 17a of approximately the same size as a, 450
A heat treatment for 30 minutes is performed in a nitrogen atmosphere to diffuse the silicon film 17a into the aluminum film so that the silicon color disappears visually. Finally, the product is packaged with epoxy resin. In the above-mentioned embodiment, it is preferable that the photoresist 1119 not only be used to form a bonding pad portion, but also to provide a slit at a position that does not cause a short circuit in the wiring, since this improves the lift-off property of the silicon film.

上述したように本発明は、ボンディングパッド部のアル
ミニウム配線にシリコンを含有させ、耐蝕性を高めたも
のである６本出願人の実験によれば、配線材料の種類と
耐蝕性（プレッシャー・クツカー・テストで判定）の関
係は、純ＡＪＩ＜ＡＪ−８ｉ合金とシリコンを添加する
二とで高まり、しかもその量が多いほど効果があった。As mentioned above, the present invention improves corrosion resistance by incorporating silicon into the aluminum wiring in the bonding pad portion.6According to experiments conducted by the applicant, the type of wiring material and the corrosion resistance (pressure, scratch, etc.) The relationship (determined by testing) was enhanced between the pure AJI<AJ-8i alloy and the addition of silicon, and the greater the amount, the more effective it was.

しかしながらＡ１−８ｉ合金はエレクトロ・マイグレー
ションに弱く、またコンタクト部でシリコン・ノジュー
ル（ｎｏｄｕｌｅ）不良を引き起こしやすくシリコン添
加量はあまり多くできない状況にある。このなめにもボ
ンディングパッド部のみシリコン濃度を高める必要性が
ある。However, the A1-8i alloy is susceptible to electromigration and tends to cause silicon nodule defects in the contact area, so the amount of silicon added cannot be increased too much. For this reason, it is necessary to increase the silicon concentration only in the bonding pad portion.

なお、窒化シリコン膜にボンディングパッド部の開口を
形成した後、シリコン膜を被着し、これをフォトレジス
ト膜をマスクとし、ボンディングパッド部を残して弗酸
・硝酸混合液で選択エッチした後、熱処理を施す方法で
高濃度シリコン層を形成してもよい。After forming an opening for the bonding pad in the silicon nitride film, a silicon film was deposited, and this was selectively etched using a hydrofluoric acid/nitric acid mixture using a photoresist film as a mask, leaving the bonding pad. The high concentration silicon layer may be formed by a method of performing heat treatment.

いずれにせよ、ボンディングパッド部のみでアルミニウ
ム配線中のシリコン濃度が高まれば耐湿性向上に効果が
ある。In any case, if the silicon concentration in the aluminum wiring is increased only in the bonding pad portion, it will be effective in improving moisture resistance.

〔発明の効果〕〔Effect of the invention〕

以上説明した通り、本発明の樹脂封止型半導体装置によ
れば、金属配線のボンディングパッド部にシリコンを導
入し、しかも部分的に濃度を高めたため、配線部の信頼
性をそこねることなくボンディングパッド部を起点とす
る金属配線の腐蝕を防止することができる効果がある。As explained above, according to the resin-sealed semiconductor device of the present invention, silicon is introduced into the bonding pad portion of the metal wiring and the concentration is partially increased, so that the bonding pad can be bonded without impairing the reliability of the wiring portion. This has the effect of preventing corrosion of the metal wiring starting from the part.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）は本発明の一実施例を示す半導体チップの
平面図、第１図（ｂ）は第１図（ａ）のＸ−Ｘ線断面図
、第２図（ａ）、（ｂ）は一実施例の製造方法の工程順
断面図、第３図（ａ）は従来例を示す半導体チップの平
面図、第３図（ｂ）は第３図（ａ）のＸ−Ｘ＠断面図で
ある。 １１．２１・・・半導体基板、１２．２２・・・絶縁膜
、１３．２３・・・アルミニウム配線、１４．２４・・
・窒化シリコン膜く表面保護膜）、１４ａ、２４ａ・・
・開口、１５．２５・・・ボンディングパッド部、１６
．２６・・・ボンディング用金線、１７ａ、１７ｂ・・
−シリコン膜、２７・・・アルミニウム腐蝕層、１８・
・・高濃度シリコン層、１ａ・・・フォトレジスト膜。FIG. 1(a) is a plan view of a semiconductor chip showing an embodiment of the present invention, FIG. 1(b) is a sectional view taken along the line X--X of FIG. 1(a), and FIG. b) is a step-by-step sectional view of the manufacturing method of one embodiment, FIG. 3(a) is a plan view of a semiconductor chip showing a conventional example, and FIG. 3(b) is a cross-sectional view taken along line X-X@ of FIG. 3(a). FIG. 11.21...Semiconductor substrate, 12.22...Insulating film, 13.23...Aluminum wiring, 14.24...
・Silicon nitride film (surface protection film), 14a, 24a...
・Opening, 15.25...Bonding pad part, 16
．． 26...Gold wire for bonding, 17a, 17b...
- Silicon film, 27... Aluminum corrosion layer, 18.
... High concentration silicon layer, 1a... Photoresist film.

Claims (1)

【特許請求の範囲】[Claims] 　半導体基板の一主面上に設けられた絶縁膜の開口部を
通して半導体素子とコンタクトをとられ、保護膜の開口
部のボンディングパッド部において外部リードと接続さ
れる金属配線を有し、前記金属配線に含まれるシリコン
濃度を、前記ボンディングパッド部で他の配線部分より
高めたことを特徴とする樹脂封止型半導体装置。The metal wiring is connected to the semiconductor element through an opening in an insulating film provided on one main surface of the semiconductor substrate, and is connected to an external lead at a bonding pad portion of the opening in the protective film. A resin-sealed semiconductor device characterized in that the concentration of silicon contained in the bonding pad portion is higher than that in other wiring portions.
JP2299315A 1990-11-05 1990-11-05 Resin sealed semiconductor device Pending JPH04171835A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2299315A JPH04171835A (en) 1990-11-05 1990-11-05 Resin sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2299315A JPH04171835A (en) 1990-11-05 1990-11-05 Resin sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPH04171835A true JPH04171835A (en) 1992-06-19

Family

ID=17870949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2299315A Pending JPH04171835A (en) 1990-11-05 1990-11-05 Resin sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPH04171835A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100702449B1 (en) * 2005-12-13 2007-04-03 서울반도체 주식회사 Method for manufacturing light emitting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100702449B1 (en) * 2005-12-13 2007-04-03 서울반도체 주식회사 Method for manufacturing light emitting device

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