JPH0290637A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0290637A JPH0290637A JP24503588A JP24503588A JPH0290637A JP H0290637 A JPH0290637 A JP H0290637A JP 24503588 A JP24503588 A JP 24503588A JP 24503588 A JP24503588 A JP 24503588A JP H0290637 A JPH0290637 A JP H0290637A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- bonding pad
- passivation film
- covering
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 43
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 24
- 238000002161 passivation Methods 0.000 claims abstract description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000010931 gold Substances 0.000 claims abstract description 16
- 229910052737 gold Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000011247 coating layer Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 7
- 238000007747 plating Methods 0.000 abstract description 4
- 238000001704 evaporation Methods 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000005260 corrosion Methods 0.000 description 3
- 230000007797 corrosion Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- -1 gold-aluminum Chemical compound 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特にアルミ・ボン
ディング・パッド部の耐湿性を向上せしめた半導体集積
回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device in which the moisture resistance of an aluminum bonding pad portion is improved.
第２図は従来の半導体集積回路装置のアルミ・ボンディ
ング・パッド部近傍の断面図である。半導体集積回路装
置の電極３は、通常、アルミニウムで形成されているが
、これはパッケージ外部から水分が侵入した際、極めて
短時間のうちに腐食してしまう、この現象はプレッシャ
ー・クツカー・テスト（ＰＣＴ）で顕著に現われ、−特
にワイヤ・ボンディングするアルミ・ボンディング・パ
ッド部５を形成するパッシベーション膜４の開口部が極
めて腐食しやすい、ここで、１および２は半導体基板お
よびフィールド絶縁膜をそれぞれ示している。FIG. 2 is a cross-sectional view of the vicinity of an aluminum bonding pad portion of a conventional semiconductor integrated circuit device. The electrodes 3 of semiconductor integrated circuit devices are usually made of aluminum, but when moisture enters from outside the package, it corrodes in a very short period of time. PCT), - especially the opening of the passivation film 4 forming the aluminum bonding pad part 5 for wire bonding is extremely susceptible to corrosion. It shows.
このパッシベーション膜４は、細いアルミ配線を水分か
ら保護する目的で施されているが、ワイヤ・ボンディン
グ・パッド部５上のパッシベーション膜は開口されてい
るので、耐湿性試験、特にＰＣＴ （プレッシャー・ク
ツカー・テスト）を行うと、保護膜を欠くこの開口部直
下のアルミ・ボンディング・パッド部５に水分による腐
食が顕しく現われることがある。すなわち、パッシベー
ション膜から露出したアルミ配線部は水分等に対するパ
ッシベーション膜の保護作用が及ばず、極めて腐食しや
すいという顕著な事実がある。This passivation film 4 is applied to protect the thin aluminum wiring from moisture, but since the passivation film on the wire bonding pad portion 5 is open, it is difficult to perform moisture resistance tests, especially PCT (pressure cutter) tests.・When performing a test), corrosion due to moisture may clearly appear on the aluminum bonding pad portion 5 directly under this opening, which lacks a protective film. That is, there is a remarkable fact that the aluminum wiring portion exposed from the passivation film is not protected by the passivation film against moisture and the like, and is therefore extremely susceptible to corrosion.
本発明の目的は、上記の情況に鑑み、耐湿性高きアルミ
・ポンディングパッド部を備えた半導体集積回路装置を
提供することである。SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit device having an aluminum bonding pad portion with high moisture resistance.
本発明によれば、半導体集積回路装置は、−導電型の半
導体基板と、前記半導体基板上に形成されるフィールド
絶縁膜と、前記フィールド絶縁膜の開口部に設けられ前
記半導体基板上の半導体素子と接続されるアルミ電極と
、前記アルミ電極を含むフィールド絶縁膜上のアルミ配
線を被覆するパッシベーション膜と、前記パッシベーシ
ョン膜上に開口される前記アルミ電極のアルミ・ボンデ
ィング・パッド部と、前記アルミ・ボンディング・パッ
ド部上を被覆する金被覆層とを含んで構成される。According to the present invention, a semiconductor integrated circuit device includes a - conductivity type semiconductor substrate, a field insulating film formed on the semiconductor substrate, and a semiconductor element provided in an opening of the field insulating film on the semiconductor substrate. an aluminum electrode connected to the aluminum electrode, a passivation film covering the aluminum wiring on the field insulating film including the aluminum electrode, an aluminum bonding pad portion of the aluminum electrode opened on the passivation film, and an aluminum bonding pad portion of the aluminum electrode opened on the passivation film; and a gold coating layer covering the bonding pad portion.
以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.
第１図は本発明の一実施例を示す半導体集積回路装置の
アルミ・ボンディング・パッド部近傍の断面図である。FIG. 1 is a sectional view of the vicinity of an aluminum bonding pad portion of a semiconductor integrated circuit device showing one embodiment of the present invention.
本実施例によれば、本発明の半導体集積回路装置は、半
導体基板１と、基板１上に形成されたフィールド絶縁膜
２と、フィールド絶縁膜２の開口部に設けられ基板１上
に形成された半導体素子（図示しない）と接続されるア
ルミ電極３と、アルミ電極３を含むアルミ配線全面を被
覆するパッシベーション膜４と、パッシベーション膜４
に開口されたアルミ電極３のアルミ・ボンディング・パ
ッド部５と、このアルミ・ボンディング・パッド部５上
を被覆する薄い金被覆層６とを含む、ここで、金被覆層
６は無電界メツキ法または蒸着法で基板全面を金被覆し
、ボンディング・パッド部５上のみをマスクして周辺部
からこの金波Ｗｉ層を選択的にエツチング除去する方法
、或いは電界メツキ法を用いてパッシベーション膜４の
開口部のみに直接金メツキを施す方法で極めて容易に形
成することが可能である。特に後者の方法によるとワイ
ヤ・ボンディング後でも実施できるので利点は大きい。According to this embodiment, the semiconductor integrated circuit device of the present invention includes a semiconductor substrate 1, a field insulating film 2 formed on the substrate 1, and a field insulating film 2 provided in an opening of the field insulating film 2 and formed on the substrate 1. an aluminum electrode 3 connected to a semiconductor element (not shown); a passivation film 4 covering the entire surface of the aluminum wiring including the aluminum electrode 3;
The aluminum bonding pad portion 5 of the aluminum electrode 3 has an opening, and the thin gold coating layer 6 covers the aluminum bonding pad portion 5. Here, the gold coating layer 6 is formed by electroless plating. Alternatively, the entire surface of the substrate is coated with gold using a vapor deposition method, and only the top of the bonding pad portion 5 is masked, and the gold wave Wi layer is selectively etched away from the periphery, or the opening in the passivation film 4 is formed using an electroplating method. It can be formed extremely easily by applying gold plating directly to only the parts. Particularly, the latter method has a great advantage because it can be carried out even after wire bonding.
以上はアルミ・ボンディング・パッド部上を金被覆する
場合を説明したが、金被覆層６とパッド部５との間に遷
移金属を介在させ、金アルミの合金形成を防いでもよい
。Although the case where the aluminum bonding pad portion is coated with gold has been described above, a transition metal may be interposed between the gold coating layer 6 and the pad portion 5 to prevent the formation of a gold-aluminum alloy.
以上詳細に説明したように、本発明によれば、アルミ・
ボンディング・パッド部上は化学的に安定し且つボンデ
ィングし易い性質をもつ金屑で被覆されるので、半導体
集積回路装置は、従来構造と比べ、より高い耐湿性を得
ることができる。また、半導体装置として封止される前
のウェハーおよびペレット段階において既に安定な状態
を維持できるので、信頼性の向上に顕著なる効果を奏し
得る。As explained in detail above, according to the present invention, aluminum
Since the bonding pad portion is coated with metal chips that are chemically stable and easy to bond, the semiconductor integrated circuit device can have higher moisture resistance than conventional structures. Moreover, since a stable state can be maintained already in the wafer and pellet stages before being sealed as a semiconductor device, a remarkable effect can be achieved in improving reliability.
第１図は本発明の一実施例を示す半導体集積回路装置の
アルミ・ボンディング・パッド部近傍の断面図、第２図
は従来半導体集積回路装置のアルミ・ボンディング・パ
ッド部近傍の断面図である。
１・・・半導体基板、２・・・フィールド絶縁膜、３・
・・アルミ電極、４・・・パッシベーション膜、５・・
・アルミ・ボンディング・パッド部、６・・・金被覆。
代理人 弁理士 内 原 晋FIG. 1 is a sectional view of the vicinity of an aluminum bonding pad portion of a semiconductor integrated circuit device showing an embodiment of the present invention, and FIG. 2 is a sectional view of the vicinity of an aluminum bonding pad portion of a conventional semiconductor integrated circuit device. . DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Field insulating film, 3...
...Aluminum electrode, 4...Passivation film, 5...
・Aluminum bonding pad part, 6...Gold coating. Agent Patent Attorney Susumu Uchihara
Claims (1)
るフィールド絶縁膜と、前記フィールド絶縁膜の開口部
に設けられ前記半導体基板上の半導体素子と接続される
アルミ電極と、前記アルミ電極を含むフィールド絶縁膜
上のアルミ配線を被覆するパッシベーション膜と、前記
パッシベーション膜上に開口される前記アルミ電極のア
ルミ・ボンディング・パッド部と、前記アルミ・ボンデ
ィング・パッド部上を被覆する金被覆層とを含むことを
特徴とする半導体集積回路装置。a semiconductor substrate of one conductivity type; a field insulating film formed on the semiconductor substrate; an aluminum electrode provided in an opening of the field insulating film and connected to a semiconductor element on the semiconductor substrate; a passivation film covering aluminum wiring on a field insulating film, an aluminum bonding pad portion of the aluminum electrode opened on the passivation film, and a gold coating layer covering the aluminum bonding pad portion. A semiconductor integrated circuit device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24503588A JPH0290637A (en) | 1988-09-28 | 1988-09-28 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24503588A JPH0290637A (en) | 1988-09-28 | 1988-09-28 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0290637A true JPH0290637A (en) | 1990-03-30 |
Family
ID=17127615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24503588A Pending JPH0290637A (en) | 1988-09-28 | 1988-09-28 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0290637A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000228486A (en) * | 1999-02-08 | 2000-08-15 | Rohm Co Ltd | Semiconductor chip and semiconductor device of chip-on- chip structure |
| US6657309B1 (en) | 1999-02-08 | 2003-12-02 | Rohm Co., Ltd. | Semiconductor chip and semiconductor device of chip-on-chip structure |
| JP2009021277A (en) * | 2007-07-10 | 2009-01-29 | Murata Mfg Co Ltd | Semiconductor element and method of manufacturing semiconductor element |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5314557A (en) * | 1976-07-26 | 1978-02-09 | Hitachi Ltd | Electrode structure in semiconductor device |
-
1988
- 1988-09-28 JP JP24503588A patent/JPH0290637A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5314557A (en) * | 1976-07-26 | 1978-02-09 | Hitachi Ltd | Electrode structure in semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000228486A (en) * | 1999-02-08 | 2000-08-15 | Rohm Co Ltd | Semiconductor chip and semiconductor device of chip-on- chip structure |
| US6657309B1 (en) | 1999-02-08 | 2003-12-02 | Rohm Co., Ltd. | Semiconductor chip and semiconductor device of chip-on-chip structure |
| JP2009021277A (en) * | 2007-07-10 | 2009-01-29 | Murata Mfg Co Ltd | Semiconductor element and method of manufacturing semiconductor element |
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