JPS6035552A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6035552A
JPS6035552A JP58143866A JP14386683A JPS6035552A JP S6035552 A JPS6035552 A JP S6035552A JP 58143866 A JP58143866 A JP 58143866A JP 14386683 A JP14386683 A JP 14386683A JP S6035552 A JPS6035552 A JP S6035552A
Authority
JP
Japan
Prior art keywords
layer
pellet
tin
lead frame
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58143866A
Other languages
Japanese (ja)
Inventor
Akira Suzuki
明 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58143866A priority Critical patent/JPS6035552A/en
Publication of JPS6035552A publication Critical patent/JPS6035552A/en
Pending legal-status Critical Current

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Classifications

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the humidity resistance of bonding pads with a low cost by covering the surfaces of the bonding pads of a pellet with Sn or an alloy thereof. CONSTITUTION:The semiconductor pellet 3 consisting of Si and etc. is fixed on a tub 2 of a lead frame 1 and bonding pads of the pellet 3 are bonded to inner leads 5 of the lead frame 1 with wires 4 consisting of gold and etc. and these are connected electrically. Also, the pellet 3 and the wires 4 are sealed in a package 6 by resin-molding. The pellet 3 is formed, for example, by forming a chromium layer 10 and a Cu (or Ni) layer 11 on an opened window of a surface protection layer 9 consisting of P-SiO or P-SiN which is formed on an Al wiring 8 on an Si substrate 7 and further forming a layer 12 of Sn or an alloy thereof on said layer 11. The wires 4 are bonded on the Sn layer 12.

Description

【発明の詳細な説明】 ［技術分野］ 本発明は半導体装置、さらには、樹脂封止型の半導体装
置に適用して効果のある技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is effective when applied to semiconductor devices, and more particularly to resin-sealed semiconductor devices.

［背景技術］ 樹脂封止型の半導体装置においては、リードフレームの
ペレット取り付は部（タブ）」二に半導体ペレットをボ
ンディングし、そのペレットのアルミニウム（Ａｔ）電
極を金（Ａｕ）等のワイヤでリードフレームのインナー
リード部と電気的に接続することが考えられる。また、
ペレソ１−の表面部は内部配線、特にアルミニウム配線
を腐食から保護するため、ファイナルバッジベージラン
としてたとえばＰＳＧ、Ｐ−３ｉＮ、Ｐ−５ｉ０２等の
表面像ｇｆｆ　Ｎを設けている。しかし、ペレットの表
面部にはワイヤボンディング用の電極を形成しなければ
ならず、しかも樹脂封止型半導体装置ではリードフレー
ムと樹脂の間等から水分等が侵入し易いので、このアル
ミニウム電極部を如何にして腐食から保護するかが重要
な課題となる。[Background Art] In a resin-sealed semiconductor device, the pellet is attached to a lead frame by bonding the semiconductor pellet to a tab, and then connecting the aluminum (At) electrode of the pellet to a wire made of gold (Au) or the like. It is conceivable to electrically connect it to the inner lead part of the lead frame. Also,
In order to protect the internal wiring, particularly the aluminum wiring, from corrosion, the surface of the pereso 1- is provided with a surface image gffN such as PSG, P-3iN, P-5i02, etc. as a final badge run. However, electrodes for wire bonding must be formed on the surface of the pellet, and in resin-sealed semiconductor devices, moisture can easily enter between the lead frame and the resin. An important issue is how to protect it from corrosion.

そこで、ポンディングパッド部のアルミニウム電極の耐
湿性向上のため、アルミニウム電極の表面に金の被膜を
形成することが本出願人によって提案されている（特開
昭５４−１２８２８０号）。Therefore, in order to improve the moisture resistance of the aluminum electrode of the bonding pad portion, the present applicant has proposed forming a gold coating on the surface of the aluminum electrode (Japanese Patent Laid-Open No. 128280/1983).

この従来構造は耐湿性の向上による高信頼性を得るとい
う所期の目的を達成することができるものであることが
確認されているが、金被膜を使用しているためコストが
高くなるという問題がある。It has been confirmed that this conventional structure can achieve the desired purpose of obtaining high reliability through improved moisture resistance, but it has the problem of high cost due to the use of a gold coating. There is.

さらにまた、素子のボンディングバンドからのびるワイ
ヤを受け止めるリードフレームのインナーリード部やタ
ブに接着性を向上させるため同様に金や銀等の貴金属の
めっきをすることも考えられるが、やはりコストの上昇
をもたらすという問題がある。Furthermore, it is also possible to similarly plate the inner leads and tabs of the lead frame that receive the wires extending from the bonding band of the element with precious metals such as gold or silver to improve adhesion, but this would also increase costs. There is a problem of bringing

［発明の目的］ 本発明の目的は、低いコストでポンディングパッドの耐
湿性を向上させることのできる半導体装置を提供するこ
とにある。[Object of the Invention] An object of the present invention is to provide a semiconductor device that can improve the moisture resistance of a bonding pad at low cost.

本発明の他の目的は、リードフレームのコスト低減を実
現する半導体装置を提供することにある。Another object of the present invention is to provide a semiconductor device that achieves cost reduction of lead frames.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

［発明の概要］ 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

すなわち、ペレットのボンディングバンドの表面を安価
な錫またはその合金で覆うことにより前記目的を達成す
るものである。That is, the above object is achieved by covering the surface of the bonding band of the pellet with inexpensive tin or an alloy thereof.

また、リードフレームの少なくともワイヤボンディング
領域を安価な錫またはその合金で覆うことにより前記目
的を達成するものである。Further, the above object is achieved by covering at least the wire bonding area of the lead frame with inexpensive tin or an alloy thereof.

［実施例１］ 第１図は本発明の一実施例による半導体装置の断面図、
第２図はその要部の拡大部分断面図である。[Example 1] FIG. 1 is a cross-sectional view of a semiconductor device according to an example of the present invention,
FIG. 2 is an enlarged partial sectional view of the main part.

この実施例１において、リードフレームｌのタブ２上に
はシリコン（Ｓｔ）等の半導体ペレット３が取り付けら
れている。このペレット３のポンディングパッドは金等
のワイヤ４により、リードフレーム１のインナーリード
部５とボンディングされ、電気的に接続されている。In this embodiment 1, a semiconductor pellet 3 such as silicon (St) is attached on a tab 2 of a lead frame l. The bonding pad of the pellet 3 is bonded and electrically connected to the inner lead portion 5 of the lead frame 1 by a wire 4 made of gold or the like.

また、前記ペレット３、ワイヤ４等は樹脂のモールドに
よりパッケージ６の中に封止されている前記ペレット３
のポンディングパッドは第２図に示すように、シリコン
基板７−Ｌのアルミニウム配線８の上に形成したＰ−３
ｉＯまたはＰ−ＳｉＮ等の表面保護Ｍ９の窓開部にクロ
ームＩ’Ｗ１０および銅（またはニッケル）Ｗｌｌｌを
形成し、さらにその上に錫（Ｓ　ｎ）または錫の合金よ
りなる層１２（以下、単に錫層と称する。）を形成した
ものである。Further, the pellet 3, wire 4, etc. are sealed in a package 6 by resin molding.
As shown in FIG.
A layer 12 (hereinafter referred to as (simply referred to as a tin layer).

したがって、本実施例では、アルミニウム配線８の電極
部すなわちボンディングバンド部の最上層は錫層１２で
覆われていることになり、ワイヤ４は、この錫層１２の
上にボンディングされる。Therefore, in this embodiment, the uppermost layer of the electrode section, that is, the bonding band section of the aluminum wiring 8 is covered with the tin layer 12, and the wire 4 is bonded onto this tin layer 12.

それにより、ワイヤ４と錫層１２はそれぞれの材質であ
る金−錫（Ａｕ−３ｎ）の共晶により確実に接続される
。Thereby, the wire 4 and the tin layer 12 are reliably connected by their respective materials, eutectic gold-tin (Au-3n).

前記錫層１２はめっき、蒸着、スパツク等の方法で形成
し、その後に化学的処理等で規定の形状にパターニング
することにより作られる。The tin layer 12 is formed by a method such as plating, vapor deposition, or spatter, and then patterned into a prescribed shape by chemical treatment or the like.

錫層１２の錫材料はアルミニウムよりもイオン傾向が小
さいので、外部から侵入して来た水分等の腐食性物質に
対して抗力を有し、ポンディングパッドの耐湿性、耐食
性を大ｒｐに向」二させることができる。しかも、錫は
金や銀の如き貴金属よりもはるかに安価であり、コスト
の大中な低減が図られる。Since the tin material of the tin layer 12 has a smaller ionic tendency than aluminum, it has resistance against corrosive substances such as moisture that have entered from the outside, and improves the moisture resistance and corrosion resistance of the bonding pad to a large RP. ” You can make it two. In addition, tin is much cheaper than precious metals such as gold and silver, resulting in a significant cost reduction.

［実施例２コ 第３図は本発明の他の実施例である半導体装置の拡大部
分断面図である。[Embodiment 2] FIG. 3 is an enlarged partial sectional view of a semiconductor device according to another embodiment of the present invention.

この実施例２では、リードフレーム１のタブ２のペレッ
ト取り付は面およびインナーリード部５のワイヤボンデ
ィング面に錫または錫の合金よりなる錫層１３をめっき
等で形成した点が実施例１と異なる。Embodiment 2 differs from Embodiment 1 in that a tin layer 13 made of tin or a tin alloy is formed on the surface of the tab 2 of the lead frame 1 for attaching the pellet and on the wire bonding surface of the inner lead portion 5 by plating or the like. different.

この錫ＪＦｔ１３を設けたことにより、ペレット３の導
電性接着材によるボンディングおよびワイヤ４の熱圧着
ボンディングの接着性能が改善される上に、金や銀の如
き貴金属と比較して非常に安価に半導体装置を形成でき
る。By providing this tin JFt13, the adhesive performance of the conductive adhesive bonding of the pellet 3 and the thermocompression bonding of the wire 4 is improved, and it can be used for semiconductors at a very low cost compared to precious metals such as gold and silver. Can form a device.

したがって、本実施例では、ボンディング性能およびボ
ンディングバンドの耐食性の向上に加えて、コストの低
減も相乗的に奏せられる。Therefore, in this example, in addition to improving the bonding performance and the corrosion resistance of the bonding band, it is also possible to reduce the cost synergistically.

［効果］ （１）、ペレットのワイヤボンディング用のポンディン
グパッドの表面に錫または錫の合金の屑を形成したこと
により、低いコストで高い耐湿性を得ることができる。[Effects] (1) By forming tin or tin alloy scraps on the surface of the bonding pad for pellet wire bonding, high moisture resistance can be obtained at low cost.

（２）、リードフレームの少なくともワイヤボンディン
グ領域の上に錫または錫の合金の層を形成したことによ
り、低いコストで良好なボンディング性能を得ることが
できる。(2) By forming a layer of tin or a tin alloy on at least the wire bonding region of the lead frame, good bonding performance can be obtained at low cost.

（３）、前記（１）と（２）の組合せにより、耐湿性お
よびボンディング性能が良好な半導体装置を低コストで
得ることができる。(3) By combining (1) and (2) above, a semiconductor device with good moisture resistance and bonding performance can be obtained at low cost.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸説しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the Examples and can be modified in various ways without departing from the gist of the invention. Not even.

たとえば、錫の合金の種類、あるいはポンディングパッ
ドの錫層の下側の中間層の構造等は前記実施例に限定さ
れるものではない。For example, the type of tin alloy, the structure of the intermediate layer below the tin layer of the bonding pad, etc. are not limited to the above embodiments.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例による半導体装置の断面図、 第２図はその要部の拡大部分断面図、 第３図は本発明の他の実施例の拡大部分断面図である。 １・・・リードフレーム、２・・・クプ、３・・・ペレ
ット、４・・・ワイヤ、５・・・インナーリード部、６
・・・パンケージ、７・・・シリコン基板、８・・・ア
ルミニウム配線、９・・・表面保護層、１０・・・クロ
ーム層、１１・・・　銅（またはニッケル）層、１２．
１３・・・錫または錫の合金の層。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged partial sectional view of a main part thereof, and FIG. 3 is an enlarged partial sectional view of another embodiment of the invention. DESCRIPTION OF SYMBOLS 1... Lead frame, 2... Cup, 3... Pellet, 4... Wire, 5... Inner lead part, 6
Pan cage, 7 Silicon substrate, 8 Aluminum wiring, 9 Surface protective layer, 10 Chrome layer, 11 Copper (or nickel) layer, 12.
13...Tin or tin alloy layer.

Claims (1)

【特許請求の範囲】 １、樹脂封止型の半導体装置において、ペレットのワイ
ヤボンディング用のポンディングパッドの表面に錫また
は錫の合金の層を形成したことを特徴とする半導体装置
。 ２、樹脂封止型の半導体装置において、リードフレーム
の少な（ともワイヤボンディング領域の上の一部に錫ま
たは錫の合金の眉を形成したことを特徴とする半導体装
置。 ３、リードフレーム上に取り付けたペレットのワイヤボ
ンディング用のポンディングパッドの表面に錫または錫
の合金の層を形成したことを特徴とする特許端２求の範
囲第２項記載の半導体装置。[Claims] 1. A resin-sealed semiconductor device, characterized in that a layer of tin or a tin alloy is formed on the surface of a bonding pad for wire bonding of a pellet. 2. A resin-sealed semiconductor device that has a small lead frame (in which a tin or tin alloy eyebrow is formed on a part of the wire bonding area. 3. A semiconductor device that has a small lead frame). 2. A semiconductor device according to claim 2, characterized in that a layer of tin or a tin alloy is formed on the surface of a bonding pad for wire bonding of the attached pellet.
JP58143866A 1983-08-08 1983-08-08 Semiconductor device Pending JPS6035552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58143866A JPS6035552A (en) 1983-08-08 1983-08-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58143866A JPS6035552A (en) 1983-08-08 1983-08-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6035552A true JPS6035552A (en) 1985-02-23

Family

ID=15348808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58143866A Pending JPS6035552A (en) 1983-08-08 1983-08-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6035552A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5965943A (en) * 1997-10-01 1999-10-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with bonding pad electrode
WO2000057472A1 (en) * 1999-03-24 2000-09-28 Infineon Technologies Ag Method of connecting a connecting wire to a contact of an integrated circuit
JP2002373910A (en) * 2000-09-12 2002-12-26 Rohm Co Ltd Semiconductor device
ITTO20120374A1 (en) * 2012-04-27 2013-10-28 St Microelectronics Srl SEMICONDUCTOR STRUCTURE WITH LOW TEMPERATURE CONDUCTIVE REGIONS OF FUSION AND METHOD TO REPAIR A SEMICONDUCTOR STRUCTURE
JP2018067680A (en) * 2016-10-21 2018-04-26 国立研究開発法人産業技術総合研究所 Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5965943A (en) * 1997-10-01 1999-10-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with bonding pad electrode
WO2000057472A1 (en) * 1999-03-24 2000-09-28 Infineon Technologies Ag Method of connecting a connecting wire to a contact of an integrated circuit
JP2002373910A (en) * 2000-09-12 2002-12-26 Rohm Co Ltd Semiconductor device
JP4754763B2 (en) * 2000-09-12 2011-08-24 ローム株式会社 Semiconductor device
ITTO20120374A1 (en) * 2012-04-27 2013-10-28 St Microelectronics Srl SEMICONDUCTOR STRUCTURE WITH LOW TEMPERATURE CONDUCTIVE REGIONS OF FUSION AND METHOD TO REPAIR A SEMICONDUCTOR STRUCTURE
US9318313B2 (en) 2012-04-27 2016-04-19 Stmicroelectronics S.R.L. Semiconductor structure with low-melting-temperature conductive regions, and method of repairing a semiconductor structure
JP2018067680A (en) * 2016-10-21 2018-04-26 国立研究開発法人産業技術総合研究所 Semiconductor device

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