JPS61141157A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS61141157A JPS61141157A JP59263448A JP26344884A JPS61141157A JP S61141157 A JPS61141157 A JP S61141157A JP 59263448 A JP59263448 A JP 59263448A JP 26344884 A JP26344884 A JP 26344884A JP S61141157 A JPS61141157 A JP S61141157A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- bump electrode
- bump
- metallic
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
本発明は、半導体ウェハに外部基板端子あるいはリード
&I端子と直接接続可能な突起状のバンプ電極を有する
半導体素子の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor element having protruding bump electrodes that can be directly connected to external substrate terminals or lead & I terminals on a semiconductor wafer.
半導体素子のバンプ電極の形成には、従来例えば第2図
a ”w eに示すような工程による方法がとられてい
た。すなわち、シリコンウェハ1の上に酸化シリコン膜
3を被着し、不純物拡散領域2の上に開口部を設けてそ
の領域に接触する^l配線膜4を蒸着した後、表面保護
用の窒化シリコン膜5を被着し、バンプ形成N域に開口
部6を開ける(a図)0次に丁1のような密着金属膜?
、Goのようなバリア金属膜8を電子ビーム蒸着法等で
形成し、ホ゛トエッチング法で開口部10ををするホト
レジスト層9を設ける (b図)、つづいて電解めっき
法で^Uあるいは5%のpbを含む5n−Pb合金から
なるバンプ11を形成する cC図)0次に新しく塗布
したホトレジスト層12を加工してバンプ11の表面お
よび周辺部を覆うようにする (d図)、このレジスト
12をマスクとしてバリア金属膜8.密着金属膜7を連
続してエツチングし、最後にホトレジス)12をレジス
ト除去剤で除去する (図d)、しかしこのようなバン
プ電極形成方法では20#II〜50μの高さがあるバ
ンプ11の表面および周辺部を覆うホトレジスト12を
均一に塗布するのが困難で、バンプ11付近にはホトレ
ジストパターニング不良部13が生じやすく (図d)
、引きつづいて行なうバリア金属膜8.密着金属膜7の
エツチング時にこの不良部13から侵入した酸あるいは
水が残ってバンプ細り14.バンプ形状不良15等の不
具合が生じ(図e)、バンプ電極11の付着強度の低下
等、信鯨性に影響を与える虞があった。Conventionally, bump electrodes of semiconductor devices have been formed using a process such as that shown in FIG. After forming an opening above the diffusion region 2 and depositing a wiring film 4 in contact with the region, a silicon nitride film 5 for surface protection is deposited, and an opening 6 is opened in the bump formation region ( Figure a) Adhesive metal film like 0 and 1?
, a barrier metal film 8 such as Go is formed by electron beam evaporation or the like, a photoresist layer 9 is provided to form an opening 10 by photoetching (Figure b), and then ^U or 5% is deposited by electrolytic plating. Next, the newly applied photoresist layer 12 is processed to cover the surface and periphery of the bump 11 (Fig. d). Barrier metal film 8.12 is used as a mask. The adhesive metal film 7 is continuously etched, and finally the photoresist 12 is removed using a resist remover (Fig. d). However, in this bump electrode formation method, the bumps 11 with a height of 20#II to 50μ are removed. It is difficult to uniformly apply the photoresist 12 that covers the surface and surrounding areas, and photoresist patterning defects 13 tend to occur near the bumps 11 (Figure d).
, followed by barrier metal film 8. When etching the adhesive metal film 7, acid or water that entered from the defective portion 13 remains and the bump becomes thinner14. Problems such as a defective bump shape 15 occurred (Fig. e), and there was a risk that the adhesion strength of the bump electrode 11 would decrease, affecting reliability.
本発明は、上述の問題を解決し、バンプ電極およびその
下地金属を含めての形状不良の生じないような半導体素
子の製造方法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a semiconductor device that does not cause defective shapes of bump electrodes and their underlying metals.
本発明によれば、バンプ電極を下地金属層を覆うレジス
ト層の開口部に接してめっきにより形成後、バンプ電極
をマスクとしてプラズマエツチング法によりバンプ電極
直下以外のレジスト層を除去したのち、バンプ電極直下
以外の下地金属層をエツチングにより除去することによ
って上記の目的が達成できる。According to the present invention, after the bump electrode is formed by plating in contact with the opening of the resist layer covering the underlying metal layer, the resist layer other than directly under the bump electrode is removed by plasma etching using the bump electrode as a mask, and then the bump electrode is etched. The above object can be achieved by etching away the base metal layer other than those directly below.
第1図1〜eは本発明の一実施例の工程を示し、第2図
と共通の部分には同一の符号が付されている。第1図1
〜eに示す工程は第2図について説明した従来法の工程
と同じで、シリコンウェハ1の表面上の密着金属@7.
バリア金属膜8からなる下地金属層の上のホトレジスト
層9をマスクとして電解めっきにより下地金属層に開口
部10で接触するバンプ電極11を形成する。このあと
、本発明によって01プラズマエツチングによりホトレ
ジスト9のエツチングを行なうが、この際バンプ11が
マスクとなって第1図dに示すようにバンプ直下のレジ
スト層9が残存する。従って、例えば金バンプの際には
フォトレジスト塗布の必要な(、そのまま下地金属、す
なわちバリア金属l!I8#よび密着金属膜7のエツチ
ングを行なうことができ、バンプ直下の下地金属層はレ
ジスト層9によす保護されるため、第1図eに示すよう
に下地金属層は正常な形状に保たれる。レジスト9とし
てゴム系の材料を用いれば、例えばバンプ電極11を金
めつきにより形成し、すず被覆銅リード線端子とボンデ
ィングする際の450℃1秒間の温度に耐えるので、レ
ジストを除去しないでおくことができる。
【発明の効果]
本発明は、下地金属層上のホトレジストをマスクとして
めっきによりバンプ電極を形成後、バンプ電極をマスク
としたプラズマエツチングによりバンプ電極直下の部分
を残存させてそれ以外のレジストを除去することができ
るため、そのあとの下地金属層エツチング時にエツチン
グ液あるいは水の侵入によってバンプ直下の下地金属層
の形状が損なわれることがなく、バンプの配線金属に対
する付着強度が保持される。また下地金属層エツチング
のためのバンプ周辺部のレジストパターニングの必要が
なくなり、レジスト除去剤の使用もプラズマエツチング
により置き換えられるので下地金属層へのレジスト除去
剤の影響もなくなるなど、半導体素子の製造工程の合理
化、信幀性の向上に対して得られる効果は極めて大きい
。1 to 1e show the steps of an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. Figure 1 1
The steps shown in ~e are the same as the steps of the conventional method explained with reference to FIG.
Bump electrodes 11 are formed in contact with the base metal layer at openings 10 by electrolytic plating using the photoresist layer 9 on the base metal layer consisting of the barrier metal film 8 as a mask. Thereafter, the photoresist 9 is etched by 01 plasma etching according to the present invention, and at this time the bumps 11 serve as a mask, leaving the resist layer 9 directly under the bumps as shown in FIG. 1d. Therefore, for example, when forming a gold bump, it is possible to perform etching of the underlying metal, that is, the barrier metal l! 9, the underlying metal layer is maintained in its normal shape as shown in FIG. However, since it can withstand the temperature of 450°C for 1 second when bonding with a tin-coated copper lead wire terminal, the resist can be left unremoved. After forming a bump electrode by plating, plasma etching can be performed using the bump electrode as a mask, leaving the part directly under the bump electrode and removing the rest of the resist. The shape of the base metal layer directly under the bump is not damaged by water intrusion, and the adhesion strength of the bump to the wiring metal is maintained.Also, there is no need for resist patterning around the bump for etching the base metal layer. Since the use of a resist remover is replaced by plasma etching, the effect of the resist remover on the underlying metal layer is also eliminated, and the effects of streamlining the manufacturing process of semiconductor devices and improving reliability are extremely large.
第1図は本発明の一実施例におけるバンプ電極形成の工
程を順次示す要部断面図、第2図は従来のバンプ電極形
成の工程を順次示す要部断面図である。
1:シリコンウェハ、 2:不純物拡散領域、4:A!
配線、7:密着金属膜、8:バリア金属膜、9:ホトレ
ジスト層、lO:開口部、11:バンプ電極。
第1図
第2図FIG. 1 is a cross-sectional view of a main part sequentially showing the process of forming a bump electrode in an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a main part sequentially showing the process of forming a conventional bump electrode. 1: Silicon wafer, 2: Impurity diffusion region, 4: A!
Wiring, 7: Adhesive metal film, 8: Barrier metal film, 9: Photoresist layer, IO: Opening, 11: Bump electrode. Figure 1 Figure 2
Claims (1)
ンプ電極を有する半導体素子の製造方法であって、バン
プ電極を下地金属層を覆うレジスト層の開口部に接して
めっきにより形成後、バンプ電極をマスクとするプラズ
マエッチング法によりバンプ電極の直下以外のホトレジ
スト層を除去したのちバンプ電極直下以外の下地金属層
をエッチングにより除去することを特徴とする半導体素
子の製造方法。1) A method for manufacturing a semiconductor element having bump electrodes formed on a semiconductor wafer through a base metal layer, in which the bump electrodes are formed by plating in contact with openings in a resist layer covering the base metal layer, and then the bumps are formed on a semiconductor wafer through a base metal layer. 1. A method for manufacturing a semiconductor device, which comprises removing the photoresist layer except directly under the bump electrode by plasma etching using the electrode as a mask, and then removing the underlying metal layer except directly under the bump electrode by etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59263448A JPS61141157A (en) | 1984-12-13 | 1984-12-13 | Manufacture of semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59263448A JPS61141157A (en) | 1984-12-13 | 1984-12-13 | Manufacture of semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61141157A true JPS61141157A (en) | 1986-06-28 |
Family
ID=17389649
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59263448A Pending JPS61141157A (en) | 1984-12-13 | 1984-12-13 | Manufacture of semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61141157A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63161649A (en) * | 1986-12-25 | 1988-07-05 | Casio Comput Co Ltd | Manufacture of semiconductor device |
US5323535A (en) * | 1991-02-25 | 1994-06-28 | Canon Kabushiki Kaisha | Electrical connecting member and method of manufacturing the same |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5279664A (en) * | 1975-12-25 | 1977-07-04 | Mitsubishi Electric Corp | Forming method for electrodes of semiconductor devices |
JPS56100450A (en) * | 1980-01-11 | 1981-08-12 | Seiko Instr & Electronics Ltd | Manufacture of projected electrode of semiconductor device |
-
1984
- 1984-12-13 JP JP59263448A patent/JPS61141157A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5279664A (en) * | 1975-12-25 | 1977-07-04 | Mitsubishi Electric Corp | Forming method for electrodes of semiconductor devices |
JPS56100450A (en) * | 1980-01-11 | 1981-08-12 | Seiko Instr & Electronics Ltd | Manufacture of projected electrode of semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63161649A (en) * | 1986-12-25 | 1988-07-05 | Casio Comput Co Ltd | Manufacture of semiconductor device |
US5323535A (en) * | 1991-02-25 | 1994-06-28 | Canon Kabushiki Kaisha | Electrical connecting member and method of manufacturing the same |
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