JP3354716B2 - Method for manufacturing semiconductor integrated circuit device - Google Patents

Method for manufacturing semiconductor integrated circuit device

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Publication number
JP3354716B2
JP3354716B2 JP15734694A JP15734694A JP3354716B2 JP 3354716 B2 JP3354716 B2 JP 3354716B2 JP 15734694 A JP15734694 A JP 15734694A JP 15734694 A JP15734694 A JP 15734694A JP 3354716 B2 JP3354716 B2 JP 3354716B2
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JP
Japan
Prior art keywords
bonding
silicon
integrated circuit
circuit device
liquid material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP15734694A
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Japanese (ja)
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JPH0823007A (en
Inventor
睦実 佐々木
Original Assignee
日本プレシジョン・サーキッツ株式会社
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Priority to JP15734694A priority Critical patent/JP3354716B2/en
Publication of JPH0823007A publication Critical patent/JPH0823007A/en
Application granted granted Critical
Publication of JP3354716B2 publication Critical patent/JP3354716B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、半導体集積回路装置の
製造方法に関するものである。The present invention relates to a method of <br/> manufacturing a semiconductor integrated circuit equipment.

【０００２】[0002]

【従来の技術】従来、半導体チップ表面と封止パッケー
ジのモールド材との間の応力緩衝膜としてシリコン系液
材を介在させるものがあった。このようなものでは、図
４に示したように半導体チップ４１の中央にノズル４２
からシリコン系液材を滴下して形成していた。2. Description of the Related Art Heretofore, there has been a device in which a silicon-based liquid material is interposed as a stress buffer film between a semiconductor chip surface and a molding material of a sealing package. In such a case, as shown in FIG.
From the silicon-based liquid material.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、上記の
ものではシリコン系液材をチップの中央部分に滴下して
形成するので、シリコン系液材が全てのボンディングパ
ッド部分に十分いきわたらなかった。よって、ボンディ
ングパットのうちシリコン系液材で覆われていない部分
が水分の侵入によって腐食してしまい、半導体集積回路
装置の信頼性が低下してしまうという問題点を有してい
た。However, in the above method, since the silicon-based liquid material is formed by dropping the silicon-based liquid material on the central portion of the chip, the silicon-based liquid material does not sufficiently reach all the bonding pad portions. Therefore, there is a problem that a portion of the bonding pad that is not covered with the silicon-based liquid material is corroded by the invasion of moisture, thereby lowering the reliability of the semiconductor integrated circuit device.

【０００４】本願の発明の目的は、信頼性の向上が可能
な半導体集積回路装置の製造方法を提供することであ
る。An object of the present invention is to improve reliability.
Such is to provide a method of manufacturing a semi-conductor integrated circuit device.

【０００５】[0005]

【課題を解決するための手段】本願の半導体集積回路装
置の製造方法に係る発明は、上記ボンディングワイヤの
頂点部分にシリコン系液材を滴下することにより、上記
ボンディングパッドおよび上記ボンディングワイヤの上
記ボンディングパッドとの接続部をシリコン系被膜で全
て被覆するものである。Means for Solving the Problems] According to the manufacturing method of the semi-conductor integrated circuit device of the present invention, by dropping the silicon liquid material to the apex portion of the bonding wire, the bonding pad and the bonding wire of the The connection with the bonding pad is entirely covered with a silicon-based film.

【０００６】本願の半導体集積回路装置の製造方法に係
る発明は、上記のボンディングワイヤの頂点部分の配列
に応じた形状の部材から、上記ボンディングワイヤの頂
点部分にシリコン系液材を滴下することが望ましい。According to the invention relating to a method of manufacturing a semiconductor integrated circuit device of the present invention, a silicon-based liquid material is dropped onto a top portion of the bonding wire from a member having a shape corresponding to the arrangement of the top portion of the bonding wire. desirable.

【０００７】[0007]

【実施例】以下、本願の半導体集積回路装置の製造方法
に係る発明を図面に示す実施例に基づいて説明する。BRIEF DESCRIPTION based on examples illustrating the invention according to the manufacturing method of the semi-conductor integrated circuit device of the present application to the drawings.

【０００８】図１において、１は半導体集積回路のチッ
プで、チップ１上に設けてあるボンディングパッド２〜
２にボンディングワイヤ３〜３が接続してある。Ａ，Ｂ
は、対向するボンディングワイヤ３〜３の頂点分部の距
離をそれぞれ示している。４〜４はリードで、それぞれ
ボンディングワイヤ３〜３と接続している。５はノズル
で、各ボンディングワイヤ３〜３の頂点部分にＪＣＲコ
ートからなるシリコン系液材を滴下する。図２は、ノズ
ル５の注入口５ａの形状を示しており、図中Ａ，Ｂの長
さはそれぞれ図１のＡ，Ｂの長さに対応している。すな
わち、ノズル５の注入口５ａは、ボンディングワイヤ３
〜３の頂点部分の配列に応じた形状となっている。よっ
て、注入口５ａから滴下されるシリコン系液材は、各ボ
ンディングワイヤ３〜３の頂点部分に滴下される。この
滴下されたシリコン系液材はそれぞれのボンディングワ
イヤ３〜３を被覆しながらボンディングパッド２〜２に
達して、ボンディングパッド２〜２を被覆する。In FIG. 1, reference numeral 1 denotes a semiconductor integrated circuit chip, and bonding pads 2 to 2 provided on the chip 1 are provided.
2, bonding wires 3 to 3 are connected. A, B
Indicates the distance between the vertices of the bonding wires 3 to 3 facing each other. Reference numerals 4 to 4 are leads connected to the bonding wires 3 to 3, respectively. Reference numeral 5 denotes a nozzle for dropping a silicon-based liquid material made of a JCR coat on the apexes of the bonding wires 3 to 3. FIG. 2 shows the shape of the injection port 5a of the nozzle 5, and the lengths of A and B in the figure correspond to the lengths of A and B in FIG. 1, respectively. That is, the injection port 5a of the nozzle 5 is
The shape is in accordance with the arrangement of the apexes of ~ 3. Therefore, the silicon-based liquid material dropped from the injection port 5a is dropped on the apex portion of each of the bonding wires 3 to 3. The dropped silicon-based liquid material reaches the bonding pads 2-2 while covering the respective bonding wires 3-3, and covers the bonding pads 2-2.

【０００９】よって、図３に示したように、ボンディン
グワイヤ３〜３の頂点部分からボンディングパッド２〜
２との接続部までの部分およびボンディングパッド２〜
２がシリコン系被膜６で全て被覆される。同図は図１の
Ｃ−Ｃ線断面のボンディングバッド２が形成してある部
分の拡大図で、同図において、７はシリコン基板、８は
層間絶縁層、９は保護膜である。なお、図１と同一番号
のものは、同一のものとする。Therefore, as shown in FIG. 3, the bonding pads 2 to 3 extend from the tops of the bonding wires 3 to 3.
2 and bonding pad 2
2 is entirely covered with the silicon-based coating 6. FIG. 2 is an enlarged view of a portion of the cross section taken along line CC of FIG. 1 where the bonding pad 2 is formed. In FIG. 1, reference numeral 7 denotes a silicon substrate, 8 denotes an interlayer insulating layer, and 9 denotes a protective film. The components having the same numbers as those in FIG. 1 are the same.

【００１０】このように、ボンディングワイヤ３〜３の
頂点部分にシリコン系液材を滴下するので、ボンディン
グパッド２〜２およびボンディングワイヤ３〜３の頂点
部分からボンディングパッド２〜２との接続部までの部
分がシリコン系被膜６によって被覆され、水分の侵入に
よるボンディングパッド２〜２の腐食を解消でき、半導
体集積回路装置の信頼性が格段に向上する。As described above, since the silicon-based liquid material is dripped onto the apexes of the bonding wires 3 to 3, the bonding pads 2 to 2 and the connection from the apex of the bonding wires 3 to the connection with the bonding pads 2 to 2 are formed. Is covered with the silicon-based coating 6, the corrosion of the bonding pads 2 and 2 due to the invasion of moisture can be eliminated, and the reliability of the semiconductor integrated circuit device is remarkably improved.

【００１１】なお、リード４〜４と接続している側のボ
ンディングワイヤ３〜３に流れるシリコン系液材も、ボ
ンディングワイヤ３〜３を被覆しながらリード４〜４に
達する。The silicon-based liquid material flowing through the bonding wires 3 to 3 connected to the leads 4 to 4 also reaches the leads 4 to 4 while covering the bonding wires 3 to 3.

【００１２】シリコン系液材６を滴下するノズル５の注
入口５ａの形状がボンディングワイヤ３〜３の頂点部分
の配列に応じた形状なので、シリコン系液材６を滴下す
る際にノズルとボンディングワイヤ３〜３の頂点との位
置合わせが一度で済み製造工程の簡略化が図れるととも
に、確実に全てのボンディンクワイヤ３〜３の頂点部分
にシリコン系液材６を滴下できる。Since the shape of the injection port 5a of the nozzle 5 for dropping the silicon-based liquid material 6 is in accordance with the arrangement of the apexes of the bonding wires 3 to 3, the nozzle and the bonding wire are used when the silicon-based liquid material 6 is dropped. The alignment with the vertices of 3 to 3 can be performed only once and the manufacturing process can be simplified, and the silicon-based liquid material 6 can be surely dropped onto the vertices of all the bonding wires 3 to 3.

【００１３】なお、シリコン系液材６を滴下するノズル
５の形状は、図２に示したものに限らず、ボンディング
ワイヤ３〜３の頂点部分の配列に応じて、適宜変更可能
である。The shape of the nozzle 5 for dropping the silicon-based liquid material 6 is not limited to that shown in FIG. 2, but can be changed as appropriate in accordance with the arrangement of the apexes of the bonding wires 3 to 3.

【００１４】[0014]

【発明の効果】本願の半導体集積回路装置の製造方法に
よれば、ボンディングワイヤの頂点部分にシリコン系液
材を滴下することにより、ボンディングパッドおよびボ
ンディングワイヤのボンディングパッドとの接続部をシ
リコン系被膜で全て被覆できるので、信頼性の高い半導
体集積回路装置を製造できる。According to the method of manufacturing a semi-conductor integrated circuit device of the present, according to the present invention, by dropping the silicon liquid material to the apex portion of the bonding wire, silicon-based connection portion between the bonding pad and the bonding wire bonding pad Since the whole can be covered with the film, a highly reliable semiconductor integrated circuit device can be manufactured.

【００１５】さらに、ボンディングワイヤの頂点部分の
配列に応じた形状の部材から、ボンディングワイヤの頂
点部分にシリコン系液材を滴下することにより、シリコ
ン系液材を滴下する際にシリコン系液材を滴下する部材
とボンディングワイヤとの位置合わせが一度で済むので
製造工程の簡略化が図れるとともに、確実に全てのボン
ディンクワイヤの頂点部分にシリコン系液材を滴下でき
る。Further, by dropping a silicon-based liquid material onto a top portion of the bonding wire from a member having a shape corresponding to the arrangement of the top portions of the bonding wire, the silicon-based liquid material is dropped when the silicon-based liquid material is dropped. Since the positioning of the member to be dropped and the bonding wire can be performed only once, the manufacturing process can be simplified, and the silicon-based liquid material can be reliably dropped on the apexes of all the bonding wires.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の製造工程の一実施例を示した説明図。FIG. 1 is an explanatory view showing one embodiment of a manufacturing process of the present invention.

【図２】図１の要部詳細図。FIG. 2 is a detailed view of a main part of FIG. 1;

【図３】図１の要部断面図。FIG. 3 is a sectional view of a main part of FIG. 1;

【図４】従来の半導体集積回路装置の製造工程を示した
説明図。FIG. 4 is an explanatory view showing a manufacturing process of a conventional semiconductor integrated circuit device.

【符号の説明】[Explanation of symbols]

２ ボンディングパット ３ ボンディングワイヤ ５ 部材 ６ シリコン系被膜，シリコン系液材 2 Bonding pad 3 Bonding wire 5 Member 6 Silicon coating, silicon liquid material

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭60−85548（ＪＰ，Ａ) 特開 平４−56840（ＪＰ，Ａ) 特開 平５−121474（ＪＰ，Ａ) 特開 平５−152365（ＪＰ，Ａ) 特開 平６−333970（ＪＰ，Ａ) 特開 平７−86324（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 H01L 21/56 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-60-85548 (JP, A) JP-A-4-56840 (JP, A) JP-A-5-121474 (JP, A) JP-A-5-121474 152365 (JP, A) JP-A-6-333970 (JP, A) JP-A-7-86324 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21/60 H01L 21 / 56

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 ボンディングパッドおよびこのボンディ
ングパッドに接続されるボンディングワイヤを有する半
導体集積回路装置の製造方法において、上記ボンディングワイヤの頂点部分にシリコン系液材を
滴下することにより、 上記ボンディングパッドおよび上
記ボンディングワイヤの上記ボンディングパッドとの接
続部をシリコン系被膜で全て被覆する工程を有すること
を特徴とする半導体集積回路装置の製造方法。1. A method for manufacturing a semiconductor integrated circuit device having a bonding pad and a bonding wire connected to the bonding pad, wherein a silicon-based liquid material is applied to a top portion of the bonding wire.
A method for manufacturing a semiconductor integrated circuit device , comprising the step of: dropping all of the bonding pads and connecting portions of the bonding wires to the bonding pads with a silicon-based coating. 【請求項２】 ボンディングパッドおよびこのボンディ
ングパッドに接続されるボンディングワイヤを有する半
導体集積回路装置の製造方法において、上記のボンディングワイヤの頂点部分の配列に応じた形
状の部材から、 上記ボンディングワイヤの頂点部分にシ
リコン系液材を滴下することにより、上記ボンディング
パッドおよび上記ボンディングワイヤの上記ボンディン
グパッドとの接続部をシリコン系被膜で全て被覆する工
程を有することを特徴とする半導体集積回路装置の製造
方法。2. A method of manufacturing a semiconductor integrated circuit device having a bonding pad and a bonding wire connected to the bonding pad, wherein the shape according to the arrangement of the apex portion of the bonding wire is provided.
A step of dripping a silicon-based liquid material onto the apex portion of the bonding wire from the member in the shape of a member to cover the bonding pad and the connection portion of the bonding wire with the bonding pad with a silicon-based coating. A method for manufacturing a semiconductor integrated circuit device.
JP15734694A 1994-07-08 1994-07-08 Method for manufacturing semiconductor integrated circuit device Expired - Fee Related JP3354716B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15734694A JP3354716B2 (en) 1994-07-08 1994-07-08 Method for manufacturing semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15734694A JP3354716B2 (en) 1994-07-08 1994-07-08 Method for manufacturing semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPH0823007A JPH0823007A (en) 1996-01-23
JP3354716B2 true JP3354716B2 (en) 2002-12-09

Family

ID=15647678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15734694A Expired - Fee Related JP3354716B2 (en) 1994-07-08 1994-07-08 Method for manufacturing semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JP3354716B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201432864A (en) * 2013-02-01 2014-08-16 Murata Manufacturing Co Semiconductor device

Also Published As

Publication number Publication date
JPH0823007A (en) 1996-01-23

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