JPH033200A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the number of external test control terminals and, simultaneously, to facilitate a test work by providing a test pattern generating circuit, a read/write control signal generating circuit, a counter, a comparing circuit and a clock generating circuit inside. CONSTITUTION:When a test mode is selected by a control to an external test control terminal 5, selectors 2-4 select an input terminal B, and a clock signal is outputted from a clock generating circuit 17. Thus, a counter 15 successively updates an address, and the address if given as the address of a storage circuit 1 through the selector 4. Simultaneously, a test pattern is successively outputted from a test pattern generating circuit 13, and it is given as input data through the selector 2. A read/write control singnal is outputted from a signal generating circuit 14, and it is given through the selector 3 to the storage circuit 1. As a result, the storage circuit 1 aternately executes the write and read of the test pattern to be successively generated, the write data and read data are compared by a comparing circuit 16, and the fact that the correct write is executed is confirmed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device with a test mode.

[Prior Art] A device shown in FIG. 2 has been known as a semiconductor memory device equipped with a test mode.

This device is constructed by connecting selectors 2, 3.4 to the respective front stages of the data input terminal 11 of the memory circuit 1, the read/write control signal input terminal RW, and the address input terminal ADR. These selectors 213.4 select the first input terminal A in the normal mode and the second input terminal B in the test mode, respectively, based on the test control signal applied to the external test control terminal 5. Output from output terminal Y.

As a result, in the normal mode, the input data from the data input terminal θ, the read/write control signal from the read/write control signal input terminal 7, and the address from the address input terminal 8 are selected, respectively, and each of the memory circuits 1 Input terminal I, RW, AD
In the test mode, the test data from the external test data input terminal 9, the test read/write control signal from the external test read/write control signal input terminal 10, and the external test address input terminal Test addresses from 11 are selected and applied to input terminals I, RW, and ADR of the memory circuit 1, respectively.

According to this device, the external test control terminal 5 is controlled to be in the test mode, and test data, read/write control signals, and addresses are externally applied to the input terminals 9, 10, and 11, respectively, and the output terminal 12 By externally confirming the data read from the semiconductor memory device, it is possible to confirm the normal operation of the semiconductor memory device.

[Problems to be Solved by the Invention] However, in the above-described conventional semiconductor memory device, test data, addresses, and read/write control signals must be input from the outside during the test mode. This has the problem of requiring an extra external terminal for input, which increases the chip size.

Furthermore, when performing a test, test circuits must be externally attached to these external terminals, so there is a problem in that the test work is also complicated.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a semiconductor memory device that can reduce the number of external terminals and also allows easy testing.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a clock generation circuit that outputs a clock signal, and a test pattern generation circuit that sequentially outputs test patterns according to the clock signal output from the clock generation circuit. , a first selector that selects and outputs either normal data or the test pattern based on an external test control signal, and a signal generation circuit that sequentially outputs test read/write control signals in accordance with the clock signal. a second selector that selects and outputs either the normal read/write control signal or the test read/write control signal based on the external test control signal; a counter that sequentially outputs addresses; a third selector that selects and outputs either the normal address or the test address based on the external test control signal; and the first to third selectors. A memory circuit whose output is input to a data input terminal, a read/write control control input terminal, and an address input terminal, respectively, and a comparison circuit which compares input and output data of this memory circuit and outputs the comparison result as a test result. It is characterized by having

[Function] According to the present invention, when the test mode is switched from the outside by an external test control signal, the first to third selectors select the test pattern and signal from the test pattern generation circuit provided inside the semiconductor device. A test read/write control signal from the generation circuit and a test address from the counter are respectively selected. As a result, test patterns are sequentially written into the memory circuit and sequentially read out. The test pattern before being written into the storage circuit and the test pattern after being written into the storage circuit are compared by a comparison circuit, and the comparison result is read out to the outside as a test result.

Therefore, according to the present invention, the only information provided from the outside for testing is a test control signal for switching the device to the test mode, and the number of external terminals can be significantly reduced.

Furthermore, since there is no need to externally supply data, addresses, and read/write control signals for testing, testing can be performed extremely easily.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention. Note that in FIG. 1, the same parts as in FIG. 2 are given the same reference numerals, and explanations of overlapping parts will be omitted.

In this embodiment, a test pattern generation circuit 13, a signal generation circuit 14, and a counter 15 are newly provided in front of the second input terminal B of the three selectors 2 and 3. A clock generation circuit 1 is provided with a comparison circuit 16 that compares read data from the storage circuit 1 with data read from the storage circuit 1, and further supplies a clock signal to each of these circuits.
7 has been newly established. The test control signal inputted from the external test control terminal 5 is supplied not only to the three selectors 2 and 3. In this case, the clock generation circuit 17 is activated to output a clock signal.The test pattern generation circuit 13, the signal generation circuit 14, and the counter 15 generate test patterns and test readout according to the clock signal. A write control signal and a test address are sequentially output.The comparison circuit 16 also compares the data before being written to the memory circuit 1 and the data read after being written to the memory circuit 1. Then, the comparison result is output from the test result output terminal 18 as a test result.

Next, the operation of the semiconductor memory device according to this embodiment configured as described above will be explained.

In the normal mode, the selectors 2 to 4 select the first input terminal A, so the data input terminal 11 of the storage circuit 1
Input data from the data input terminal 6, a read/write control signal from the read/write control input terminal 7, and an address from the address input terminal 8 are input to the read/write control terminal RW and address input terminal ADH, respectively. Therefore, in this case, normal access to the memory location specified by the address in memory circuit 1 is performed.

When the test mode is selected by controlling the external test control terminal 5, the selectors 2 to 4 select the second input terminal B, and the clock generation circuit 17 outputs a clock signal. Thereby, after the counter 15 is reset, the address is sequentially updated from the initial address value according to the clock signal, and the updated address is given as the address of the memory circuit 1 via the selector 4. At the same time, the test pattern generation circuit 13 sequentially outputs test patterns in accordance with the clock signal, and these are given as input data to the storage circuit 1 via the selector 2. Further, the signal generation circuit 14 outputs a read/write control signal that instructs writing and reading of the test data and address at twice the cycle, and this signal is transmitted to the memory circuit 1 via the selector 3. Provided as a write control signal.

As a result, the memory circuit 1 alternately writes and reads sequentially generated test patterns. The write data and the read data are then compared in the comparison circuit 18, and if the comparison results match, it can be confirmed that the write has been performed correctly.

[Effects of the Invention] As described above, according to the present invention, a test pattern, a test read/write control signal, and a test address are generated internally by an external test control signal, and are selectively applied to the storage circuit. At the same time, the comparison circuit compares the test pattern before it is written to the memory circuit with the test pattern after it is written to the memory circuit, so that the information given from the outside for testing can be used to set the device in test mode. All that is required is a control signal to switch to , and the number of external terminals can be significantly reduced.

Furthermore, since there is no need to externally supply data, addresses, and read/write control signals for testing, testing can be performed extremely easily.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional semiconductor memory device.

Claims (1)

[Claims] (1) A clock generation circuit that outputs a clock signal, a test pattern generation circuit that sequentially outputs test patterns according to the clock signal output from this clock generation circuit, and a test pattern generation circuit that generates normal data and the test pattern based on an external test control signal. a first selector that selects and outputs either one of the signals; a signal generating circuit that sequentially outputs a test read/write control signal according to the clock signal; and a signal generator that sequentially outputs a test read/write control signal based on the external test control signal. a second selector that selects and outputs either the control signal or the test read/write control signal; a counter that sequentially outputs test addresses in accordance with the clock signal;
a third selector that selects and outputs either the normal address or the test address based on the external test control signal; and a third selector that selects and outputs either the normal address or the test address based on the external test control signal; A semiconductor comprising: a memory circuit that receives input to a write control control input terminal and an address input terminal; and a comparison circuit that compares input and output data of the memory circuit and outputs the comparison result as a test result. Storage device.