JPH04324191A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To decrease the number of terminals without reducing the function and reliability of the device. CONSTITUTION:The device is provided with a switching circuit 6 for generating a switching signal SC which becomes low and high levels for specified periods within a period from the specified starting point of the current address of an address signal to the specified starting point of next address. It is also provided with a switching circuit 7 for supplying its result by switching the specified bit D 0 of the first data D 0 to D m of a main memory cell section 1 with the parity bit data P of a parity data memory cell section 2 in accordance with the level of the switching signal SC to one terminal Td 0.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a semiconductor memory device.
In particular, the present invention relates to a semiconductor memory device including a main memory cell section and a memory cell section that writes and reads data in synchronization with the main memory cell section.

0002

[Prior Art] As a conventional semiconductor memory device of this type,
FIG. 4 shows an example in which the memory cell section that reads data in synchronization with the main memory cell section is a parity data memory cell section.

This example includes a main memory cell section 1 that reads and outputs a plurality of bits of first data D0-Dm from an address specified by address signals A0-An via an address selection circuit 3, and A parity data memory cell section 2 reads parity bit data P corresponding to the first data D0 to Dm read from the main memory cell section 1 from an address specified by An, and the first data D0 to Dm. and parity bit data P
The configuration includes output circuits 4 and 5 that output the signals to the outside via corresponding terminals Td0 to Tdm and Tp, respectively.

FIG. 5 is a timing diagram of signals of various parts for explaining the operation of this example.

[0005] From time t1 when specifying the current address of address signals A0 to An to start specifying the next address t
The period T up to 4 is one read cycle of this semiconductor memory device. During this period T, data is read from the addresses of the main memory cell section 1 and the parity data memory cell section 2 specified by the address signals A0 to An.

[0006]

[Problems to be Solved by the Invention] The above-described conventional semiconductor memory device corresponds to the data D0 to Dm read from the main memory cell section 1 and the parity bit data P read from the parity data memory cell section 2, respectively. Since the output is output to the outside via terminals Td0 to Tdm and Tp, there is a drawback that the number of terminals increases, and in memory cards etc. using this semiconductor storage device, the number of terminals that can be used is limited. Since restrictions may be placed on the data, it is necessary to take measures such as deleting the parity function, which poses a problem in that reliability and functionality must be reduced.

An object of the present invention is to provide a semiconductor memory device in which the number of terminals can be reduced without reducing reliability or functionality.

[0008]

[Means for Solving the Problems] A semiconductor memory device of the present invention includes a main memory cell portion that reads and outputs a plurality of bits of first data from an address specified by an address signal, and an address specified by the address signal. a memory cell section for reading out second data corresponding to the first data read out from the main memory cell section; and a memory cell section for reading out second data corresponding to the first data read out from the main memory cell section; In a semiconductor memory device having a plurality of output terminals, the first level and the second level are set for predetermined periods, respectively, from the start of specifying the current address of the address signal to the start of specifying the next address. a control circuit that outputs a switching signal having a level of
and a switch circuit that selects either a specific bit of the data or the second data and outputs the selected one to a terminal corresponding to the specific bit of the first data.

Further, the main memory cell section and the memory cell section can read the first and second data from the address specified by the address signal and write data to the address specified by the address signal. A switch circuit selects either a specific bit of the plurality of bits of the first data or the second data according to the level of the switching signal, and selects one of the specific bit of the plurality of bits of the first data and the second data. The circuit is configured to output a bit to a corresponding terminal and supply data from a terminal corresponding to the specific bit to either the main memory cell section or the memory cell section.

0010

[Example] Next, an example of the present invention will be described.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory device shown in FIG. , a switch control circuit 6 that outputs a switching signal SC that is at a first level (low level) and a second level (high level) for each predetermined period, and a plurality of bits of first data according to the level of the switching signal SC. D
The present invention is characterized in that a switch circuit 7 is provided which selects either a specific bit D0 of 0 to Dm and parity bit data P and outputs it to a terminal Td0 corresponding to the specific bit D0.

Next, the operation of this embodiment will be explained. FIG. 2 is a timing chart of signals of various parts to explain the operation of this embodiment.

[0014] From time point t1 when designation of the current address of address signals A0 to An starts to time point t when designation of the next address starts.
The period T up to 4 is one reading heading cycle, and within this period T, the switching signal SC has a low level period (period up to t3) and a high level period (period after t3).

During the period when the switching signal SC is at a low level, data D0 from the main memory cell section 1 is output to the terminal Td0, and during the period when the switching signal SC is at a high level, the parity bit data P from the parity data memory cell section 2 is output to the terminal Td0. is output.

[0016] In this way, the number of terminals can be reduced without removing the parity function or reducing data reliability.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

This embodiment uses a readable and writable general-purpose 2
The present invention is applied to a memory card equipped with two main memory cell sections 1a and 1b and a 1-bit general-purpose sub-memory cell section 8 that can be read and written in synchronization with these main memory cell sections 1a and 1b. It is. The basic operation and effects are the same as in the first embodiment.

Note that in these embodiments, the switching signal S
Although the data to be switched by C is one bit, it is also possible to switch a plurality of bits, and in this case, the number of terminals can be reduced by the number of bits.

[0020]

Effects of the Invention As explained above, the present invention provides a first level and a second level for each predetermined period within the period from the start of designation of the current address of the address signal to the start of designation of the next address. A switching signal is generated, and depending on the level of this switching signal, a predetermined bit of the first data of the main memory cell section and the second data of the memory cell section are switched and supplied to one terminal and this terminal. By adopting a configuration in which transmission is performed from the terminal, there is an effect that the number of terminals can be reduced without deteriorating functionality or reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing diagram of signals of various parts for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a block diagram showing a second embodiment of the invention.

FIG. 4 is a block diagram showing an example of a conventional semiconductor memory device.

5 is a timing diagram of signals of various parts for explaining the operation of the semiconductor memory device shown in FIG. 4; FIG.

[Explanation of symbols]

1, 1a, 1b Main memory cell section 2
Parity data memory cell section 3 Address selection circuits 4, 5 Output circuit 6 Switch control circuit 7 Switch circuit 8 Sub-memory cell sections 9a to 9c Input/output circuit

Claims (2)

[Claims] 1. A main memory cell unit that reads and outputs a plurality of bits of first data from an address specified by an address signal; A semiconductor memory device having a memory cell section for reading out second data corresponding to one data, and a plurality of terminals for respectively outputting each bit of the data read from the main memory cell section to the outside in a corresponding manner. , a control circuit that outputs a switching signal that is at a first level and a second level for a predetermined period, respectively, within a period from the start point of specifying the current address of the address signal to the start point of specifying the next address; , a terminal that selects either a specific bit of the plurality of bits of first data or the second data according to the level of the switching signal and corresponds to the specific bit of the first data. What is claimed is: 1. A semiconductor memory device comprising: a switch circuit for outputting data to a semiconductor memory device; Claim 2: The main memory cell section and the memory cell section are configured to perform a first
and second data can be read and data can be written to an address specified by the address signal, and a switch circuit selects a specific bit of the plurality of bits of the first data according to the level of the switching signal. and selecting one of the second data and outputting a specific bit of the first data to the corresponding terminal,
2. The semiconductor memory device according to claim 1, wherein the circuit supplies data from a terminal corresponding to the specific bit to either the main memory cell section or the memory cell section.