JPH0241058B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to information processing devices such as computers, and particularly to a high-speed continuous read/write operation method for a storage device.

[Prior art]

In recent years, with the rapid development of semiconductor integrated circuit technology, semiconductor memory ICs used in storage devices have
There is a trend toward increasing capacity. A storage device using such a large-capacity memory IC as a storage medium is
Not only is it required to be able to perform read/write operations at high speed, but it is also required to transfer data at high speed.

Conventionally, interleaving, in which different memory IC groups perform read/write operations in parallel, has been known as a method for reading or writing data at high speed. However, in order to reduce the number of input/output pins, single memory ICs tend to have larger capacities in the word direction, for example, 64k words x 1 bit or 256k words x 1 bit, so multiple memory ICs When interleaving is performed by dividing into groups, there is a drawback that the capacity of the memory device increases.

By the way, as such a large-scale memory IC,
To reduce the number of input pins, two-address transfer memory ICs are often used, which receive two timing inputs and an address signal twice. Some memory ICs of this type employ a nibble mode that allows for high-speed reading and writing of consecutive addresses.

Using this nibble mode, you can use the same memory
High-speed data transfer is possible because reading and writing can be performed at high speed to consecutive addresses within the IC. However, in a storage device that performs error correction, a write/read operation of consecutive addresses including a partial write operation (an operation of writing to a part of the data width) is performed after reading the data at the address, and then In addition to check correction, partial writing is performed by generating an error correction code from partial write data and rewrite data that is a part of read data, so there is a drawback that the partial write cycle time increases. [Object of the Invention] An object of the invention is to provide a system for high-speed reading and writing of continuous addresses, including partial writing, using a memory IC having a nibble mode in a storage device that performs error correction.

[Structure of the invention]

The present invention provides a memory which receives first and second address signals in synchronization with first and second clocks and sequentially performs read or write operations on several bits of the second address signal using the second clock. a storage section consisting of a group of elements; a data control section having an error correction code generation function and an error correction function; a memory control section that sends a signal for controlling error correction code generation and error correction to the control section; and a holding means for holding the data read from the memory unit for the number of consecutive operations, and selects the output of both holding means for each byte to create an error correction code, and the memory control unit is configured to perform partial writing. When performing a continuous operation from an address specified by a second address signal including input the clock until it returns to the partial write address, perform a read, write, or dummy operation during that time, and when it returns to the partial write address again, the information is output from the data control unit to the partial write address. This is a continuous operation method for continuous addresses including partial writing of a memory device that performs error correction.

[Embodiments of the invention]

Next, embodiments of the present invention will be described with reference to the drawings. Referring to FIG. 1, one embodiment of the present invention includes a memory control section 1, a storage section 2, and a data control section 3. The memory control unit 1 includes a start signal 4, a read/write designation signal 5, and an address signal 6.
is an input, and an address signal 9, a read/write control signal 10, and a data control signal 11 are output. The data control unit 3 writes the write data 7
The data control signal 11 is input, the read data 8 is output, and the data 12 is input/output. The storage unit 2 receives an address signal 9, a read/write
The write control signal 10 is input, and data 12 is input/output.

Here, the data 12 exchanged between the data control section 3 and the storage section 2 is error correction encoded data including information bits and error correction check bits added thereto. The data control unit 3 takes in the write data 7 and a first holding circuit (not shown) using the data control signal 11, creates an error correction check bit, adds this to the write data, and then reads the data 12. Output as . Further, the data control section 3 takes in data 12 consisting of information bits and check bits into a second holding circuit (not shown) using a data control signal 11, detects an error in the data, corrects it, and stores it in a third holding circuit.
A data control signal 11 is supplied to a holding circuit (not shown) of
, and outputs it as read data 8. Furthermore, the data control unit 3 selects the output of the first holding circuit and the output of the third holding circuit for each byte according to the specification of the data control signal 11, creates a check bit for error correction, and partially Data 1 is added to the write data as write data.
Output as 2. Note that the first and third holding circuits have as many sets of holding circuits as the number of consecutive partial write operations. In addition, the storage unit 2 has a data width equal to the data 12, is addressed by a first address signal and a second address signal synchronized with the first and second clocks, and is configured by applying the second clock. It is composed of a group of memory elements that can sequentially read or write several bits of the second address signal.

Next, the operation of this embodiment will be explained.

First, in the case of a read operation, the memory control unit 1
In addition to the start signal 4, an address signal 6 and a read/write designation signal 5 specifying reading are applied. At this time, the address signal 9 is outputted from the memory control unit 1 by two transfers, and in synchronization with this, the first and second clocks and a read/write control signal 10 specifying reading are outputted. At this time,
Data 12 is read from the storage section 2 from the address specified by the address signal 9. The data control section 3 converts this data 12 into a data control signal 1.
1, the data is held in the second holding circuit, and if there is an error, it is corrected and output as read data 8.

Next, in the case of a full write operation, the memory control unit 1 is supplied with a start signal 4, an address signal 6, and a read/write designation signal 5 specifying the full write state. At this time, the data control signal 11 is output from the memory control section 1. When the data control section 3 receives this data control signal 11, the first
After the write data 7 is held in the holding circuit, an error correction check bit is created from the write data 7, and this is output as data 12 together with the information bits. The storage unit 2 is given a read/write control signal 10 specifying writing together with the first and second clocks, and an address signal 9 transferred twice in synchronization with these clocks, and the corresponding address in the storage unit 2 is given. Data 12 is written to.

Further, in the case of a partial write operation, a read/write designation signal 5 specifying a partial write byte is provided to the memory control unit 1 along with a start signal 4 and an address signal 6. At this time, the data control signal 11 is output from the memory control section 1. After the write data 7 is input to the data control section 3 by this data control signal 11, it is held in the first holding circuit. On the other hand, the memory control section 1 outputs a first clock, a second clock, a read/write control signal 10 specifying reading, and an address signal 9 transferred twice in synchronization with these clocks. Data 12 is read from the corresponding address in storage section 2 by these signals. Data control section 3
In response to the data control signal 11, after holding the data 12 in the second holding circuit, checking whether there is an error in the data 12 and correcting it if there is an error,
It is held in the third holding circuit. Furthermore, the data control unit 3 creates write data 12 from this data and the data 7 that has already been input, and stores it in the storage unit 2.
give to In the storage unit 2, this write data 1
2 is written to the address previously designated by the address signal 9 by the read/write control signal 10 designated for writing. In this way, partial writing is performed.

Incidentally, the memory element group used in the storage section 2 is characterized in that several bits of the second address signal change continuously at high speed by inputting the second clock. Therefore, in the case of reading to consecutive addresses, high-speed continuous reading is possible by specifying the number of addresses to be read in advance using the read/write designation signal 5, and in the case of writing to all consecutive addresses, read/write is possible. If the number of addresses to be written is specified in advance by the write designation signal 5 and the write data 7 is sequentially applied, high-speed continuous full writing is possible.

However, in the case of a write or read operation that includes a partial write operation, as explained above, the partial write operation corrects errors in the data that has been read once, and combines part of this read data with the partial write data. This is done by creating information bits and error correction check bits from the data and then rewriting. Therefore, the cycle time becomes long and operations to consecutive addresses cannot be performed at high speed.

Therefore, in the embodiment of the present invention, in order to perform high-speed operation to consecutive addresses including partial writing,
After a read operation for partial writing, write once to another address in sequence using the second clock, perform a read or dummy operation, and when the address returns to the original address again, perform a write operation to perform partial writing. It's summery.

Note that the dummy operation means that the first clock remains output from the memory control unit 1 and the second clock and the control signal 10 designated for reading are output, but the data control signal 11 is not output. ,
This means that the data control section 3 does not operate and only the address given to the storage section 2 is updated.

2 to 4 are operation examples in which the memory element group can be operated in the nibble mode for the lowest two bits of the second address by the second clock. Figure 2 shows an example of partial writing and partial writing to consecutive addresses. Figure 3 is an example of partial writing, full writing, and partial writing to consecutive addresses. Figure 4 shows partial writing. , all writes,
This is an example of full write and partial write operations to consecutive addresses. In any of the cases shown in FIGS. 2 to 4, the start signal 4 and the operation start address are given by the address signal 6, these operation modes are given by the read/write designation signal 5, and the write data is given by the write data 7. shall be given in order.

First, referring to FIG.
The first and second addresses A are given in synchronization with RAS and the second clock, and read/write control is performed by timing, and the second clock reads address A ₀ and addresses (A ₀ +1) Read, address (A ₀ +2),
By dummy read operation of (A ₀ +3), write of address A ₀ , and write operation of address (A ₀ +1),
Partial writing to addresses A ₀ and (A ₀ +1) is performed. D ₀ is output data from the storage section, and D _I is input data to the storage section.

That is, as shown in FIG. 2, when a write operation is performed such as address A ₀ : partial write address A ₀ +1 address : partial write, both addresses A ₀ and A ₀ +1 are partial writes, so writing is performed after reading once. The reason why addresses A ₀ +2 and A ₀ +3 perform dummy operations is that in nibble mode, the address specification is performed by the second clock, and the addresses A ₀ →A ₀ +
This is to return to the original address A ₀ because 1→A ₀ +2→A ₀ +3→A ₀ is repeated.

As mentioned above, the dummy operation is a case where the first clock is kept on, the second clock is on, the read/write control is in the read state, and the data control signal 11 is not applied. This refers to the case where only the address is updated.

Here, the data control unit 3 has a first holding circuit for write data and a third holding circuit for read data for the number of consecutive operations, and furthermore, the partial write operation is divided into a read operation and a write operation. Therefore, no data collision or contention occurs in the data control unit 3.

In the case of Figure 3, the address is
Read A ₀ , write address (A ₀ +1), read address (A ₀ +2), address (A ₀ +3)
Dummy read of address A 0, write of address A ₀ , dummy read of address (A ₀ + 1), address (A ₀ +
By writing 2), partial writing to address A ₀ , full writing to address (A ₀ +1), and partial writing to address (A ₀ +2) are performed.

That is, as shown in FIG. 3, when a write is performed at address _A0 : partial write _A0 +1 address: full write _A0 +2 address: partial write, writing to address _A0 is a partial write, so 2 Writing to address A _{0 +1} is completed when address A ₀ +1 is specified for the first time, and writing to address A ₀ +2 is completed when address A ₀ +1 is specified for the first time.
Writing to an address is a partial write, so the second time
This is performed when address A ₀ +2 is designated, and the dummy operation to addresses A ₀ +3 and A ₀ +1 is performed again because it is necessary to write to addresses A ₀ and A ₀ +2. That is, the address is A ₀ in nibble mode.
This operation is included to perform the cycle →A ₀ +1 →A ₀ +2 →A ₀ +3 →A ₀ . Furthermore, as described in FIG. 2, the data control section 3 is provided with first and third holding circuits corresponding to the number of consecutive operations.
No data conflicts or collisions occur.

In the case of FIG. 4, read address A ₀ and read address (A ₀ +1) in the same way as FIGS. 2 and 3.
write, write address (A ₀ +2), read address (A ₀ +3), write address A ₀ ,
Dummy reading of addresses (A ₀ +1), (A ₀ +2),
By writing the address (A ₀ + 3), the address
Partial write to A ₀ , full write to address (A ₀ +1), full write to address signal (A ₀ +2),
Partial writing to address (A ₀ +3) is performed.

That is, as shown in FIG. 4, when the A ₀ address: partial write A ₀ +1 address: full write A ₀ +2 address: full write A ₀ +3 address: partial write operation is performed, A ₀ , A ₀ Addresses A ₁ and A ₀ +2 are both full write, so they can be written in one operation, but A ₀
To call address +3 again, A ₀ +1, A ₀
A dummy operation is being performed at address +2. Also in this case, due to the configuration of the data control unit 3, data competition and collision will not occur.

In addition, in the explanation of FIGS. 2 to 4, the nibble mode is the lowest two bits of the second address, but
It is not necessarily limited to 2 bits. Further, the starting address is not limited to the minimum address of the lower several bits of the second address. That is, it is sufficient if the storage section can be operated by cycling in order from the start address within a predetermined address range using the second clock.

〔Effect of the invention〕

As explained above, according to the present invention, in an error correction device, the first address and the second address are synchronized with the first clock and the second clock.
After the second address is given, a read operation of the partial write operation is performed using a memory element group capable of high-speed reading/writing to successive addresses, and then the next address is read. Perform sequential read, write, or dummy operations, and then write to the partial write address again.
This has the advantage that it is possible to provide a storage device capable of reading and writing operations to continuous addresses, including partial writing, at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
4 are time charts showing an example of the operation of the embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Memory control unit, 2...Storage unit, 3...Data control unit, 4...Start signal, 5...Read/write designation signal, 6...Address signal, 7...Write data,
8... Read data, 9... Address signal, 10... Read/write control signal, 11... Data control signal,
12...Data.

Claims (1)

[Claims] 1 From a group of memory elements that receive first and second address signals in synchronization with first and second clocks and perform read or write operations on several bits of the second address signal in order by the second clock. a data control unit having an error correction code generation function and an error correction function;
and a memory control section that sends out a second clock, a read or write control signal, and an address signal, and sends a signal for controlling error correction code generation and error correction to the data control section, and the memory control section includes: When performing a continuous operation from the address specified by the second address signal including partial writing to consecutive addresses, after reading the information of the partial write address from the storage section and inputting it to the data control section, 2 clock is input until it returns to the partial write address, during which it performs read, write, or dummy operations, and when it returns to the partial write address again, it is output from the data control section to that partial write address. A method of continuous operation to continuous addresses, including partial writing of a storage device that performs error correction, characterized by writing information.