JPH04106793A - Memory interface circuit - Google Patents

Abstract

PURPOSE:To shorten the read-out/write time of a memory by providing a write register and a read-out register of data and various control circuits in a memory interface circuit. CONSTITUTION:Based on a low speed clock pulse CK1, a low speed address signal is generated by a low speed address generating means 21. The low speed address signal is decoded by a decoder 22 and a register select is generated. The register select selects a data storage means 28, and by the pulse CK1 and a read-out pulse generating means 23, a read-out register strobe is generated and supplied to a read-out data storage means 29. A memory data bus of a memory 24 is connected to a selecting means 27, the storage means 29 and the storage means 28, and at the time of write, first of all, by a write register strobe, data on a register data bus is stored in the write storage means 28. At the time of read-out, by read-out register enable, data is outputted to the register data bus from the storage means 29.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interface circuit that performs memory reading and writing in an information processing device equipped with a nonvolatile memory.

[Conventional technology]

FIG. 4 shows a block diagram of a conventional example, and FIG. 3 shows a timing chart during memory operation.

Although FIG. 3 shows an operation in which the memory control command and data are of a 4-bit parallel type, there is also a type in which the memory control command and data are configured in a serial type, and a type in which a part of the control command is deleted.

In FIG. 4, 41 is a microprocessor, 42 is an interface device for connecting the microprocessor and memory, and 46 is a memory.

In FIG. 3, ■ is a memory chip select, 0 is a memory clock signal (hereinafter referred to as memory CLK),
0 to ■ are 4-bit parallel data, such as memory control signals, memory addresses, and memory data.

Next, the operation will be explained. When reading and writing data to the memory, the microprocessor 41 accesses the memory 46 via the bus and interface device 42 to read and write data from the memory.

As an access operation of the memory 46 when reading/writing data from the memory, a read/write command, a lower address, an upper address, and a reset command are sequentially sent to the memory. These are written to the memory at the falling edge of memory CLK (Z). Next, note 1. IcL
In synchronization with the rising edge of K(2), data corresponding to 4 clock pulses, that is, 16 bits, is read and written. Finally, a reset command is sent to the memory, and one cycle ends. Regarding writing to the memory, after the last reset command shown in FIG. 3, old data is erased and new data is written inside the memory.

[Problem to be solved by the invention]

However, when using a non-volatile memory such as E2FROM, it generally takes more time to read and write to a non-volatile memory than a normal RAM. If the pulse width of the memory CLK■, which allows the memory to operate, is about 40 μs, the memory read time is about 360 μS, and the memory write time (even if the same amount of time is required).

The present invention aims to shorten memory read and write times.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a data write register, a data read register, and various control circuits in a memory interface circuit placed between the microprocessor and the memory, so that the microprocessor can send and receive data. By dividing the functions between the memory interface circuit and these registers to write and read data in a relatively time-consuming manner in response to control signals from the microprocessor. Reduces the burden on the microprocessor and speeds up the entire system.

As shown in the principle diagram of Fig. 2, the low-speed clock pulse CK
1, the low-speed address generation means 21 generates a low-speed address signal. A low-speed address signal is decoded by a decoder 22 to generate a register select. Register select selects the write data storage means 28, and CKI
A read register strobe is generated by the read pulse generating means 23 and supplied to the read data storage means 29.

The control signal generation means 26 receives inputs such as an R/W control that determines memory reading and writing, an address bus that selects each storage means, a data bus that inputs and outputs memory read and write data, and an enable control that executes access. and generates each control signal.

The register data bus output from the control signal generating means 26 inputs and outputs data to and from the read data storage means 29 and the write data storage means 28. The address of the memory is stored from the address control input bus into the memory address storage means 25 by a memory address strobe. A memory control signal 71 is input to the selection means 27 as a memory read, write, and reset signal. The start enable is a signal that starts the operation of the low-speed address generation means 21. Memory chip select is memory 2
4 to enable the memory to operate.

Memory CLK is a clock signal for memory operation, and memory 2
4. The memory data bus of the memory 24 is connected to the selection means 27, the read data storage means 29, and the write data storage means 28, and when writing, the data on the register data bus is first stored in the write data storage means 28 by a write register strobe. Ru. At the time of reading, data is outputted from the reading ratio data storage means 29 to the register data bus by the reading ratio register enable.

[Effect]

For memory reading and writing, the memory is accessed via the control signal generating means 26. The address bus sets the lower and upper addresses of the memory address storage means, the start of operation of the low-speed address generation means, and the settings of the write and read data storage means. The data node inputs the lower and upper addresses of the memory and write data, and when reading, the read data is output. The R/W control is set to "1" for reading and "0" for writing. The enable control is normally in the "0" state and is accessed during the "1" period during reading, and at the falling edge from "l" to "0" during writing.

In a memory read operation, the address bus is set to address 1 of the memory address storage means 25, the data bus is set to the memory address, the R/W control is set to "0", and the enable control is set to "0". from 1
By setting it to "1" and setting it to "0" again, the memory address is stored in the memory address storage means 5 by the memory address strobe at the fall of the enable control. Next, by setting address 0, which specifies the low-speed address generation means 21, in the address bus and inputting it to the control signal generation means 26 in the same way, the low-speed address generation means 21 is put into an operating state by the start enable, and the memory chip The select and memory CLK are as shown in the timing chart in FIG.

The selection means 27 selects C according to the state of the low-speed address signal bus.
Memory reading comparison command in synchronization with the rise of KI,
Output the lower memory address, upper address, and reset, and take notes!
Data is output from the memory in synchronization with the rising edge of JCLK, and is stored in the read data storage means 29 by the read register strobe. When it is desired to read memory data onto the data bus, the address of the read storage means 29 is set on the address bus and the enable control is set to l'-IJK.

Next, when writing data to the memory, the memory address is stored in the memory address storage means 25, the address of the write data storage means 28 is set to the address bus, and the memory write data is transferred to the data bus. Set the R/W control to ``0'' and turn the enable control from rOJ to ``1'' again.
By setting OJ, memory data is stored in the write data storage means 28 by the write register strobe at the fall of the enable control.

Then, the address is set to O and R/W control is set to rOJ, and at the fall of the enable control, the low-speed address generation means 21 is activated by the start enable, and the memory CLK and memory chip select are also activated in the same way as for reading @Figure 3 It will look like the timing chart of
A write operation is started. In the write operation, when the memory write, memory lower, upper, and reset commands are output from the selection means 27, register select is selected from the decoder from the next rising edge of CKI, and the write data is transferred from the write data storage means 28 to the memory data. It is output to the bus, input to the memory, and written to the memory at the falling edge of memory CLK.

In other words, by sending the memory address data at high speed when reading, and the memory address data and memory write data when writing, it is possible to shorten the time and improve the processing speed of the system by starting memory reading and writing. is planned.

〔Example〕

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment.

The counter 1 is a component of the low-speed address generation means 21, the selector 7 is a component of the selection means 27, the OR 3.4 is a component of the reading pulse generation means 23, and the address register 6 is a component of the memory address storage means 25. , write register 1 (9)...4 (10) is a component of the write data storage means 28, read register 1 (11)
-...4 (12) is a component of the read data storage means 29, and the control circuit 8 is a component of the control signal generation means 26. CLKl inputs a low-speed clock signal that allows the memory to operate. Memory read and write operations are accessed via a signal line input to the control circuit 8.

First, the signal lines of the control circuit 8 will be explained. The address bus is used to set the lower and upper addresses of the address register, the operation start setting of the counter, and the settings of write registers 1 to 4 and read registers 1 to 4. It is assumed that there are four read and write registers, and their addresses are 3 to 6, respectively. The data bus inputs the lower and upper addresses of the memory and write data, and when reading, the read data of the memory is output. When the R/W control is "1", it reads memory data, and when it is "0", it writes memory data, starts counter operation, and writes to lower and upper memory addresses. The enable control is a signal line that controls the start of reading and writing, and during read comparison operation, it usually changes from the state of "0" to "
The bit changes to "1", and data is output to the data bus while it is "1". When rOJ is reached, data is not output. When writing, it usually changes from "0" to "1" and then becomes "0" again.
Write the data and address on the data bus at the falling edge of the signal, and set the counter operation to start at the falling edge, as well as when writing data.

Next, the operation of this embodiment having such a configuration will be explained. When reading data from memory, first set the memory lower address. This sets the address to 1 (address register 6
), set memory address to data bus, R/W
By setting the control to ``0'' and changing the enable control from rOJ to ``1'' and setting it to ``0'' again, the data is stored in the address register 6 from the control circuit 8 via the address control input bus under the memory address strobe. . Also, set the upper address in the same way. Next, to read the memory data, set the address to O (designating counter 1), set the R/W control to "0", and change the enable control from rOJ to rlJ and back to rOJ, and then set the start enable from the control circuit 8. Through this, the counter 1 becomes operational, starts a count-up operation, and generates a low-speed address signal. At this time, the selector 7 is selected based on the low-speed address signal, and the memory read mode, lower address, upper address, and reset are sequentially written into the memory as shown in the timing chart of FIG. At this time, the memory chip select and memory CLK that are input to the memory are similarly changed as shown in FIG. by CK
In synchronization with I, read register strobes 1 to 4 store read data in read registers 1 (11) to 4 (12).

Then, when actually reading, set addresses 3 to 6 corresponding to numbers 1 to 4 of the register you want to read and R/
By setting the W control to "1" and setting the enable control to "1", data is output to the data bus. This operation allows data to be read out sequentially by simply changing the address.

Next, in a memory write operation, first a memory lower address is set. This sets the address to 1, the memory address to the data bus, the R/W control to "0", the enable control from "0" to rlJ, and rO again.
By setting the value to J, the data is stored in the address register 6 from the control circuit 8 via the address control input bus under the memory address strobe. Also, set the upper address in the same way.

Also, for the memory data l to be stored in write register 1, set the address to 3, set the write data on the data bus, set the R/W control to rOJ, change the enable control from rOJ to "1", and set it to "0" again. By doing this, the control circuit 8 outputs the write register strobe 1.
The data set on the data bus is stored in the write register 1 (9) via the register data bus.

Similarly, write data 2.3.4 is sequentially written to write register 2.3.4 (10
) is written. When this series of operations is completed, the address is set to 0, the R/W control is set to rOJ, and the enable control is set from rOJ to "1" and then set to "0" again. enters the operating state, the input of the selector 7 is selected by the low-speed address signal bus, and the write command, address lower, upper, and reset are sequentially output to the memory 5, and the memory chip select input to the memory 5 at this time , the memory CLK becomes as shown in FIG. 3, and the memory becomes operational. Decoder 2 by low speed address signal
is selected, and memory data is output to the memory data bus by register selects 1 to 4 and sequentially written into the memory.

〔Effect of the invention〕

According to the memory interface circuit of the present invention, when reading memory, if the table memory address is written and access is started, the waiting time of the external circuit is reduced, and whenever the external circuit wants to read the data at the memory address, the register address By setting , it is possible to read and compare the data read to the read register by setting it to read mode.

When writing, write the memory write address, sequentially write memory data to the write register, start access, and then the memory data can be written by the processing of the memory interface circuit, allowing high-speed writing.

Additionally, since the memory mode settings are included in the circuit, the burden on software is reduced.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is a principle diagram of the present invention, FIG. 3 is a memory operation timing chart, and FIG.
The figure is a block diagram of a conventional example. 5... Memory, 6... Address register, 7... Selector, 8... Control circuit, 9... Write register 1. 10...Write register 4.11...
・Read register 1112...Read register 4゜θ θO■ O■

Claims (1)

[Scope of Claims] An information processing device equipped with a non-volatile memory (hereinafter referred to as memory), comprising: low-speed address generation means for generating a low-speed address signal based on a low-speed clock signal that enables the memory to operate; and the low-speed address signal. a decoder that generates a selection signal based on the low-speed address signal; a memory address storage unit that stores memory addresses for reading and writing data; and output signals of the memory address storage unit and memory read and write control signals in response to the low-speed address signal. selection means for selecting, read data storage means comprising at least one register and storing data read from the memory, and write data storage means comprising at least one register and storing write data in the memory. and when reading data from the memory, a memory address is stored in the memory address storage means, and a memory clock signal generated based on the output signal of the selection means and the low-speed clock signal corresponds to the memory address. The data is read from the memory and stored in the register of the read data storage means selected by the selection signal of the decoder, and when writing data to the memory, the memory address is stored in the memory address storage means and the write Write data is stored in the data storage means, and the data stored in the register of the write data storage means selected by the selection signal of the decoder is transferred to the memory by the output signal of the selection means and the memory clock signal. A memory interface circuit configured to write to memory corresponding to an address.