JPH10340596A - Data storage device and semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To send out parity bits to a data bus without providing an exclusive data line and affecting to writing/reading timing of data. SOLUTION: This semiconductor memory is provided with a parity control circuit 20 sending out parity bits to a data bus after finish of a write-cycle, the parity control circuit 20 has a parity bits generation circuit 22 and a write- parity register 23. Each data during a write-cycle period is synchronized with the external clock and written in a cell array 7. Parity bits corresponding to these write-data are generated by the parity bit generation circuit 22. Generated parity bits are converted to parallel data in accordance with pulse width of a data bus by the write-parity register 23, synchronized with the external clock, and sent out to a data bus. Thereby, write-data can be checked without providing newly an exclusive line for outputting parity bits.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data storage device and a semiconductor storage device capable of performing a parity check of data written in a storage unit such as a memory cell array.

[0002]

2. Description of the Related Art A semiconductor memory device for reading or writing data on a data bus in synchronization with an external clock is also called a synchronous semiconductor memory device. 2. Description of the Related Art Some synchronous semiconductor memory devices of this type can perform burst write for continuously writing a plurality of data and burst read for continuously reading a plurality of data.

FIG. 6 is a block diagram of a conventional synchronous semiconductor memory device capable of performing burst read and burst write. 6 includes an address register 1, a CE register 2, a burst signal register 3, a write signal register 4,
It includes an input register 5, an output register 6, a cell array 7, a sensor amplifier 8, a write control circuit 9, a burst counter 10, and an address decoder 11.

An address register 1, a CE register 2, a burst signal register 3, a write signal register 4 and an input register 5 store an externally input address signal, control signal (CE), burst signal, write signal and input data. Performs processing to synchronize with an external clock.

[0005] The sensor amplifier 8 amplifies the data read from the cell array 7 and supplies the amplified data to the output register 6. A write circuit 8a is provided inside the sensor amplifier 8, and the write circuit 8a controls writing of data output from the input register 5 to the cell array 7. The write control circuit 9 outputs a signal for controlling the write circuit 8a.

[0006] The address decoder 11 decodes an address signal output from the address register 1 and supplies it to the cell array 7. The burst counter 10 counts the number of burst writes and the number of burst reads.

FIG. 7 is an operation timing chart of the apparatus of FIG. 6. The operation of the apparatus of FIG. 6 will be described with reference to this timing chart. The timing chart of FIG. 7 shows an example in which burst read is performed continuously after performing burst write.
More specifically, an example is shown in which cell data at four addresses A5 to A8 is read immediately after data is written to four addresses A1 to A4.

The semiconductor memory device of FIG. 6 determines whether or not a burst write period or a burst read period is in accordance with the logic of a burst signal input from the outside. More specifically, a period from the time when the burst signal goes low to the time when the burst signal goes low is a write cycle period for performing burst write or a read cycle period for performing burst read.

When the burst signal goes low immediately before time T1 in FIG. 7, the address signal A1 is input to the address register 1 almost simultaneously, and at this time, the write signal goes low.

The address register 1 and the input register 5 latch the address signal A1 and the input data D (A1) at the edge of the external clock and synchronize them with the external clock. The output of the address register 1 is the address decoder 11
, And a decode signal for selecting a specific cell in the cell array 7 is output from the address decoder 11. The data output from the input register 5 is written to the specified cell.

As described above, the semiconductor memory device shown in FIG. 6 synchronizes an external address signal and input data with an external clock once and writes the data into the cell array 7. One clock delay occurs. For example, the data D (A1) input at time T1 in FIG. 7 is written to the cell array 7 after time T2 one clock later.

Similarly, in the case of performing a burst read, data read from the cell array 7 is synchronized with an external clock by the output register 6 and then transmitted onto the data bus. Until the data is output, a delay of one clock or more of the external clock occurs.

Therefore, in the case where burst write and burst read are performed consecutively, there is an empty space of about two external clocks after the end of the write cycle until the head data of the read cycle appears on the external data bus. A period occurs.

Therefore, in the device shown in FIG.
Is connected to the input terminal of the output register 6 so that the last data of the write cycle can be transferred from the input register 5 to the external data via the output register 6 by utilizing the idle time when switching from burst write to burst read. Output to the bus. The last data of the write cycle output immediately before such a read cycle is called write pass-through data.

For example, FIG. 7 shows an example in which write pass-through data Q (A4) is output before and after time T6, and this data Q (A4) is written before and after time T4. It is the same as A4). Each read data in the burst read period is output after the write pass-through data is output (after time T7 in FIG. 7).

[0016]

Since the above-mentioned write pass-through data is the last data of a write cycle, even if such data is sent out on the data bus, nothing is actually used in many cases. For this reason, a configuration that does not output write pass-through data is also conceivable.

However, even if the write pass-through data is not output, the data read timing and the write timing are not advanced. On the other hand, the data bus is in an empty state from the end of the write cycle to the start of the read cycle, and it is desirable to effectively use the data bus during this period.

Incidentally, there is a method called parity check as a method for determining whether or not data written in a semiconductor memory device is correct. This method sets a parity bit for each data to be written to the semiconductor memory device, and determines whether or not the data has been normally written to the cell array 7 based on the constituent bits of each data and the parity bit corresponding to the data. To judge.

The above-mentioned parity bits are usually dedicated I
In general, the generated parity bit is output by a different path from the data bus.
Therefore, there has been a problem that the circuit becomes complicated and the cost increases.

The present invention has been made in view of such a point, and an object of the present invention is to provide a dedicated data line for a parity bit without providing a dedicated data line for a parity bit, and to a timing for writing / reading data to / from a storage unit. Without affecting
An object of the present invention is to provide a data storage device and a semiconductor storage device capable of transmitting a parity bit onto a data bus.

[0021]

According to a first aspect of the present invention, there is provided a storage unit which is readable and writable, and synchronizes a plurality of bits of data on a data bus with an external clock. In the data storage device which writes the data to the storage unit and sends the data read from the storage unit to the data bus in synchronization with the external clock, a data write error is generated for each data written to the storage unit. A parity bit generation circuit for respectively generating a parity bit for detection, and a write cycle for writing data to the storage unit, after the end of the write cycle, the parity bits generated by the parity bit generation circuit during the write cycle period At least a part is synchronized with the external clock and transmitted on the data bus. And a tee output control circuit.

According to a second aspect of the present invention, in the data storage device according to the first aspect, the parity output control circuit continuously reads data from the storage unit after the end of the write cycle. Is performed, after the last data during the write cycle period is written to the storage unit, and before the leading data during the read cycle period is transmitted onto the data bus,
At least a part of the parity bits corresponding to each of the write data during the write cycle period is transmitted onto the data bus.

According to a third aspect of the present invention, in the data storage device according to the first or second aspect, the parity output control circuit includes a parity corresponding to an arbitrary number of continuous data including the last data in the write cycle period. Each of the bits is assigned to a different bit line of the data bus and transmitted in synchronization with the external clock.

According to a fourth aspect of the present invention, there is provided a memory cell array capable of reading and writing, an input register for synchronizing input data consisting of a plurality of bits on a data bus with an external clock, and output data read from the memory cell array. An output register that synchronizes the external clock with an external clock, an address register that synchronizes an external address signal with the external clock, and a decode signal for specifying a memory cell in the memory cell array based on an output of the address register. A semiconductor memory device comprising: an address decoder circuit for outputting data; and a control register for synchronizing a control signal for controlling writing and reading of data to and from the memory cell array with the external clock. A parity bit generation circuit for generating a parity bit for detecting a data write error, and a parity bit generation circuit for generating the parity bit during the write cycle after the end of a write cycle for writing data to the memory cell array. A parity bit output control circuit for transmitting at least one kind of the parity bits onto the data bus in synchronization with the external clock.

According to a fifth aspect of the present invention, in the semiconductor memory device according to the fourth aspect, the burst write is terminated based on a burst signal for instructing a burst write for continuously writing a plurality of types of data in the memory cell array. A burst end detection circuit for detecting whether or not the burst write has been completed, and the parity bit output control circuit generates the burst bit during the burst write period when the burst end detection circuit detects the end of the burst write. And transmitting at least one type of the parity bits on the data bus.

According to a sixth aspect of the present invention, in the semiconductor memory device according to the fifth aspect, the parity bit output control circuit continuously reads a plurality of types of data from the memory cell array after burst write. When the burst read is performed, after the last data during the burst write period is written to the memory cell array,
Before the first data in the burst read period is transmitted onto the data bus, at least a part of the parity bits corresponding to each data in the burst write period is transmitted to the data bus.

According to a seventh aspect of the present invention, in the semiconductor memory device according to the fifth or sixth aspect, the parity bits generated by the parity bit generation circuit are sequentially stored, and the parity bits are determined according to the number of bits of the data bus. A parallel-to-parallel conversion circuit that converts the data into parallel data and outputs the data in synchronization with the external clock.The parity bit output control circuit outputs the output of the serial-to-parallel conversion circuit to the data bus after the end of the burst write period. Send out.

The invention according to claim 8 is the semiconductor memory device according to claim 7, wherein the serial-parallel conversion circuit has a plurality of flip-flops directly connected, and the first-stage flip-flop is the parity bit generation circuit. Latching the parity bit generated in the above based on the external clock,
The flip-flops other than the first stage latch the output of the preceding flip-flop based on the external clock.

According to a ninth aspect of the present invention, in the semiconductor memory device according to the seventh or eighth aspect, the serial-parallel conversion circuit comprises:
When the number of parity bits equal to or greater than the number of output bits of the serial-parallel conversion circuit is input, the parity bits are replaced with newer parity bits in order from the oldest parity bit.

The invention of claim 1 will be described with reference to FIG. 1, for example. The "storage section" is in the cell array 7, the "parity bit generation circuit" is in the parity bit generation circuit 22,
"Parity output control circuit" is write parity register 2
3 and buffers 26b and 26c, respectively.

The invention of claim 4 will be described with reference to FIG. 1, for example. The "control register" corresponds to the CE register 2, the burst signal register 3, and the write signal register 4.

The invention of claim 5 will be described with reference to FIG. 1, for example. The "burst end detection circuit" corresponds to a parity bit binary counter 24 and a parity bit decoder circuit 25.

The invention of claim 7 will be described with reference to, for example, FIG. 1. The “serial / parallel conversion circuit” corresponds to the write parity register 23.

The invention of claim 8 will be described with reference to FIG. 5, for example.
Corresponds to 7.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a data storage device and a semiconductor storage device to which the present invention is applied will be specifically described with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram of a first embodiment of a semiconductor memory device according to the present invention. In FIG. 1, the same components as those in FIG. 6 are denoted by the same reference numerals, and the following description will focus on differences from FIG.

The semiconductor memory device of FIG. 1 is characterized in that it has a parity control circuit 20 indicated by a dashed line. The parity control circuit 20 generates a parity bit for each data to be written to the cell array 7, and sends out the generated parity bit to a data bus. It is assumed that the data bus includes M-bit data I / O1 to I / OM.

The parity control circuit 20 includes a parity input / output control circuit 21 and a parity bit generation circuit 22
, A write parity register 23, a parity bit binary counter 24, a parity bit decoder circuit 25, and buffers 26a to 26d.

The parity bit generation circuit 22 generates a parity bit for each data written in the cell array 7. The parity input / output control circuit 21 controls the operation timing of the parity bit generation circuit 22. The write parity register 23 rearranges the parity bits generated by the parity bit generation circuit 22, converts the data into parallel data having the same number of bits as the data bus, and outputs the parallel data in synchronization with an external clock.

Parity bit binary counter 24
Counts the number of data for generating parity bits. The value counted by this counter is decoded by the parity bit decoder circuit 25. The write parity register 23 is controlled according to the output of the parity bit decoder circuit 25.

In addition, unlike the conventional apparatus shown in FIG. 6, the output terminal of the input register 5 and the input terminal of the output register 6 are separately provided in the apparatus shown in FIG.
a, the input register 5 and the output register 6
Are not connected to each other. Therefore, the device shown in FIG. 1 does not output the write pass-through data at time T6 in the timing chart of FIG.

FIG. 2 is a diagram for explaining the schematic operation of the parity control circuit 20. FIG. 2 shows an example in which burst write for four cycles is performed four times in succession, and then a read cycle is performed. Each data is composed of 16 bits of I / O1 to I / O16. Each of these data is stored in the cell array 7 and a parity bit is generated for each data. The generated parity bit is sent to the data bus after the end of the write cycle period, and thereafter, the read cycle is performed.

The parity bit generation circuit 22 in the parity control circuit 20 changes the value of the parity bit for each data so that the result of adding the bits constituting each data and the parity bit is always even or odd. Set. For example, FIG. 3A shows constituent bits of write data.
FIG. 3B shows an example in which the addition result of I / O1 to I / O16 and the parity bit is an even number. FIG. 3B shows the configuration bits I / O1 to I / O16.
FIG. 14 is a diagram showing an example in which the addition result of a parity bit and a parity bit is set to an odd number.

In the case of FIG. 3A, if the addition result of I / O1 to I / O16 is odd, the parity bit is set to 1, and
If the addition result of I / O1 to I / O16 is an even number, the parity bit is set to 0. In the case of FIG. 3B, I / O1
If the addition result of ~ I / O16 is odd, the parity bit is 0
And the parity bit is set to 0 if the addition result of I / O1 to I / O16 is an even number.

The parity bits generated by the parity bit generation circuit 22 are sequentially input to the write parity register 23. The write parity register 23
As shown in FIG. 2, the parity bits from the parity bit generation circuit 22 are rearranged in accordance with the bits I / O1 to I / O16 on the data bus and converted into parallel data. There is no particular limitation on the order of rearrangement. For example, as shown in FIG. 2, previously input data is allocated to lower bits of the data bus. The rearranged parity bits are output to the outside via the data bus after the end of the write cycle.
A control circuit such as a CPU is connected to the outside of the semiconductor memory device, and the control circuit checks a parity bit.

FIG. 4 is an operation timing chart of the device of FIG. 1. The operation of the circuit of FIG. 1 will be described with reference to this timing chart. The timing chart of FIG. 4 shows an example in which, similar to FIG. 7, a burst write of 4 data (addresses A1 to A4) is performed and then a burst read of 4 data (addresses A5 to A8) is performed. I have. The external clock, address signal, burst signal, write signal and O
The timing of the E signal is the same as in FIG.

The input data on the data bus is input to an input register 5 and a parity bit generation circuit 2
2 is input. The parity bit generation circuit 22 generates and outputs a parity bit for each input data. The generated parity bit is stored in the write parity register 23.
And converted into parallel data having the same number of bits as the data bus.

For example, when write data is continuously input during times T1 to T4 in FIG. 4, a parity bit is generated for each data in the parity bit generation circuit 22. The generated parity bit is output from the parity bit generation circuit 22 during the cycle, and is output from the parity bit generation circuit 22 immediately after the data on the data bus is determined.

These parity bits are sequentially input to the write parity register 23 to rearrange the data, and sent out to the data bus in synchronization with an external clock around time T6 after the end of the write cycle. This time T6
In the prior art, the conventional semiconductor memory device shown in FIG. 6 sends out the write pass-through data on the data bus, but in the present embodiment, outputs the parity bit data instead of the write pass-through data. After time T7, the device operates in the same manner as the conventional device shown in FIG. 6, and data read from the cell array 7 during the burst read period is sequentially sent to the data bus.

As described above, in the first embodiment, the parity bits corresponding to each of the write data during the burst write period are sent to the data bus immediately after the end of the burst write. It can be detected via the data bus whether or not the proper write data has been input. Therefore, there is no need to provide a separate data line for parity bit detection, and write data can be checked with a simple circuit configuration.

In the first embodiment, the parity bit is output during the idle period (write pass-through data output period) after the end of the burst write, so that the parity bit is not affected without affecting the data write timing and the read timing. Can output bits.

In the apparatus shown in FIG. 1, if the burst write period continues for a long time, the number of parity bits output from the parity bit generation circuit 22 increases, and the write parity register 23 may overflow. In such a case, the write parity register 2
Among the parity bits input to 3, the oldest parity bits are erased in order, and the parity bits from the parity bit generation circuit 22 may be stored instead.

[Second Embodiment] In the second embodiment, a shift register comprising a plurality of flip-flops is connected to the output side of the parity bit generation circuit 22.

FIG. 5 is a block diagram of a second embodiment of the semiconductor memory device. In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals, and the following description will focus on differences from FIG.

The parity control circuit 20a shown in FIG. 5 includes a shift register 27 in which S flip-flops are connected in series, instead of the write parity register 23 shown in FIG.
Having. The parity bits output from the parity bit generation circuit 22 are sequentially input to the shift register 27. The output signal of the parity bit binary counter 24 is input to the clock terminal of each flip-flop 27a in the shift register 27.

With such a connection, the shift register 2
The flip-flop 27a in 7 sequentially shifts the parity bit in each cycle during the burst write period. Therefore, when the burst write period ends, the number (S) of parity bits equal to the number of flip-flops 27a is output from the shift register 27.

Each parity bit output from the shift register 27 is input to the parity bit decoder circuit 25 and is converted into parity bit data of the same number as the number of data buses. This data is sent out via the data bus after the end of the burst write period, as in the first embodiment.

As described above, in the second embodiment, the parity bits generated by the parity bit generation circuit 22 are input to the shift register 27 and sequentially shifted, so that the flip-flop 27a in the shift register 27 is shifted.
, The number of parity bits output in parallel can be easily changed. Therefore, for example, when the burst write period continues for a long time, the flip-flop 27
A change such as increasing the number of flip-flops 27a and reducing the number of flip-flops 27a when the burst write period is short can be easily performed.

In the second embodiment, even when the burst write period is long and the number of parity bits is larger than the number of flip-flops 27a, old parity bits are replaced with newer parity bits in order.
There is no possibility that the shift register 27 will overflow.

In the above-described first and second embodiments, an example has been described in which burst read is performed after burst write is performed. However, the present invention is applicable only to the case where burst write or burst read is performed. However, the present invention can also be applied to a case where writing and reading are performed continuously. In such a case, the parity bit of the write data may be output before reading the data from the cell array 7.

In each of the embodiments described above, the semiconductor memory device formed on the semiconductor chip has been described. However, the present invention can be applied to a circuit formed on a printed circuit board or the like. In this case, the cell array 7 shown in FIG. 1 may be replaced with a DRAM or SRAM chip, and the circuit shown in FIG. 1 may be connected to a control circuit such as a CPU.

[0062]

As described above in detail, according to the present invention, at least a part of the parity bits during the write cycle is transmitted onto the data bus in synchronization with the external clock after the end of the write cycle. A dedicated data line for outputting the parity bit is unnecessary, and the write data can be checked with a simple circuit configuration.

Since different parity bits are assigned to each bit of the data bus, the parity bits of a plurality of types of write data can be sent out simultaneously on the data bus, and the write data for a plurality of cycles can be checked simultaneously. .

Further, since the parity bit is output using the idle period of the data bus (the output period of the write pass-through data) after the end of the write cycle, the parity bit is not affected at all without affecting the data write timing and the read timing. Can output bits.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 illustrates a schematic operation of a parity control circuit.

FIG. 3 is a diagram showing an output example of a parity bit.

FIG. 4 is an operation timing chart of the device of FIG. 1;

FIG. 5 is a block diagram of a second embodiment of the semiconductor memory device.

FIG. 6 is a block diagram of a conventional synchronous semiconductor memory device.

FIG. 7 is an operation timing chart of the device of FIG. 6;

[Explanation of symbols]

 1 Address Register 2 CE Register 3 Burst Signal Register 4 Write Signal Register 5 Input Register 6 Output Register 7 Cell Array 8 Sensor Amplifier 9 Write Control Circuit 10 Burst Counter 11 Address Decoder 20 Parity Control Circuit 21 Parity I / O Control Circuit 22 Parity Bit Generation Circuit 23 Write parity register 24 Parity bit binary counter 25 Parity bit decoder circuit 26a, 26b, 26c, 26d Buffer 27 Shift register 27a Flip-flop

Claims (9)

[Claims] A storage unit that is readable and writable, wherein data composed of a plurality of bits on a data bus is written into the storage unit in synchronization with an external clock, and data read from the storage unit is used as the external clock. A data storage device for transmitting the data to the data bus in synchronization with the data bus; a parity bit generation circuit that generates a parity bit for detecting a data write error in correspondence with each data written to the storage unit; After the end of the write cycle for writing the data, at least a part of the parity bits generated by the parity bit generation circuit during the write cycle is transmitted to the data bus in synchronization with the external clock. A data storage device comprising: an output control circuit. 2. The parity output control circuit, when performing a read cycle for reading data from the storage section continuously after the end of the write cycle, sets the last data in the write cycle period to the storage cycle. After the data has been written to the data bus, at least a part of the parity bits corresponding to each of the write data during the write cycle period is stored before the head data during the read cycle period is transmitted onto the data bus. The data storage device according to claim 1, wherein the data is transmitted on the data bus. 3. The external output clock circuit, wherein the parity output control circuit assigns each of parity bits corresponding to a continuous arbitrary number of data including the last data during the write cycle to different bit lines of the data bus, and 3. The data storage device according to claim 1, wherein the data is transmitted in synchronization with the data. 4. A memory cell array capable of reading and writing, an input register for synchronizing a plurality of bits of input data on a data bus with an external clock, and synchronizing output data read from the memory cell array with an external clock. An output register for synchronizing an external address signal with the external clock; and an address decoder circuit for outputting a decode signal for specifying a memory cell in the memory cell array based on an output of the address register. And a control register for synchronizing a control signal for controlling writing and reading of data to and from the memory cell array with the external clock, wherein a data write operation is performed for each of the data to be written to the memory cell array. A parity bit generation circuit for generating a parity bit for detecting a write error, and at least one type generated by the parity bit generation circuit during a write cycle after completion of a write cycle for writing data to the memory cell array. And a parity bit output control circuit for transmitting the parity bit to the data bus in synchronization with the external clock. 5. A burst end detecting circuit for detecting whether or not a burst write has been completed, based on a burst signal for instructing a burst write to continuously write a plurality of types of data into the memory cell array, When the end of the burst write is detected by the burst end detection circuit, the bit output control circuit sends at least one type of the parity bits generated by the parity bit generation circuit to the data bus during a burst write period. 5. The semiconductor memory device according to claim 4, wherein: 6. A parity bit output control circuit according to claim 1, wherein when a burst read for reading a plurality of types of data from said memory cell array is performed continuously after the burst write, a final data during a burst write period is provided. Is written to the memory cell array, and at least a part of the parity bits corresponding to each data during the burst write period is transmitted to the data bus before the first data during the burst read period is transmitted onto the data bus. 6. The semiconductor memory device according to claim 5, wherein the data is transmitted to the semiconductor memory device. 7. Parity bits generated by the parity bit generation circuit are sequentially stored, and these parity bits are converted into parallel data according to the number of bits of a data bus, and are output in synchronization with the external clock. 7. The semiconductor memory device according to claim 5, further comprising a parallel conversion circuit, wherein the parity bit output control circuit sends an output of the serial / parallel conversion circuit to the data bus after a burst write period ends. . 8. The serial-parallel conversion circuit has a plurality of flip-flops directly connected, and a first-stage flip-flop latches a parity bit generated by the parity bit generation circuit based on the external clock, 8. The semiconductor memory device according to claim 7, wherein the flip-flops other than the first stage latch the output of the preceding flip-flop based on the external clock. 9. The serial-parallel conversion circuit according to claim 1, wherein when the number of parity bits equal to or more than the number of output bits of the serial-parallel conversion circuit is input, the parity bits are replaced by new parity bits in order from an old parity bit. Item 9. The semiconductor memory device according to item 7 or 8.