JP2000010850A - Memory access system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a sure memory access when data are determined. SOLUTION: A memory access detecting circuit 4 detects a variation of data on a data bus 10 and generates a ready signal (RDY) 70. In response to this generated ready signal 70, an I/O device 1 takes in the data on the data bus 10. Even when the data on the data bus 10 has no variation, the ready signal 70 is generated and in response to the generated ready signal 70, the I/O device 1 takes in the data on the data bus 10. The active state of the ready signal 70 is continued up to rising timing up to two clocks later and when a command signal becomes inactive, the active state is finished to effectively prevent illegal access. Even when the data to not vary, since the ready signal 70 is generated, a sure memory access can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access system, and more particularly to an access method for an external storage circuit.

[0002]

2. Description of the Related Art Conventionally, a CPU (Central Pro
A peripheral circuit (hereinafter abbreviated as a peripheral circuit) is provided in order for a sessing unit to access an external storage circuit (hereinafter abbreviated as a memory circuit) such as an asynchronous memory circuit. This peripheral circuit has generated a ready signal for terminating the CPU's access to the memory circuit.

As a technique of the peripheral circuit, a circuit technique considering two characteristics is required. One is a circuit technology in consideration of memory access characteristics such as data write time and read time, which are held by various memory circuits. The other is a circuit technology that takes into account the delay characteristics of the logic element circuit that constitutes the peripheral circuit.

Here, since the characteristics of the memory circuit are disclosed in device data books of various memory circuits and the like,
It is known. The characteristics of the element delay are also known because they are disclosed in device data books of various logic element circuits.

[0005] The access time of the CPU is determined by the memory access characteristic and the element delay characteristic. Therefore, it has a timing specification of the peripheral circuit in consideration of the maximum delay time of the delay characteristic. FIG. 8 is a block diagram showing a configuration example of a memory access system for accessing a conventional asynchronous memory.

An address signal, a write signal 30, a read signal 40, and an operation clock (CLK) 60 output from the I / O device 1 to the address bus 20 are memory access peripheral circuits for generating control signals for performing memory access. 3 is input.

The general-purpose memory 2 includes an address signal output from the I / O device 1 to the address bus 20, a write signal 30 and a read signal 40, and the I / O device 1
And a chip select signal (Chip Select) output from the memory access peripheral circuit 3 and enabling the memory.
t; CS) 50 is input. The ready signal output from the memory access peripheral circuit 3 is input to the I / O device 1. This ready signal (Ready; RDY) 7
0 is a signal for ending the memory access.
At the time of the read operation, it has a function of taking in data at the rising edge of the operation clock when the ready signal becomes active.

A detailed circuit example of the memory access peripheral circuit 3 is shown in FIG. A memory access peripheral circuit 3 for generating a control signal for performing a memory access decodes an address bus and activates a chip select signal when an address for the general-purpose memory 2 shown in FIG. A flip-flop circuit 3b for activating the select signal at the rising edge of the clock, and a chip select signal for generating the pulse signal and an output of the flip-flop circuit 3b
And an R element 3d. Then, the output of the OR element 3d is transmitted as a ready signal. In order to output a ready signal from the flip-flop circuit 3b only during a read operation or a write operation, a read signal and a write signal are input to the NAND element 3c,
The output is input to the reset terminal of the flip-flop circuit 3b.

FIG. 10 shows an example of a timing at the time of a read operation when this circuit is used. I in FIG.
In synchronization with the operation clock output from the / O device 1, a read signal and an address for accessing the general-purpose memory 2 in FIG. 8 are output from the address bus. These synchronization signals are output with a certain delay, though they are also affected by the performance of the I / O device 1 in FIG. When this address is input to the decode circuit 3a, a chip select signal is output.

Similarly, the chip select signal further delays after the address is output due to a logic circuit element delay of the decode circuit 3a and a wiring delay between the I / O device 1 and the decode circuit 3a in FIG. Will be output. The pulsed ready signal from the chip select signal to the next clock rise is the I / O signal of FIG.
Output to device 1.

The data is output from the general-purpose memory 2 shown in FIG. 8 after a certain period of time after the active state of the chip select signal is input to the general-purpose memory 2 shown in FIG. The certain time is a time determined by the performance of the general-purpose memory 2 in FIG.

FIG. 11 is a diagram showing the operation when the same circuit is used. In particular, FIG. 11 shows an example of the timing when the operation clock is fast or the performance of each device used is inferior. In this example, the chip select signal output from the decode circuit 3a does not catch up with the rise of the first clock after the I / O device 1 in FIG. 8
Is output to the I / O device 1. If the output timing of the chip select is immediately before the rising edge of the clock, the active time of the ready signal becomes very short, and illegal access may occur.

When it is necessary to prevent such unauthorized access, a circuit configuration having n stages of flip-flop circuits as shown in FIG. 12 is used, and the ready signal always has a length of one clock. Needed to be a pulse signal.

[0014]

In the above-mentioned prior art, in the circuit design of an asynchronous memory without a system clock, the access is expected after the access is started due to the access speed of each device itself, the delay of the logic circuit element, and the wiring delay. I do not know the exact time until the output data is output. For this reason, in the case of the circuit configuration shown in FIG. 9, if the chip select signal is output immediately before the rise of the clock, the access may be illegal or the expected data cannot be read. Disadvantage.

In order to address this disadvantage, FIG.
A circuit configuration as shown in FIG. However, this circuit configuration has a drawback that only one clock wait can be reliably accessed, which hinders an increase in access speed.

The prior art described in Japanese Patent Application Laid-Open No. H8-17182 relates to a latch circuit and cannot solve the above-mentioned disadvantages of the prior art.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object of the present invention is to output a ready signal when data is determined, thereby enabling reliable memory access and achieving high speed. It is to provide a memory access system capable of performing such operations.

[0018]

A memory access system according to the present invention is a memory access system which takes in data read from a memory onto a data bus. Data change detecting means for detecting a change in the data, and data taking means for taking in data on the data bus in response to the detection of the data change.

In another memory access system according to the present invention, there is provided a data-unchanged-ready generation means for outputting the ready signal in response to an input of an address input to access the memory; It further comprises a selector for selectively inputting a ready signal output from the detection means and the ready signal when the data does not change to the data acquisition means.

In order to achieve the above object, the present system detects a data change point and outputs a ready signal.
More specifically, it latches data when the chip select signal is output, compares the latched data with the output signal, and outputs a ready signal.

Further, the apparatus has a function of preventing unauthorized access even when a data change point is detected immediately before the rise of the clock and a ready signal is output. Specifically, the active state of the ready signal output immediately before the rising of the clock is held until the next clock, and when the read signal is completed, the ready signal is made inactive, thereby making the ready signal illegal. Prevent access.

If there is no change point in data for a certain period of time, a ready signal output from the above-described conventional ready signal generation circuit is selected.

In the present system, by taking in a bidirectional data signal between the I / O device and the general-purpose memory into the memory access detection circuit, the time at which expected data is determined is compared with the data before determination. It is detected by this. For this reason, there is no need to design a circuit by guessing on a desk, and it is not necessary to design with a margin in consideration of a logic circuit element delay and a wiring delay.

Further, for a ready signal output immediately before the rising edge of the clock, the signal is kept active until the next rising edge of the clock to determine whether or not the data receiving device itself has received the data. As a result, unauthorized access can be prevented.

[0025]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same reference numerals are given to the same parts as those in the other drawings.

FIG. 2 is a block diagram showing an embodiment of the memory access system according to the present invention. As shown in the figure, in the present system, a data bus 10 is connected to a memory access detection circuit 4, and a bidirectional data signal between the I / O device 1 and the general-purpose memory 2 is fetched. . Then, the time (timing) at which the expected data is determined is detected by comparing with the data before the determination. Therefore, it is not necessary to design a circuit by guessing on a desk, and it is not necessary to design a circuit with a margin in consideration of a logic circuit element delay and a wiring delay.

Also for a ready signal output immediately before the rising edge of the clock, the signal is kept active until the next rising edge of the clock so that the device receiving the data can determine whether or not the data has been received. That is, unauthorized access can be prevented.

Next, the memory access detection circuit 4 shown in FIG.
Will be described in detail with reference to FIG.

Referring to FIG. 3, a memory access detection circuit 4 includes a decode circuit 40 for decoding an address bus.
1, a data-unchanged ready generation circuit 402 that generates a ready signal when the data bus has not changed, a data-change-point detection ready generation circuit 403 that detects a data change point and generates a ready signal, A command status output circuit 404 for detecting that a command for accessing the memory has been generated, and an output selector circuit 405 for selecting a ready signal from the data-unchanged ready generation circuit 402 and the data-change-point detection ready generation circuit 403. It is composed of

The decoding circuit 401 is constituted by a logic element which receives an address on an address bus as an input, decodes the address and outputs the decoded address.

The command state output circuit 404 is composed of a logic element which receives a write signal and a read signal.

The output of the decode circuit 401, the output of the command status output circuit 404, and the operation clock are input to the ready data generation circuit 402 when no data changes. This circuit 4
02 is composed of a flip-flop circuit and a logic element as described later. The output of the decode circuit 401, the output of the command state output circuit 404, the data bus, and the operation clock are input to the data change point detection ready generation circuit 403. The circuit 403 includes a latch circuit, a comparison circuit, a flip-flop circuit, and a logic element, as described later. The data-unchanged ready generation circuit 402 and the data change point detection ready generation circuit 403 operate in synchronization with the level transition timing of the clock 60.

The output selector circuit 405 is composed of a logic element as described later.

Next, the operation of the present invention will be described in detail with reference to FIG.

The decode circuit 401 receives an address bus output from the I / O device 1 of FIG. 1 as an input, and outputs a chip select signal when an address for the general-purpose memory 2 of FIG. 1 is input.

The command state output circuit 404 outputs a signal for enabling the ready generation circuit to operate only during a command operation during a read operation or a write operation.

Data change point detection ready generation circuit 403
Receives a signal of a bidirectional data bus 10 between the I / O device 1 and the general-purpose memory 2 of FIG.
Latch is triggered by the moment when the output signal 01 becomes active. Here, the latched signal is compared with the current signal on the data bus 10 to output an active signal at a change point. Also, when this change point is output immediately before the rising edge of the clock, in order to prevent unauthorized access, this active signal is pulsed and output until the next rising edge of the clock. Further, the active signal becomes an inactive state at the time when the command is completed according to the command state signal from the command state output circuit 404.

The data-unchanged ready generation circuit 402
If the data change point detection ready generation circuit 403 does not output an active signal for a certain period of time, it outputs an active signal instead.

The output selector circuit 405, among the outputs from the data change point detection ready generation circuit 403 and the data non-change ready generation circuit 402, activates the previously active signal to the I / O device 1 in FIG. Output as a signal.

[0040]

Next, a more specific embodiment of the present system will be described in detail with reference to FIG. Referring to the figure, the memory access detection circuit 4 in the present memory access system includes a decode circuit 4a, a data invariable ready generation circuit 402 including flip-flop circuits 4b and 4e and an OR element 4d, and a latch circuit (LAT).
4f, comparison circuit 4g, flip-flop circuits 4h and 4
i, and a data change point detection ready generation circuit 403 comprising a NAND element 4j, and an AN serving as an output selector circuit.
It is configured to include a D element 4k, a NAND element 4c serving as a command state output circuit, and a NOT element 41.

Here, an example of the internal configuration of the comparison circuit 4g is shown in FIG.
Is shown in Referring to the figure, the comparison circuit 4g has E
XOR element (exclusive OR circuit) 4ga, 4gb, 4g
c, 4gd, 4ge, 4gf, 4gg, 4gh and 4g
i and an 8OR element 4gj. In such a configuration, EXOR elements 4ga to 4gi are provided corresponding to the data latched by the latch circuit 4f in FIG. 3 and each bit forming the data on the data bus. Is detected.

Returning to FIG. 3, the decoding circuit 4a is a circuit which receives an address on the address bus output from the I / O device 1 of FIG. 1 as an input and decodes it.

The NAND element 4c receives a write signal and a read signal output from the I / O device 1 of FIG. 1 as inputs, and the output is input to the set terminal of the flip-flop circuit.

The flip-flop circuit 4b outputs the output from the decode circuit 4a as a signal synchronized with the clock. The flip-flop circuit 4e at the next stage holds the output signal in an active state until the next clock rises. The OR element 4d is a first-stage flip-flop circuit 4
The output b and the inverted logic output of the second-stage flip-flop circuit 4e are input and output to the AND element 4k.

The latch circuit 4f inverts the output from the decode circuit 4a by the NOT element 41 and uses the inverted signal as a trigger to generate a bidirectional data bus signal between the I / O device 1 and the general-purpose memory 2 in FIG. Latch. The comparison circuit 4g
The output data of the latch circuit 4f and the data on the data bus are input, and the two data are compared for each constituting bit.

The flip-flop circuit 4h includes the comparison circuit 4
The output from g is output as a signal synchronized with the clock, and the next-stage flip-flop circuit 4i holds the output signal in an active state until the rise of the next clock. NAND
The element 4j receives the output from the comparison circuit 4g and the inverted logic output of the second flip-flop, and
k.

The AND element 4k receives the output of the OR element 4d and the output of the NAND element 4j, and the output is input to the I / O device 1 in FIG.

The operation of the memory access system according to this embodiment having the above configuration will be described in detail. Referring to FIG. 3, the decode circuit 4a receives an address bus output from the I / O device 1 of FIG. 1 as an input, and outputs a chip select signal 50 when an address to the general-purpose memory 2 of FIG. 1 is input. .

The NAND element 4c receives the write signal 30 and the read signal 40 as inputs, and outputs a signal for enabling the ready generation circuits 402 and 403 to operate only during a read operation or a command operation during a write operation. .

The output signal of decode circuit 4a of FIG.
It is inverted by the T element 41. The latch circuit 4f uses this signal as a trigger to latch a bidirectional data bus signal between the I / O device 1 and the general-purpose memory 2. Comparison circuit 4g
Compares the signal latched by the latch circuit 4f with the data bus signal. Then, an active signal is output at a change point (change timing) of the comparison result.

The flip-flop circuit 4h is connected to the comparison circuit 4
g is output as a signal synchronized with the clock. Also, the flip-flop circuit 4i holds and outputs the active signal until the next rising edge of the clock in order to prevent unauthorized access even when this change point is output immediately before the rising edge of the clock. NAND
The circuit 4j receives the output from the comparison circuit 4g and the inverted logic output of the flip-flop circuit of the second stage as inputs, and outputs a pulse. Further, the active signal becomes an inactive state at the time when the command is completed by the command state signal from the NAND element 4c.

The flip-flop circuit 4b receives a chip select signal 50, which is an output signal of the decode circuit 4a, as an input. The flip-flop circuit 4b operates when a data change point cannot be detected, and outputs the chip select signal 50 in synchronization with the clock 60. The flip-flop circuit 4e at the next stage holds the active state of the output signal until the next clock rise. The OR element 4d receives the output of the first-stage flip-flop circuit 4b and the inverted logic output of the second-stage flip-flop circuit as inputs, and outputs a pulse.

The AND element 4k receives the output of the NAND element 4j and the output of the OR element 4d as inputs, and outputs the previously activated signal to the I / O device 1 of FIG. 1 as a ready signal.

FIG. 5 is a timing chart showing the circuit operation of FIG. In FIG.
One cycle of the LK60, that is, the time from the transition timing of the pulse T1 to the transition timing of the pulse T2 is t1.

A read signal and an address for accessing the general-purpose memory 2 are output from an address bus in synchronization with an operation clock output from the I / O device 1 of FIG. These synchronization signals are output with a certain delay, depending on the performance of the I / O device 1 in FIG.

The address 20 is input to the decode circuit 4a, and a chip select signal 50 is output. Similarly, the chip select signal 50 is output with a further delay after the address is output due to the element delay of the decode circuit 4a and the wiring delay between the I / O device 1 and the decode circuit 4a in FIG. . The chip select signal 50 is used as a trigger to latch the data 10 on the data bus. The latched data and the data on the data bus are compared by the comparison circuit 4g.

The ready signal 70 is a pulse which goes into an active state (low level) from the point where the data has changed, and which keeps the active state until the rising timing of the clock after a maximum of two clocks. However, the active state of the ready signal 70 ends when the read signal 40 ends. Therefore, when the read signal becomes inactive, the ready signal becomes inactive (high level) after the element delay and the wiring delay, and one command cycle ends.

FIG. 6 is a timing chart showing the circuit operation of FIG. In particular, this is an example where the operation clock is fast or the access time of each device used is long. One cycle of the clock CLK60, that is, the time from the transition timing of the pulse T1 to the transition timing of the pulse T2 is t2, and t1> t2.

In the figure, the data change point is located near the rising edge of the clock, but the read command ends in synchronization with the rising edge of the clock. Therefore, at this timing, the I / O device 1 in FIG. 1 reads data.

FIG. 7 is a timing chart showing the circuit operation of FIG. In particular, this is an example where the operation clock is fast or the access time of each device used is long. One cycle of the clock CLK60, that is, the time from the transition timing of the pulse T1 to the transition timing of the pulse T2 is t2, and t1> t3.

In the figure, the data change point is located near the rising edge of the clock, but the read command ends in synchronization with the rising edge of the clock following the clock. For this reason, the I / O device 1 in FIG. 1 cannot read data at the rising edge of the clock near the data change point, but reads at the next rising edge of the clock.

As described above, according to the present system, the ready signal is output when the memory actually outputs the expected data in order to detect the data change point and output the ready signal. The access time according to the performance of each used device can be achieved.

In addition, since the active state of the ready signal is continued until the rising timing after a maximum of two clocks, and the active state is terminated when the command signal becomes inactive, illegal access can be effectively prevented. it can. On the other hand, when the data has not changed, the conventional ready circuit operates. Therefore, according to the present system, reliable memory access can be realized.

The present invention can take the following aspects in connection with the description of the claims.

(1) The memory access system according to any one of claims 1 to 6, wherein the memory and the data fetch means operate asynchronously.

(2) The memory further includes a decoding circuit for decoding the address, wherein the memory is selected by the decoded output.
7. The memory access system according to any one of claims 6 to 6.

[0067]

As described above, the present invention detects a change in the data on the data bus, generates a ready signal, and takes in the data in response to the generated ready signal. It is possible to access when it is determined, and it is possible to effectively prevent unauthorized access. Even when the data does not change, the generation of the ready signal has an effect that a reliable memory access can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a memory access system of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory access detection circuit in FIG.

FIG. 3 is a block diagram showing a more detailed configuration example of a memory access detection circuit in FIG. 2;

FIG. 4 is a diagram illustrating a configuration example of a comparison circuit in FIG. 3;

FIG. 5 is a first time chart illustrating an operation example of the memory access circuit illustrated in FIG. 3;

FIG. 6 is a second time chart showing an operation example of the memory access circuit shown in FIG. 3;

FIG. 7 is a third time chart illustrating an operation example of the memory access circuit illustrated in FIG. 3;

FIG. 8 is an overall block diagram for accessing a conventional asynchronous memory.

FIG. 9 is a first configuration example of a conventional memory access peripheral circuit.

10 is a first example showing an operation example of the circuit shown in FIG. 9;
It is a time chart.

FIG. 11 shows a second example of the operation of the circuit shown in FIG.
It is a time chart.

FIG. 12 is a second configuration example of a conventional memory access peripheral circuit.

[Explanation of symbols]

Reference Signs List 1 I / O device 2 General-purpose memory 3, 4 Memory access peripheral circuit 3a, 4a, 401 Decoding circuit 3b, 3e, 4b, 4e, 4h, 4i Flip-flop circuit 3c, 4c, 4j NAND element 3d, 4d OR element 4g Comparison Circuit 4k AND element 4l NOT element 4ga to 4gi EXOR element 4gj 8-input OR element 402 Ready generation circuit when data does not change 403 Data change point detection ready circuit 404 Command status output circuit 405 Output selector circuit CLK Operation clock CS Chip select signal RDY ready Signal F / F flip-flop circuit

Claims (6)

[Claims] 1. A memory access system for taking in data read from a memory onto a data bus, comprising: a data change detecting means for detecting a change in data on the data bus at each clock transition timing of the system. A data fetching means for fetching data on the data bus in response to the detection of the data change. 2. The data change detection means outputs a ready signal indicating the change in response to the detection of the data change, and the data fetch means reads data on the data bus in response to the ready signal. 2. The memory access system according to claim 1, wherein the data is fetched. 3. The data-unchanged ready generation means for outputting the ready signal in response to the input of an address input for accessing the memory, the data change detection means and the data-unchanged ready generation. 3. The memory access system according to claim 2, further comprising: a selector for selectively inputting a ready signal output from each of the means to the data fetching means. 4. The data change detecting means includes: a latch circuit for latching data on the data bus in response to the input of the address; and a latch circuit for latching data latched by the latch circuit and data on the data bus. 4. The memory access system according to claim 3, further comprising: a comparison circuit for performing comparison; and a ready signal generation circuit that outputs the ready signal when the comparison result indicates a mismatch. 5. An exclusive OR circuit provided in correspondence with data latched by the latch circuit and each bit constituting data on the data bus, and having the corresponding bits as inputs. The memory access system according to claim 4, comprising: 6. A first flip-flop for holding the comparison result at a transition timing of the clock, and a ready signal for holding the output of the first flip-flop at a transition timing of the clock. 6. The flip-flop according to claim 4, wherein the ready signal is output in accordance with an input of the first flip-flop and an output of the second flip-flop.
A memory access system as described.