JPH01171191A - Storage element with arithmetic function - Google Patents

Abstract

PURPOSE:To shorten a time necessary for an arithmetic processing by providing a means to send an arithmetic control signal based on a control signal inputted from a control signal input terminal. CONSTITUTION:At the time of executing the arithmetic processing to data stored into a storing means 33, an address signal is sent fan external part through an address signal input terminal 32 to the storing means 33 and a transfer and arithmetic means 35, simultaneously, the control signal is sent through a control signal input terminal 36 to a control means 37, and further, arithmetic data are sent through a data signal input/output terminal 34 to the transfer and arithmetic means 35. The control means 37 sends a transfer and operation control signal to the transfer and arithmetic means 35 based on the control signal, the storing means 33 reads the data stored in an area based on the address signal, and the data are sent to the transfer and arithmetic means 35. Since, in such a way, only by sending the address signal, data signal and control signal to a storage element 31 having an arithmetic function, the arithmetic processing is automatically executed, the time necessary for the arithmetic processing can be widely shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory element with an arithmetic function used for storing data in a computer or the like.

[Conventional technology]

Conventional memory element (RAM-Random Access
ss Me+w.

ry) 11 includes, for example, as shown in FIG. 8, a storage means 13 to which an address signal is supplied from an address signal input terminal 12, a transfer means 15 connected to a data signal input/output terminal 14, and a control signal input terminal 16. A control means 17 is provided for controlling the storage means 13 and the transfer means 15 based on control signals inputted from the controller.

The storage means 13 is configured to write and read data into and from an area based on an address signal input from the address signal input terminal 12. Further, the transfer means 15 includes the data signal input/output terminal 14 and the storage means 13.
Data is transferred between the two.

Such a storage element 11 includes, for example, a data register 23 connected to a data signal input/output terminal 22 and a calculation unit 24.
, an address register 26 connected to an address signal output terminal 25, and a control section 28 connected to a control signal output terminal 27.
Processing Unit) 21, etc., and is used to perform various data processing.

In particular, arithmetic processing such as logical product, logical sum, and exclusive logical sum of the data stored in the storage means 13 of the storage element 11 and the data held in the data register 23 of the CPU 21 is performed relatively frequently. In this case, the memory element 11 and C
In the PU 21, the following operations are performed, for example, by program processing.

First, an address signal is outputted from the address register 26 of the CPU 21 to the storage means 13 of the storage element 11, and a read command signal is outputted from the control section 28 of the CPU 21 to the control means 17 of the storage element 11. Therefore, the data stored in the storage means 13 of the storage element 11 is read out and transferred to the data register 2 of the CPU 21 via the transfer means 15.
Sent to 3.

The data sent to the data register 23 is sent to the calculation unit 2 along with the data held in the data register 23 in advance.
4, the calculation is performed, and the calculation result is returned to the data register 23.

Next, an address signal is outputted from the address register 26 of the CPU 21 to the storage means 13 of the storage element 11, and a write command signal is outputted from the control section 28 of the CPU 21 to the control means 17 of the storage element 11. Therefore,
The calculation result of the data register 23 is sent to the storage means 13 via the transfer means 15 of the storage element 11 and written therein.

In this way, various calculations have been performed by utilizing the calculation functions of the CPU 21 and the like through program processing, for example.

[Problem that the invention seeks to solve]

However, in the above-mentioned conventional storage element, each time arithmetic processing is performed, data is read from the storage means 13 and the CPU 2
This requires a series of operations such as calculation using 1st grade, and writing the calculation result to the storage means 13. Furthermore, since this type of arithmetic processing is performed relatively frequently, there has been a problem in that a long time is spent on the arithmetic processing in general.

Furthermore, since the CPU 21 and the like are solely engaged in arithmetic processing from the time when data is read from the storage means 13 to the time when the calculation result is written, there is a problem in that a large burden is placed on the CPU 21 and the like.

[Means for solving problems]

In order to solve the above-mentioned problems, the memory element with an arithmetic function according to the present invention includes a storage means for writing and reading data in an area based on an address signal input from an address signal input terminal, and an address signal input terminal. Data is transferred between the storage means and the data signal input/output terminal based on the data signal input/output terminal and the data read out from the storage means based on the data signal input/output terminal and the data signal input/output terminal. a transfer/calculation means for calculating the data and sending it to the storage means; and a control means for sending a transfer/calculation control signal to the transfer/calculation means based on a control signal input from the control signal input terminal. It is characterized by being provided with.

[For production]

With the above configuration, when performing arithmetic processing on data stored in the storage means, an address signal is sent from the outside to the storage means and the transfer/calculation means via the address signal input terminal, and an address signal is sent from the outside to the storage means and the transfer/arithmetic means via the control signal input terminal. A control signal is sent to the control means via the data signal input/output terminal, and calculation data is sent to the transfer/calculation means via the data signal input/output terminal.

Then, the control means sends a transfer/calculation control signal to the transfer/calculation means based on the control signal, and the storage means reads out the data stored in the area based on the address signal and sends it to the transfer/calculation means.

Therefore, the transfer/calculation means performs the calculation specified by the address signal on the data sent from the storage means and the data sent via the data signal input/output terminal.

The calculation result is sent from the transfer/calculation means to the storage means and written into the area based on the address signal, and the calculation process is completed.

In this way, simply by sending address signals, data signals, and control signals to the memory element with arithmetic functions, arithmetic processing is automatically performed, so that the time required for arithmetic processing can be significantly reduced.

Moreover, the CPU, etc. that sends address signals, data signals, and control signals to the memory element with arithmetic functions only needs to output these signals once, so the burden on the CPU, etc. is greatly reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 7.

Memory element with arithmetic function (RAM-Random Ac
As shown in FIG. 1, cessMemory 31 is an example of a storage element that performs calculations and storage on 1-bit data. Output terminal 3
Transfer/calculation means 35 is connected to 4 and is supplied with an address signal specifying transfer/calculation, and the transfer/calculation means 35 is connected to the transfer/calculation means 35 based on a control signal inputted from a control signal input terminal 36. A control means 37 for sending a control signal is provided.

The storage means 33 is connected to the transfer/calculation means 35 via a write data line 38 and a read data line 39. The storage means 33 writes the data sent from the transfer/calculation means 35 via the write data line 38 to an area based on the address signal input from the address signal input terminal 32, and reads the written data to the read data line. 39 to the transfer/calculation means 35.

Further, the transfer/calculation means 35 transfers data between the storage means 33 and the data signal input/output terminal 34 based on the address signal and the transfer/calculation control signal. An operation specified by an address signal is performed on the data inputted from the storage means 33 and the data read from the storage means 33, and the operation result is sent to the storage means 33.

More specifically, the memory element with arithmetic function 31 can be configured by a circuit as shown in FIG. 2, for example.

That is, the storage means 33 is provided with a memory cell array 33a having a 1-bit input terminal and an output terminal.

Of the address signals A o to A i input from the address signal input terminal 32, n+1 bit address signals of A0 to A, l are input to this memory cell array 33a.
It is designed to be input via an address decoder 33b.

An output terminal of the memory cell array 33a is connected via a read data line 39 to an input terminal of a three-state buffer 35a of the transfer/calculation means 35 and a data terminal of a launch circuit 35b. three state buffer 3
The output terminal of 5a is connected to the data signal input/output terminal 34. Further, the output terminal of the launch circuit 35b is connected to an AND circuit 35c, an OR circuit 35d, and an XOR circuit 35e that perform logical operations.

A data signal input from the data signal input/output terminal 34 is further input to the AND circuit 35c, the OR circuit 35d1, and the XOR circuit 35e via the three-state buffer 35g. The three-state buffer 135g is also a three-state buffer 35f.
is also connected.

The above AND circuit 35c, OR circuit 35d, and XOR circuit 3
5e and the output terminals of the three-state buffer 35f are connected to each other and to the input terminal of the memory cell array 33a in the storage means 33.

Further, among the address signals inputted from the address signal input terminal 32, 3-bit address signals A□1 to ARo3, which specify the presence or absence of logical operation and the type thereof, are sent to an AND circuit 35C and an OR circuit 35d1, respectively. and X
While connected to the gate terminal of the OR circuit 35e, both are connected to the NOR circuit 35h. NOR circuit 35h
is connected to the gate terminal of the three-state buffer 35f. , That is, as shown in FIG. 3, A7+1 to A7. .

When any one of the 3-bit address signals is at high level, it becomes high level.

Any one of the AND circuit 35c, OR circuit 35d1, and XOR circuit 356 corresponding to the bit being turned on is turned on, and an AND, OR, or exclusive OR operation is performed. Also, A h + I-A
. .

On the other hand, the control means 37 receives a clock signal (CK), a chip select signal (C8), and a write enable (W
E) The control signals of the signals are respectively connected to the control signal input terminals 36.
It is designed to be input via...

The above clock signal is directly sent to the clock terminal of the latch circuit 35b in the transfer/calculation means 35.

It is now entered. Both the chip select signal and the write enable signal are connected to a negative logic NAND circuit 37a and a gate 37b. This gate 37b is activated when the chip select signal is at a low level.
Moreover, when the read/write signal is at a high level, a high level signal is output.

The outputs of the negative logic NAND circuit 37a and the gate 37b constitute a transfer/calculation control signal, and each
Three-state buffer 3 in transfer/calculation means 35
5g1 and the gate terminal of the three-state buffer 35a.

For example, as shown in FIG. 4, m memory elements 31 with arithmetic functions as described above are provided to constitute an m-bit memory device 51 with arithmetic functions, and a CPU (Central Pr
processing unit) 41 to perform various data processing.

That is, the m-bit data of D, -D, is configured to be stored one bit at a time in the storage element with arithmetic function 31, . . . .

The cpυ 41 includes a data register 43 connected to the data signal input/output terminal 42, an arithmetic unit 44 connected to the data register 43 to perform data calculations, an address register 46 connected to the address signal output terminal 45, and a control unit 44 connected to the data signal input/output terminal 42. A control section 48 is provided which is connected to the signal output terminal 47 and controls the data register 43, arithmetic section 44, address register 46, and the like.

In the above configuration, the data register 43 of the CPU 41
When writing data held in the memory device 33 of the memory element 31 with arithmetic function, the following operation is performed.

First, as shown in FIG.
o ”” A i is output. At this time, the 3-bit address signals A, l+1 ""A□, are all at low level, and the three-state buffer 3
5f becomes ON state.

Further, the control section 48 of the CPU 41 outputs a write command signal to the control means 37 of the memory element 31 with arithmetic function. That is, the chip select signal becomes low level, and subsequently the write enable signal becomes low level.

Therefore, since the three-state buffer 35g is turned on, the data signal sent from the data register 43 of the CPU 41 is transmitted to the memory of the storage means 33 via the three-state buffers 35g and 35f of the transfer/calculation means 35 and the write data line 38. The signal is sent to the cell array 33a and written into the area based on the address signals A0-A, .

On the other hand, when data written in the storage means 33 of the storage element with arithmetic function 31 is read out and sent to the data register 43 of the CPU 41, the following operation is performed.

First, as in the case of the write operation described above, as shown in FIG. 6, address signals A6 to A are output from the address register 46 of the CPU 41 to the memory element with arithmetic function 31. Further, the control section 48 of the CPU 41 outputs a read command signal to the control means 37 of the memory element 31 with arithmetic function. In other words, the chip select signal becomes low level, but the write enable signal remains high level.

Therefore, since the three-state buffer 35a is turned on, the data written in the area based on the address signals A0 to A, 1 in the memory cell array 33a of the storage means 33 is transferred via the read data line 39 and the three-state buffer 35a. The data is sent to the data register 43 of the CPU 41.

In addition, when performing arithmetic processing such as logical product, logical sum, and exclusive logical sum between the data stored in the storage means 33 of the storage element 31 and the data held in the data register 43 of the CPU 41, The functional memory element 31 and the CPU 41 perform the following operations.

First, as shown in FIG. 7, address signals A0 to At are output from the address register 46 of the CPU 41 to the storage means 33 of the storage element 31 with arithmetic function. At this time, only one bit of the 3-bit address signals A n+ 1 to A□ is at a high level, and accordingly, either the AND circuit 35C1, the OR circuit 35d1 or the XOR circuit 35e is in the ON state. become.

Further, the control unit 48 of the CPU 41 outputs a calculation command signal to the control means 37 of the storage element 31 with calculation function.

That is, after the chip select signal becomes low level and the clock signal subsequently becomes low level, the write enable signal becomes low level.

Then, when the clock signal becomes low level, the address signal A of the memory cell array 33a.

~A, and read data line 3
9 is latched by the latch circuit 35b, and sent to the AND circuit 35C, the OR circuit 35d, and the XOR circuit 35e. Also, when the write enable signal goes low level, the three-state buffer 3
5g becomes ON state, data register 4 of CPU 41
The data signal sent from 3 is also connected to AND circuit 35c and OR circuit 35c.
The signal is sent to a circuit 35d and an XOR circuit 35e.

Sokote, AND circuit 35c, OR circuit 35d1 and X
Among the OR circuits 35e, the output of the circuit that is in the ON state is sent to the memory cell array 33a of the storage means 33 via the write data line 38, and the address signals A0 to A are sent to the memory cell array 33a of the storage means 33.
, 1 is written again, and the arithmetic processing ends.

As a result, for example, the data r5A (hexadecimal) written at the address ``rob (hexadecimal)'' in the storage means 33 of the storage element 31 with arithmetic function, and the CP
Data r held in data register 43 of U41
69 (hexadecimal number)", the address signal r100 (hexadecimal number)" is calculated from the address register 46, data register 43, and control unit 48 of the CPU 41, respectively. By simply outputting the data signal r69 (hexadecimal number) and control signals such as a clock signal, a chip select signal, and a write enable signal,
48 (hexadecimal number) is written to "rob (address 16)" at "rob (address 16)".

〔Effect of the invention〕

As described above, the memory element with an arithmetic function according to the present invention includes a storage means for writing and successively outputting data in an area based on an address signal input from an address signal input terminal, and an address signal and a transfer/operation. Based on the control signal and
While transferring data between the storage means and the data signal input/output terminal, the data input from the data signal input/output terminal and the data read from the storage means are calculated and transferred to the storage means. The configuration is provided with a transfer/calculation means for sending out a signal, and a control means for sending a transfer/calculation control signal to the transfer/calculation means based on a control signal input from a control signal input terminal.

As a result, arithmetic processing is automatically performed simply by sending an address signal, a data signal, and a control signal to the memory element with arithmetic functions, so that the time required for arithmetic processing can be significantly shortened.

Moreover, since the CPU, etc. that sends address signals, data signals, and control signals to the memory element with arithmetic function only needs to output these signals once, there is an effect that the burden on the CPU, etc. is significantly reduced.

[Brief explanation of the drawing]

1 to 7 show an embodiment of the present invention, in which FIG. 1 is a block diagram showing the configuration of a memory element with an arithmetic function, and FIG. 2 shows a specific example of the memory element with an arithmetic function. A circuit diagram showing a circuit example, FIG. 3 is an explanatory diagram showing the structure of an address signal, and FIG. 4 is an example in which an m-bit arithmetic function storage device consisting of m arithmetic function storage elements is connected to a CPU. 5 is a timing chart showing the operation of each part when writing data to a memory element with an arithmetic function, and FIG. 6 is a timing chart showing the operation of each part when reading data from a memory element with an arithmetic function. , FIG. 7 is a timing chart showing the operation of each part when performing arithmetic processing. FIG. 8 shows a conventional example, and is a block diagram showing the configuration of a conventional memory element and an example in which the conventional memory element is connected to a CPU. 31 is a storage element with an arithmetic function, 32 is an address signal input terminal, 33 is a storage means, 34 is a data signal input/output terminal, 3
5 is a transfer/calculation means, 36 is a control signal input terminal, and 37 is a control means. Figure 5 Thin Figure 6 Figure 17 E

Claims (1)

[Claims] 1. Storage means for writing and reading data in an area based on an address signal input from an address signal input terminal; While transferring data between the means and the data signal input/output terminal, the data input from the data signal input/output terminal and the data read from the storage means are calculated and sent to the storage means. Based on the control signal input from the transfer/calculation means and the control signal input terminal,
A memory element with an arithmetic function, characterized in that the above-mentioned transfer/arithmetic means is provided with a control means for sending out a transfer/arithmetic control signal.