JPS59132376A - Test pattern reading control system - Google Patents

Abstract

PURPOSE:To enable the addressing and the sequential reading for a test pattern based on a sequence information read out by memorizing into a separate sequence information memory the sequence information on reading out the test pattern in the form of a specified compressed address. CONSTITUTION:Only information required to successively generate addresses of test patterns is memorized into a sequence memory as sequence information in the form of a compressed address. This address corresponds to the address of the test pattern one for one. The symbol l indicates information in the form of a compressed address and, for example, continuous sequence information NOP is represented by single sequence information NOP until. Therefore, as the memory capacity of the sequency information in the form of a compressed address can be reduced drastically, a small and fast memory can be used for the sequence information memory to separate it from a memory for storing test patterns thereby ensuring a high speed operation and a high economy.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to integrated circuits (IC, LSI) and memories.

A test device (e.g., logic tester, memory tester) that inputs a logic test pattern into a digital circuit such as a microcomputer, performs a comparison test to see whether the logic output matches the expected value pattern, and determines the acceptability of the circuit under test. ) relates to a test pattern readout control system that can efficiently read and generate a large number of test patterns.

[Prior art]

Generally, in this type of test equipment, tests are performed by repeatedly inputting the test pattern stored in the pattern memory into the circuit under test. Along with the pattern, sequence information that defines the reading order is stored in the pattern memory, and the address of the pattern memory to be read next is generated in accordance with the sequence information.

The prior art will be further explained below with reference to the drawings.

FIG. 1 is a system configuration diagram of an example of a conventional test pattern readout control system.

First, if the value of the address counter indicates address ≠0, the test pattern "01010100" stored at addresses +-0 of the pattern memory is read out and applied to the circuit under test.

On the other hand, the control unit reads out the test pattern and
The corresponding order information is read and decoded, and the corresponding operation instruction is given to the address counter.

FIG. 2 is a correspondence diagram of order information and operation contents.

According to this, address ≠0 in Figure 1 has order information 1NOPJ
Therefore, the control section simply instructs the address counter by +1.

As a result, in the next cycle, the address counter points to address +1, and the test pattern stored there is "0".
0010100'' and the order information rLOOP 3 times'' are read out.

This order information rLOOP 3 times” is the order information rLOOP
This means that the section of order information until ENDJ is read is repeated up to three times.

Furthermore, when the control unit instructs the address counter by +1, the address is updated to ≠2 in the next cycle,
According to the order information rsUB+address 6, the process branches to address 4=6.

≠ Address 6 has order information 1'-NOPj, so
In the next cycle, the address is advanced to address 1#-7.

At address 4F7, according to the order information [LETj, in the next cycle it returns to address ≠ 3, and the order information rLOOPEN
DJ returns to the top address counter of the loop again.

Thereafter, the addresses are sequentially updated in the same manner according to the order information, and the test turns stored there are read out.

However, in recent years, as circuits under test have become faster and more complex, there has been a strict requirement to generate a large number of test patterns at high speed.

However, in the above-mentioned conventional method, reading and decoding of sequential information, address instruction according to the result, address update, etc. must be performed within one cycle, and in order to increase operation speed, the memory speed of sequential information must be extremely high. It is necessary to make it higher.

Furthermore, since there is a one-to-one correspondence between sequence information and test patterns in the pattern memory, storing a large number of test patterns requires a sequence information memory capacity with a correspondingly large depth.

Therefore, the conventional method described above not only requires the use of a large amount of expensive high-speed memory, which not only increases the cost of the device, but also currently there is no high-capacity high-speed memory, and it is difficult to implement a large number of high-speed memories. Therefore, the problem of signal delay due to the wiring must also be solved. In this way, in the conventional method, increasing the number of test patterns and increasing the speed of pattern generation are contradictory conditions.
It was difficult to achieve these simultaneously.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an economical test pattern readout control system that eliminates the drawbacks of the prior art described above and can efficiently read and generate a large number of test patterns at high speed.

[Summary of the invention]

The configuration of the test pattern readout control method according to the present invention is to store various test patterns and readout order information and expected value turns corresponding to each of the test patterns, and perform the relevant test according to the above order information. In a test device that has the function of reading out a pattern, inputting it to the circuit under test, and comparing the output with the expected value of the turn to determine the profit or loss of the circuit under test, the order information for reading out the test pattern is set in a predetermined manner. This is stored in a sequence information memory separate from the button memory for storing test patterns, and the test patterns are sequentially addressed and read based on the sequence information read out from the sequence information memory. It is controlled and processed in such a way.

The supplementary explanation is as follows.

According to the conventional method described above, the pattern memory for storing test patterns and the memory for storing sequence information for reading out the pattern memory (sequence information memory) must have the same capacity (same depth). There wasn't.

However, since most of the above order information is the order information rNOPJ (see FIG. 2) which is an invalid instruction, the order information memory capacity is wasted.

Therefore, in the method of the present invention, only the information necessary to successively generate test pattern addresses is stored in the sequence information memory as compressed address type sequence information.

This will be explained using FIG. 3, which is a memory configuration diagram of an example of compressed address type order information.

FIG. 3(a) is for the conventional method, and the addresses of the order information correspond one-to-one with the addresses of the test pattern.

On the other hand, FIG. 3(b) is of a compressed address type, and, for example, consecutive order information rNOPJ is represented by a single order information "NOp unti1~".

Therefore, since the memory capacity for this compressed address type sequential information is significantly reduced compared to the conventional method, the sequential information memory should be a small capacity, high-speed memory that can be separated from the test pattern storage memory. Not only high speed but also economy can be obtained.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The implementation of the present invention will be explained below based on the drawings.

FIG. 4 is a system configuration diagram of an embodiment of the test pattern readout control system according to the present invention.

Here, 1 is a pattern memory for storing (storing) test patterns, 2 is an address counter for specifying the address thereof, 3 is an order information memory for storing (storing) order information for reading test patterns, and 4 is a pattern memory for storing (storing) test patterns. , a program counter 5 which specifies the address thereof, according to the read order information, the address counter 2 . A control section 7, which provides various control signals to the program counter 4 and also gives instructions to the loop counter 6 in the case of a loop command, and also controls the entire A comparator 8 compares the operand with the value of the address counter 2 and, if they match, sends a match signal to the control unit 5. A clock generator 8 generates a clock for the overall operation timing. 9 is a circuit under test.

In FIG. 4, only a part of the test pattern and order information of this method are shown as an example, but below:
The ordering information set forth in FIG. 4 will therefore explain its operation.

First, assume that in the initial state, both the program counter 4 and the address counter 2 indicate address +0.

At this time, the comparator 7 uses its order information rNOPunti
2'', which is the operand of ``l~'', is compared with ``0'', which is the value of the address counter 2, and the controller 5 is notified of the mismatch.

Since the output of the comparator 7 indicates a mismatch, the control unit 5 instructs the program counter 4 to hold the value, and instructs the address counter 2 to perform count amplification.

In this state, the pattern stored at address 0 of pattern memo IJ 1 is read out as a test pattern ("10101001"') and applied to circuit under test 9.

At the next clock, the program counter 4 does not change its value and continues to indicate ≠0 address, and the address counter 2 counts and amplifies and indicates +1 zone.

The comparator 7 uses its order information “NOP until ~
fil + 2 j), which is the operand of J, and ≠1'', which is the value of the address counter 2, and again informs the control unit 5 of the mismatch.

Since the output of the comparator 7 indicates a mismatch, the control unit 5 instructs the program color/return 4 to hold the value again, and instructs the address counter 2 to count up.

In parallel with these operations, a test pattern ("11001010") is read from address +1 of memory 1.

Furthermore, at the next clock, the program counter 4 holds the value and continues to indicate address ≠0, but the address counter 2 counts and amplifies and indicates address ≠2.

Again, the comparator 15 compares the operand '≠2'' with the value "+2" of the address counter 2, and since they match, it sends a match signal to the control section 5.

Based on the coincidence signal, the control section 5 instructs the program counter 4 to count up and down, and also instructs the address counter 2 to count up.

In parallel with these, test patterns ("00011011
”) is read from address +2 of pattern memory 1,
The signal is applied to the circuit under test 9.

At the next clock, the program counter 4 will indicate address +1, and the address counter 2 will indicate address ≠3.

When the control unit 5 recognizes that the order information “LOOP■” is a loop instruction, the control unit 5 changes the number of loop operands to “LOOP■”.
The loop counter 6 is instructed to load . It also instructs the program counter 4 to count up and also instructs the address counter 2 to count up.

At the very next clock, program counter 4 is +
-2 address, and address counter 2 will point to address 4. Thereafter, in the same way as described above, the value of the program counter 4 is held at address ≠2 until the value of address counter 2 indicates address +-6, and the NOP operation (
(See Figure 2).

When the value of the address counter 2 indicates address +6, this matches the operand ``'≠6'' of the NOP instruction, and a match signal is sent from the comparator 7, so the controller 5
According to the instruction, the program counter 4 indicates address ≠3 and the address counter 2 indicates address +7 at the next clock.

Here, the controller 5 verifies the zero signal from the loop counter 6 based on the order information rLOOPENDJ (loop end command), but in this case, since the count result of the loop counter 6 is not 0, Instructs a countdown, specifies a load of address ≠1 for program counter 4, specifies a load of address ≠3 for address counter 2, and branches to the beginning of the loop at the next clock. I'll do what I do.

At this time, the data of addresses +1 and +3 indicating the start position of the loop may be included in the loop end instruction as operands, or the value of program counter 6 and the value of address counter 2 may be included at the time of the loop instruction. may be temporarily stored in the control unit 5. After this,
Repeat the same operation as above.

In this way, even if a small-capacity order information memory 3 storing compressed address type information as order information is used, the order information shown in FIG.
Since the order information before compression shown in a) can be realized as is, the amount of hardware in the test equipment can be reduced,
Along with economicalization, it also becomes possible to increase speed.

It is obvious that such a test pattern readout control method can also be used for pattern generation sequence control in a memory tester and pattern generation in a logic tester.

〔Effect of the invention〕

As described in detail above, according to the present invention, the order information for reading test patterns can be compressed to about a few tenths of that in the conventional case in normal cases, and the order information memory that requires high speed can be compressed. Since it becomes possible to use a small-capacity device, a remarkable effect can be obtained in increasing the efficiency, speed, and economy of this type of testing equipment.

[Brief explanation of the drawing]

FIG. 1 is a system configuration diagram of an example of a conventional test pattern readout control method, and FIG. 2 is a correspondence diagram of order information and operation contents.
FIG. 3 is a memory configuration diagram of an example of compressed address type order information, and FIG. 4 is a system configuration diagram of an embodiment of the test pattern readout control method according to the present invention. 1...Pattern memory, 2...Address counter,
3... Sequence information memory, 4... Program counter, 5... Control unit, 6... Loop counter, 7...
Comparator, 8 service 1. Turn 2 to the national exam, 3rd pass.

Claims (1)

[Claims] 1. Various test patterns and readout order information;
Expected value patterns corresponding to each of the above test patterns are memorized, the test pattern is read out according to the order information, inputted to the circuit under test, and the output is compared with the expected value pattern to determine whether the circuit under test is correct. In a test device having a function of determining the acceptability of a test pattern, order information for reading test patterns is in a predetermined compressed address format, and this is stored in an order information memory separate from a pattern memory for storing test patterns, A test pattern readout control method characterized by controlling and processing test patterns so that addressing and reading are sequentially performed based on order information read out from the test patterns.