JP3177975B2 - One-chip microcomputer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a one-chip microcomputer, and more particularly to a one-chip microcomputer in which an externally programmable memory and a microprocessor are integrated on a single chip.

[Conventional technology]

Conventionally, externally programmable memory (for example, EPRO
A microcomputer having an M, E ² PROM, or the like, hereinafter referred to as a PROM) on the same chip has a control circuit for applying a program voltage to the memory for writing the program into the memory, and an input port for inputting an address and a program. In order to check the written program, an output port for reading out to the outside is required, and the configuration as shown in FIG. 7 is employed.

FIG. 7 shows a control circuit 14 to which a mode setting signal MODE for instructing switching between a normal mode and a program mode, a program control signal ▼, and an output enable signal ▲ for instructing program reading, ie, verifying, are inputted, and a writing circuit. 12, PROM 10 including input buffer 13
FIG. 1 is a block diagram of a one-chip microcomputer in which a CPU (not shown) is integrated on the same chip.

Usually, such a one-chip microcomputer has a PROM
An input port for inputting a program to be written in 10 and an input port for inputting address information (address) in which the program is to be written are required. Further, a function (verify) of reading out the program written in the PROM 10 to the outside in order to check whether or not the written program is correct is also required, and an output port therefor is also required. The port circuits 20 and 30 shown in FIG. 7 function as an input port for inputting an address and an input / output port for writing and reading out a program in the PROM program mode. During the operation of, it functions as a port circuit controlled by the microcomputer. As a one-chip microcomputer, the hardware integrated on the chip must be as small as possible. For this purpose, the address for program and verification and the input / output port of the program are shared with the ports originally required by the microcomputer.

That is, when the mode setting signal MODE is “0”, the normal operation mode is set, and the port circuits 20 and 30 and the control circuit 14 are controlled.
Follow the instructions of the CPU (not shown).

When the mode setting signal MODE is "1", the mode is the program mode, and the port circuit 20 functions as a port circuit for inputting an address. The control circuit 14 outputs the output enable signal ▲
▼, follow the instructions of the program control signal ▲ ▼.
The port circuit 30 is an output port if ▲ ▼ is “0”,
If “1”, each functions as an input port.

A microcomputer incorporating such a PROM is used to detect defects that occur during the manufacturing and assembly processes.
All functions inside the microcomputer are tested by an LSI tester or the like. Built in as one of these tests
There are PROM program and verify test. In FIG. 7, when a program is written to the PROM 10 by the LSI tester, the address (ADDR) input from the terminal group 21 is input to the address decoder 11 of the PROM 10 via the address bus 50. Also, program data (DATA) to be written is sent from the terminal group 31 via the data bus 60 to the input / output buffer 13.
Is input to Here, the program control signal ▲ ▼
Becomes low level ("0"), a program is written to a specified memory cell of the PROM 10.

FIG. 8 is a timing chart showing this state. Terminal group
Addresses A0, A1, A2, ---, An are input from 21 and program data D0, D1, D2 --- corresponding to addresses A0, A1, A2, --- are respectively input from terminal group 31. input. The program control signal ▼ is an active low signal given from the outside of the microcomputer by the LSI tester. When ▼ is at a low level, for example, the program data of D0 is written into the memory cell of the PROM 10 designated by the address A0. The address and the program data to be input to the port circuit must be prepared in the pattern memory of the LSI tester, and one pattern is required for writing the program to one address. The verify check after writing the program can be realized by controlling the output enable signal ▲ ▼. When the address is designated and ▲ ▼ is set to low level, the program data is transferred from the input / output buffer 13 to the terminal via the data bus 60 and the port circuit 30. Output to group 31 (timing not shown).

[Problems to be solved by the invention]

In the conventional one-chip microcomputer described above,
The input pattern of the LSI tester for writing the program to the PROM must be prepared for each address, and the capacity of the pattern memory of the LSI increases with the increase of the PROM capacity.
There is a disadvantage that the use efficiency of the SI tester is reduced.

An object of the present invention is to provide a one-chip microcomputer capable of efficiently testing a program.

[Means for solving the problem]

The one-chip microcomputer of the present invention receives a mode setting signal for instructing switching between a normal mode and a program mode, an output enable signal, and a program control signal, and writes data to a memory cell, and outputs data from the memory cell. A PROM circuit including means for controlling data reading, and n address signal input terminals, and m (m is smaller than n and an integer of 1 or more) m in the program mode in response to the mode setting signal A port circuit for address input that blocks input from the address signal input terminal of the above, receives the program control signal, generates an m-bit alternative address signal, sends it to the PROM circuit, and outputs 2 ^m selection signals. And a port control circuit that receives a reset signal and returns the selection signal to an initial value. Receiving a No.択信, a said program mode, and, when it is selected by the selection signal, and the port circuit of the 2 ^m -1 pieces of data input and output to be set to the input mode, setting the mode Receiving the signal, the output enable signal, and the selection signal, in the program mode, if the output enable signal is inactive and selected by the selection signal, the input mode is set; Has a single data input / output port circuit set to the output mode if is in the active state.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a port control circuit in this embodiment.

In this embodiment, a mode setting signal MODE for instructing switching between a normal mode and a program mode, an output enable signal ▲ ▼, and a program control signal ▲ ▼
A PROM including a control circuit 14, a decoder 11, a writing circuit 12, and an input / output buffer 13 for controlling data writing to the PROM 10 as a memory cell and data reading from the PROM 10
An address signal input terminal having a circuit and n address signal input terminals 21 for receiving a mode setting signal MODE and inputting the least significant bit of an address signal in a program mode
Port circuit 20 for address input that blocks input from 21
Receives the program control signal ▼, generates a 1-bit alternative address signal and sends it to the PROM circuit, generates two selection signals, and resets the reset signal ▲.
▼ receives the above-mentioned selection signal to the initial value, the port control circuit 100, the inverter circuit 200, receives the mode setting signal MODE and the above-mentioned selection signal, is in the program mode, and When the mode is selected, the data input / output port circuit 40 set to the input mode, the mode setting signal MODE, the output enable signal ▲ ▼, and the above selection signal are received. The data input / output port circuit 30 is set to the input mode if the enable signal ▲ ▼ is inactive and selected by the above selection signal, and is set to the output mode if the output enable signal ▲ ▼ is active. It is that it has.

When the mode setting signal MODE is “0”, the normal mode is specified, and the port circuits 20, 30, 40 and the control circuit 14
(Not shown). When the mode setting signal MODE is "1", the program mode is set. In the program mode, a program is written to the PROM 10 and a verify check is performed.

 First, a program write operation will be described.

FIG. 3 is a timing chart of the program write operation of the first embodiment.

First, an address A0 is transmitted from the terminal group 21 to the address bus 50 in order to select a memory cell of the PROM to be written.
Is input to the address decoder 11 of the PROM 10 via the. However, at this time, since the least significant bit information (AD0) of the address is given by the port control circuit 100 as described later,
It is not output on the address bus 50. Therefore, the address information input to the decoder 11 from the address bus 50 includes both the even address and the odd address. For example, if the capacity of the PROM 10 is 256 bytes, the terminal group 2
One usually requires eight. At this time, the address 000000000 _B (B represents binary notation) is assigned as A0 to the terminal group 21.
, The least significant bit (AD
0) is not output and information of 00000000 × _B (× represents indefinite) is given. It is the output (AD0) of the port control circuit 100 that specifies whether the least significant bit is “0” or “1”.

Now, assuming that the address of address 0 is input from the terminal group 21 as A0, the program data D0 of the even address (address 0) is transferred from the terminal group 31 to the port circuit 30, and the program data D1 of the odd address (address 1) is From terminal group 41 to port circuit 40
Is input to At the timing when the program control signal ▼ changes to low level, the control circuit 14 writes data into the specified memory cell of the PROM 10;
Is also input to the port control circuit 100 to generate a 1-bit alternative address signal AD0. AD0 and ▲
▼ is used as a selection signal for switching the port circuits 30 and 40. FIG. 2 shows an example of the configuration of the port control circuit, which functions as a frequency dividing circuit for the program control signal ▼. Reset signal input to input terminal I2
If ▼ is low level and the program control signal ▲ ▼ to be input to the input terminal I1 is high level, the output (AD0) of the AND NOR gate circuit 101 is low level, the output of the AND NOR gate circuit 102 is high level, and the ORAND gate 1
The output of 03 is at a low level, the output of the orand gate 104 is at a high level, and initial values are set. In this state, if the reset signal ▼ is set to a high level (not shown), the port control circuit 100 operates as a circuit for dividing the program control signal ▼ by two.

That is, the output AD0 of the output terminal O1 of the port control circuit 100
And signal from AD0 via inverter circuit 200
▼ changes in synchronization with the rise of the program control signal ▲ ▼. These ▲ ▼ and AD0 are port circuits, respectively.
Since the control signal is 30, 40, the program data D0 of the even address input from the terminal group 31 is output to the data bus 60 when ▲ ▼ is high level, and is input from the terminal group 41 when AD0 is high level. The odd-numbered address data D1 is output to the data bus 60. As described above, the output AD0 of the port control circuit 100 is input to the decoder 11 as the least significant bit of the address. Therefore, when AD0 is at a low level, the decoder 11 points to an even address (A0, that is, address 0) of the PROM 10; When AD0 is at a high level, the decoder 11 points to an odd address (A1, that is, address 1) of the PROM 10. As a result the third
As shown in the figure, although the input pattern of the LSI tester is one pattern, writing for two addresses can be performed. That is, when the program control signal ▼ is input from the LSI tester as shown in FIG.
▼ is a low level period, and the program data D0 input from the port circuit 30 via the data bus 60 to the memory cell of the PROM 10 specified by the address A0 (address 0) is
The data is written via the input / output buffer 13 and the write circuit 12, and during the second low level period, the data bus 60 is transferred from the port circuit 40 to the memory cell of the PROM 10 designated by the address A1 (address 1). The program data D1 input through the I / O buffer 13 and the write circuit 12
Written via

The program data of the PROM 10 written in this manner can be verified by the output enable signal ▲ ▼. When an address is designated from the terminal group 21 and ▲ ▼ is set to the low level, the data bus 60 Via the port circuit 30
To a terminal group (not shown).

 The above description is summarized in Table 1.

FIG. 4 is a block diagram of a second embodiment of the present invention.

In the first embodiment, the program data to be written into the PROM 10 is input simultaneously from two ports. In the present embodiment, the program data is input simultaneously from four ports. 4th
In the figure, port circuits 300 and 400 including terminal groups 301 and 401 respectively
Are added to FIG. Also port control circuit
As shown in FIG. 5, 110 includes blocks 111 and 112 having the same functions as the port control circuit 100 in FIG. 2, inverter circuits 113 and 114, and AND gates 115, 116, 117 and 118.
The output circuits S1, S2, S3, S4 use port circuits 30, 40, 300, 4 respectively.
00 is selected, and an address bus 150 of lower two bits composed of AD0 and AD1 is input to the decoder 11. 4 and 5, those having the same functions as those in FIGS. 1 and 2 are denoted by the same reference numerals or symbols, and detailed description is omitted.

FIG. 6 is a timing chart showing the operation in the program write mode of the second embodiment. The operation of the second embodiment shown in FIG. 4 will be described with reference to FIG. First, the terminal group
21 is input with an address A0 representing address 0. However, the lower two bits (150) of the address information are stored in the port control circuit 110.
Therefore, the lower two bits of information are not output to the address bus 50. Terminal group 31, 41, 301, 401
, Program data D0 at address 0, program data D1 at address 1, program data D2 at address 2 and program data D3 at address 3 are input.

The port control circuit 110 shown in FIG.
12 (same configuration as in FIG. 2) is connected in series by a divide-by-4 circuit, inverter circuits 113 and 114, and AND gate circuits 115 and 11
6, 117, 118, the alternative address signals AD0, AD1, selection signals S0, S1, S2, S3 shown in FIG. Therefore, when S0 is at the high level, the program data D0 to be written to the address 0 input from the terminal group 31 is output to the data bus 60 via the port circuit 31, and at this time both AD1 and AD0 are at the low level. lower 2-bit information of the address to be input to the decoder 11 for it (150) is fixed at the 00 _B, PROM10
0 (A0) is specified and the program control signal ▲
While ▼ is at the low level, the program data D0 on the data bus 60 is written via the input / output buffer and the write circuit. Similarly, when S2 is high level, AD1, AD0
There confirm the low level, the lower 2 bits of information (150) of the address becomes a high level to 01 _B, respectively, address 1 (A1)
When the program data D1 is written to S3 and S3 is at the high level, the information (150) of the lower 2 bits of the address becomes 10 _{B and} 2
When the address (A2) contains the program data D2, and when S4 is at the high level, the lower two bits of the address information (150) becomes 11 _B , and the program data D3 becomes ▲ at the address 3 (A3).
Is written in the low level period. That is, as shown in FIG.
When ▼ is input, writing of four addresses can be performed even though the input pattern of the LSI tester is one pattern. The function of the output enable signal ▼ is the same as that of FIG.

 The above description is summarized in Table 2.

As described above, the first embodiment uses a program control signal to simultaneously input program data for two addresses from two ports, and the second embodiment uses the same program control signal to simultaneously program four addresses from four ports. Although data input is described, the number of ports is not limited, and it is clear that program data can be input simultaneously by the number of ports built in the microcomputer.

〔The invention's effect〕

As described above, the present invention generates a specific m-bit address signal of a PROM accessed by an n-bit address signal based on a program control signal.
Since it has a port control circuit that generates 2 ^m selection signals, when writing PROM built in the microcomputer with an LSI tester, etc., it is necessary to input program data from 2 ^m ports at the same time. Traditional
Since the PROM can be written with 1/2 ^m pattern, LSI
The use efficiency of a tester or the like can be greatly improved, leading to an increase in the efficiency of a product inspection process and a reduction in cost, and an effect of providing an inexpensive one-chip microcomputer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
FIG. 3 is a circuit diagram showing a port control circuit according to the first embodiment, FIG. 3 is a timing chart for explaining the operation of the first embodiment, and FIG. 4 is a block diagram showing a second embodiment of the present invention. FIG. 5, FIG. 5 is a circuit diagram showing a port control circuit in the second embodiment, FIG. 6 is a timing chart for explaining the operation of the second embodiment, FIG. 7 is a block diagram showing a conventional example,
FIG. 8 is a timing chart for explaining the operation of the conventional example. 10 ... PROM, 11 ... Decoder, 12 ... Write circuit, 13 ...
I / O buffer, 14 ... Control circuit, 20, 30, 40, 300, 400 ...
... port circuits, 50, 150 ... address bus, 60 ... data bus, 100, 110 ... port control circuit.

Claims (1)

(57) [Claims] A mode control signal for instructing switching between a normal mode and a program mode, an output enable signal, and a program control signal are used to control data writing to a memory cell and data reading from the memory cell. A PROM circuit having a means for performing the operation, and n address signal input terminals.
An address input port circuit for interrupting an input from m (m is smaller than n and an integer of 1 or more) address signal input terminals in a mode, and an m-bit alternative address signal receiving the program control signal Generating the PROM
Output to the circuit and generate 2 ^m selection signals.
A port control circuit that receives a reset signal and returns the selection signal to an initial value, and receives the mode setting signal and the selection signal, and is in the program mode, and when selected by the selection signal, Receiving the mode setting signal, the output enable signal, and the selection signal in response to 2 ^m -1 data input / output port circuits set to the input mode, and setting the output enable signal in the program mode A data input / output port circuit that is set to an input mode when the output signal is selected by the selection signal in an inactive state, and is set to an output mode when the output enable signal is active. A one-chip microcomputer.