JPH0746517B2 - Semiconductor memory and its testing method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory and a method of testing the same, and more particularly to a semiconductor memory equipped with an error correction function based on an error correcting code (hereinafter referred to as ECC (Error Correcting Code)). The present invention relates to a semiconductor memory suitable for facilitating various checks and a test method thereof.

[Background of the Invention]

In recent years, semiconductor memories that store various types of data have tended to be more highly integrated, but the amount of accumulated charges in the memory cells decreases accordingly, so that the frequency of soft errors increases.

As a countermeasure, Yamada et al., "Self-correction method in memory LSI", IEICE Transactions, October 1984, vol.J6
7-C, No.10, pp777-784, Yamada.J., Et.al.``A Submi
cnon VLSI Memory with a 4b−at−a−Time Built in
ECC Circuit '' ISSCC Digest of Technical Papers, pp1
As described in 04-105, Feb.1984, there is a method of providing an error correction function by ECC on a memory chip.

However, when performing the above-mentioned method to check after memory manufacturing (testing), it is specified that the semiconductor memory has an error correction function, and various tests including the error correction function are performed. However, for example, when a single error correction code is used as the ECC, if one memory cell happens to have a hard error, the read data is corrected by the ECC, so that the hard error can be found. You can't do that, and there will be no apparent errors.

Further, in this hard error state, if a soft error happens to occur in another memory cell belonging to the same error correction unit block as the error memory cell, a total of 2
Since bits have been generated, error correction by ECC becomes impossible.

Therefore, in order to completely perform various tests on the semiconductor memory with an error correction function, the memory cell itself and the
An error correction function consisting of an encoding circuit and a decoding circuit,
Each must be tested independently, but has not yet been announced as a viable solution.

[Object of the Invention]

The purpose of the present invention is to solve such conventional problems and
In the semiconductor memory equipped with the error correction function by
It is an object of the present invention to provide a semiconductor memory and a test method therefor capable of independently performing a test of a memory cell for a check bit, a test of an encoding circuit, a test of a decoding circuit and the like.

[Outline of Invention]

In order to achieve the above object, the semiconductor memory of the present invention is
Encoding means for adding a check bit based on an error correction code to information bits, a plurality of word lines, a plurality of data lines, and provided at a predetermined position of an intersection of the plurality of word lines and the plurality of data lines. A check bit memory cell for storing the check bit, a check bit memory cell for storing the check bit, which is provided at a predetermined position of an intersection of the plurality of word lines and the plurality of data lines, Data line selecting means for sequentially selecting the plurality of data lines, decoding means for correcting read data read from the information bit memory cell and the check bit memory cell, and an error correcting operation of the decoding means In a semiconductor memory having an error correcting operation means for stopping, the error correcting operation stopping means for supplying a timing signal to the data line selecting means. When the control signal from 1 is in the first state, a timing signal corresponding to the check bit is voluntarily generated, and when the control signal is in the second state different from the first state, it corresponds to the check bit. It is characterized by comprising a timing generating means for generating a timing signal corresponding to the amount of time in synchronization with an external clock.

In the semiconductor memory testing method of the present invention, the error correction operation of the decoding means is stopped, the control signal is set to the second state, and the check bit memory cell receives data from outside the semiconductor memory. Is written, and then the data stored in the check bit memory cell is read out to test the check bit memory cell. Further, the control signal is set to the first state, the information bit is input to the encoding means, and thereafter the error correction operation of the decoding means is stopped, and the control signal is set to the second state.
It is also characterized in that the method further comprises a step of testing the encoding means by reading the data stored in the check bit memory cell. The control signal is set to the second state to write data from the outside of the semiconductor memory into the information bit memory cell and the check bit memory cell, and thereafter the error correction operation of the decoding means is not stopped. It is also characterized in that it has a step of testing the decoding means by reading the data corrected by the decoding means in the state.

Example of Invention

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory showing a first embodiment of the present invention. In the figure, 1 is a decoder unit which decodes log ₂ r address signals by and designates one of the word lines W _{0 to} Wr _-1 of the memory array 3 through the word line driver 2 and 4 is designated (1 Sense amplifier group for reading and amplifying the data of all memory cells on the (word) word lines through the data lines D _{0 to} D _ns-1 , and 6 decodes the log ₂ s address signals to decode the data lines D _{0 to} D _{ns-. A} decoder unit for designating n of ₁ and sending (n) data of the designated sense amplifier group 4 to (n) common input / output line I / O via a data line selection circuit 5. , 20,30,40 are decoding circuits,
An encoding circuit, a selector circuit, and a writing circuit, which constitute an error correction function by ECC.

This semiconductor memory is a RAM (Random Access Memory), and has an EC of information points k, inspection points m, and code length n (n = k + m).
Has an error correction function by C. Also, the terminal ECC for inputting the ECC enable signal and the terminal aa for specifying the inspection bit
In normal use, the terminal ECCE is a resistor
R _{1 has a} high potential (logic “1”), and one terminal aa stores a variety of data by operating the error correction function at a low potential (logic “0”) with the resistor R ₂ . Although details will be described later, terminals
The operation of the error correction function is stopped by setting ECCE to a low potential (logic "0"), and the check bit is written / read by setting one terminal aa to a high potential (logic "1"). Check each part.

Next, each circuit 10 to 40 that constitutes the error correction function by ECC
The configuration and the operation thereof will be described with reference to FIGS.

Since the decoding circuit 10 performs error correction by ECC, as shown in FIG. 2, the syndrome generation circuit 11, the error position designation circuit 12, the exclusive OR (EOR) gate group for error correction, and the AN
It consists of D gate group. The syndrome generation circuit 11 generates a syndrome for the data x _{o to} x _n−1 from the common input / output line I / O and sends it to the error position designation circuit 12.
The error locator circuit 12 analyzes the syndrome and data x _o
The error position of _xn-1 is estimated, and among the n output lines, only the output line that is estimated to have an error is set to logic "1" (all other outputs are logic "0").

At this time, when the ECCE is logic "1", that is, when error correction is performed, the n outputs are directly subjected to EOR through the AND gate group.
Since it is sent to the gate group, only the bits of the data x _{o to} x _n-1 that are estimated to be erroneous are inverted, and the output y _{o to} y _n-1.
Becomes On the contrary, when the ECCE is logic “0”, that is, no error correction is performed, all the outputs of the AND gate group are logic “0”, and the data x _{0 to} x _n-1 are output as they are y _o to y _n-1 . Become.

The selector circuit 30, the transmission data y _o ~y ₆ from the decoding circuit 10 (where, n = 7, k = 4 , m = 3) to based on the address content of terminal aa and log ₂ k the output terminal Dout In order to read data from the memory array 3, it is composed of an inverter group, an AND gate group, and an OR gate, as shown in FIG.

That is, according to the contents of the three address signals a _i , a _{i + 1} , aa, _one of the input data y _{0 to} y ₆ is sent to Dout through the selected AND gate group and OR gate. When aa
If but a logic "0", performs the selection from among y _o ~y ₃ or information bits, the opposite, y ₄ ~ If aa is logic "1"
y _6, that is, from the check bits.

That is, the original address a _i ~a _{i + 1} for reading an information bit y _o ~y _3, by adding the address aa, information bits can be read out both check bits to the outside Become.

The writing circuit 40 uses the data from the input terminal Din to convert one bit of the data y _{0 to} y ₆ (n = 7, k = 4, m = 3) based on the address contents of aa and log ₂ k lines. As shown in FIG. 4, it is composed of a decoder circuit 41 consisting of an inverter group and an AND gate group, an inverter group, and a transistor group in order to replace and send it to the encoding circuit 20 and write it to the memory array 3 again.

That is, with the contents of the three address signals a _i , a _{i + 1} , and aa, _one of the data y _{0 to} y ₆ from the decoding circuit 10 is replaced with the data from Din, and the data is transferred to the encoding circuit 20. While sending this time, aa performs the substitution is logic "0" in the y _o ~y ₃ (information bits), the opposite, y ₄ ~y ₆ if aa is logic "1"
(Check bit).

That is, as in the case of the selector circuit 30, the information bit y ₀
By adding address aa to original addresses a _i and a _{i + 1} for replacing ~ y ₃ , it is possible to write arbitrary data from both outside to both information bits and check bits. Become. In this embodiment, since it is assumed that k ≧ m, the address to be added can be realized by one aa, but k <m
In the case of, the number of addresses to be added is increased to deal with it.

Encoding circuit 20 when writing to the memory array 3 to output data Z ₀ ~Z _n-1 from the write circuit 40 in x ₀ ~x _n-1 of the common input-output lines I / O, data bits (Z _{0 to} Zk ₋₁ ) as it is, one check bit (Zk to Z _n−1 ) is replaced as it is or with a newly generated check bit. Therefore, as shown in FIG. It consists of a transistor group and an inverter.

That is, the check bit generation circuit 21 generates m check bits of ECC based on the contents of Z _{0 to} Zk ₋₁ (information bits). At this time, if aa is a logical “0”, xk to x
_The check bit generated in _n-1 (check bit) is
If it is a logical "0", Zk to Z _n-1 is sent as it is and Z _{0 to} Zk _-1
At the same time, the data is written in the memory array 3 through the data line selection circuit 5.

Here, to summarize the above-mentioned contents regarding the check (testing) after the semiconductor memory is manufactured, the memory cell test ECCE remains "0" (the error correction function is stopped) and the memory array 3 has "1". The check data of "and" 0 "is written, then read to check the data content, and the memory cell itself including the memory cell for the check bit is tested. At this time, aa is scanned in the same way as the original address.

, Encoding test ECCE is logic "1" (error correction function is activated), aa is logic "0"
, Write the information bit, and then set ECCE to logic "0".
(Error correction function is stopped), information bit, and then aa
Is set to logical "1" (specify check bit),
Both are read out, the data contents are checked, and a test is performed as to whether or not the check bit is correctly added in the encoding circuit 20.

, Decryption test ECCE is set to logic "0", aa to logic "0", information bit is written, then aa is changed to logic "1" and check bit is written, and then ECCE is set to logic "1", aa Is set to logic "0", the information bit is read, the data content is checked, and a test is performed as to whether the information bit is correctly error-corrected in the decoding circuit 10. Then, only aa is changed to the logic "1", the check bit is read and checked in the same manner, and the correction test for the check bit is performed. The data to be written has a content including an error that can be corrected by the decoding circuit 10.

In the present embodiment, the terminals ECCE, aa are provided for inputting the ECC enable signal and the address signal, but other terminals may be used in a time division manner and both signals may be input. Also, signal combinations that are not used during normal operation (eg static
In the RAM, the signal may be internally generated by applying the output enable signal OE and the write enable signal WE at the same time.

Next, a second embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 6 is a configuration diagram of a semiconductor memory. First mentioned above
The difference from the figure is that (i) the data lines D _{0 to} D _n-1 are serially selected. That is, the r word lines W _{0 to} Wr ₋₁ are
Are selected at random as well by the decoder unit 1 and Figure 1, the data lines D ₀ to D _n-1 of n book D ₀ by the shift register unit 7 for shifting in synchronization with the clock signal SCLK from the outside, D ₁ , D ₂ ... D _n-1 are selected in this order. However, the data line
Similarly to the above, D _{0 to} D _n-1 are configured to store k information bits D _{0 to} Dk _-1 and m check bits Dk to D _n-1 . Therefore, the writing / reading of the information bit to / from the memory array 3 is carried out bit by bit at the timing of k times in synchronization with the SCLK signal.

(Ii) A cyclic code is adopted as the ECC. This allows
As the encoding circuit 25 and the decoding circuit 15, circuits that serially execute encoding and decoding by using the property of cyclic code are used.

(Iii) A timing generation circuit 55 that inputs a SCLK signal and an ECC enable signal and generates a timing pulse for driving the shift register unit 7, the encoding circuit 25, and the decoding circuit 15.
Equipped with. Although details will be described later, if necessary, SCLK
Sends a timing pulse even if there is no signal.

(Iv) The connection destination of the common input / output line I / O from the data line selection circuit 5 is the output side and the input side of the decoding circuit 15, and the encoding circuit 25.
A switch 65 for switching to the input side of is provided.

FIG. 7 is a processing flowchart of the semiconductor memory of FIG. FIG. 8 is an operation timing chart at the “normal operation” in FIG.

In the semiconductor memory, when the chip select signal CS, which is a selection signal (not shown), is “L” and the decoder unit 1 and the word line driver 2 select one of the word lines W _{0 to} Wr ₋₁ , Although not shown, when the WE signal which is a signal for instructing reading or writing is "L" (writing), the timing generating circuit 55 causes the encoding circuit 25 and the shift register unit 7 to SCL.
Send a timing pulse that is synchronized with the K signal k times,
The data lines are switched one by one in the order of D ₀ , D ₁ , D ₂・ ・ ・ Dk _-1 , and the data from the input terminal Din is written in the memory cell corresponding to that of the memory array 3 (step in FIG. 7). 12
2). The switch 65 is connected to the output side (terminal C) of the encoding circuit 25.

Then, the timing generating circuit 55 sends timing pulses to the encoding circuit 25 and the shift register 7 m times, and the m check bits generated by the encoding circuit 25 are checked by the same method as described above. Write to 3 (Step 12
3).

By repeating the above operation, all the data from Din and E
Write the CC check bit into memory array 3.

On the other hand, when the WE signal is "H" (read), first, the timing generating circuit 55 sends a timing pulse to drive the shift register unit 7 and the decoding circuit 15 to calculate the syndrome (step 131). Then, the timing generation circuit 55 sends a timing pulse in synchronization with the SCLK signal to the decoding circuit 15 and the shift register unit 7, and the data lines D ₀ , D ₁ , D ₂ ... _-1 is switched one by one in order, the k information bits are read from the corresponding memory cell of the memory array 3, and the decoding circuit 15 performs error correction,
Output to output terminal Dout. At the same time, the corrected information bit is rewritten into the original memory cell of the memory array 3 through the terminal A of the switch 65 and the data line selection circuit 5 (seventh).
Step 132 in the figure).

Then, the timing pulse is sent m times from the timing generation circuit 55 to the decoding circuit 15 and the shift register section 7, and the data lines Dk, Dk _{+ 1} , ...
After switching one by _{one in} the order of D _n-1 and reading out m check bits from the corresponding memory cell and performing error correction in the decoding circuit 15, through the terminal A of the switch 65 and the data line selection circuit 5, the memory array 3 of Rewrite to the original memory cell (step
133). Note that m check bits are rewritten, but Dou
Do not send to t.

By repeating the above read operation, a specified information bit in the memory array 3 is output to Dout.

In this case, the number of cycles of the SCLK signal applied from the outside is k times during writing and reading, and the number of data to be written and read is k bits. That is, from the outside, it looks like a k-bit serial semiconductor memory, and m inspection bits for ECC cannot be seen.

FIG. 9 is an operation timing chart at the time of “test of memory cell (including memory cell for check bit)” in FIG. 6.

In the semiconductor memory, when both of the CS signal and the terminal ECCE are “L” and one of the word lines W _{0 to} Wr ₋₁ is selected, when the WE signal is “L” (write), FIG. As in the normal operation), from the timing generation circuit 55 to the encoding circuit 25, the shift register unit 7
The timing pulses synchronized with SCLK signal by out k forwarding, switching the data line in the order of _{D 0, D 1, D 2} ‥‥ Dk -1, Din
The data (information bit) from (1) is sequentially written into the memory cell corresponding to the memory array 3 through the C terminal of the switch 65 and the data line selection circuit 5 (step 112 in FIG. 7).

Subsequently, a timing pulse similar to the above is sent from the timing generation circuit 55 to the encoding circuit 25 and the shift register unit 7.
The data lines are transmitted once, and the data lines are switched in the order of Dk, Dk ₊₁ , Dk ₊₂・ ・ ・ D _n-1 and the data (check bit) from Din is switched to switch 6
Data is sequentially written into the memory cells corresponding to the memory array 3 through the C terminal 5 and the data line selection circuit 5 (step 11).
3).

By repeating the above operation, the data (information and check bits) from Din is written in each memory cell of the memory array 3.

On the other hand, when the WE signal is "H" (read), after the shift register unit 7 and the decoding circuit 15 are caused to calculate the syndrome, as in FIG. 8 (normal operation) (step 14 in FIG. 7).
1) The timing generating circuit 55 sends a timing pulse in synchronization with the SCLK signal to the decoding circuit 15 and the shift register section 7, and the data lines D ₀ , D ₁ , D ₂ ... _-1
, And reads k information bits from the corresponding memory cells of the memory array 3 and outputs them to Dout. At the same time, the data is again written into the memory array 3 through the terminal A of the switch 65 and the data line selection circuit 5 (step 142).

Then, the timing pulse similar to the above is further supplied from the timing generation circuit 55 to the decoding circuit 15 and the shift register unit 7.
, M _n times, the data lines are switched in the order of Dk, Dk ₊₁ , ..., D _n-1 , and m check bits are read from the corresponding memory cell and output to Dout. At the same time, the data is again written into the memory array 3 through the terminal A of the switch 65 and the data line selection circuit 5 (step 143).

By repeating the above-mentioned read operation, the information and the check bit of the memory array 3 are output to Dout.

In the memory cell test, unlike the normal operation, the SCLK signal is applied (k + m) times for both writing and reading, and the data error correction by the decoding circuit 15 is stopped (this is the same as in FIG. 2). It is realized by the method of). As a result, when the SCLK signal is applied n (= k + m) times, not only the information bit written in the memory cell but also the check bit are corrected without correction.
Since the data can be read in ut, the memory cell itself (including the memory cell for the check bit) can be tested. Further, in this case, it looks like an n-bit serial semiconductor memory without an error correction function from the outside.

FIG. 10 is an operation timing chart at the'encoding test 'in FIG.

In the semiconductor memory, the CS signal is "L", the terminal ECCE is "H", and the WE
When the signal is "L" (write), the word lines W _{0 to} Wr _-1 are 1
When selected, SCLK is the same as in Fig. 8 (during normal operation).
Data (information bits) from Din are written to the memory array 3 at timing pulses (k times) synchronized with the signal (step 122), and then at timing pulses (m times).
The m check bits generated by the encoding circuit 25 are written in the memory array 3 (step 123).

By repeating the above operation, all the data from Din and the ECC check bit for the data are written in the memory array 3.

On the other hand, when one of the word lines W _{0 to} Wr ₋₁ is selected when the terminal ECCE is “L” and the WE signal is “H” (read), the same as in FIG. 9 (during memory cell test). Then, after calculating the syndrome, timing pulse (k times) synchronized with the SCLK signal
Then, k information bits of the memory array 3 are read out and output to Dout, and at the same time, rewritten in the memory array 3 (steps 141 and 142). Then, similar to the above information bit, SCLK
At the timing pulse (m times) synchronized with the signal, m inspection bits of the memory array 3 are read out and output to Dout, and at the same time, written again in the memory array 3 (step 143).

By repeating the above read operation, the information and check bits in the memory array 3 are output to Dout.

In this case, set ECCE to "H" to set the information bit and encoding circuit.
After writing the check bit added in 25 to the memory cell, set ECCE to "L" (stop error correction function) and read n-bit data consisting of information bit and check bit without error correction. Therefore, it is possible to test whether the check bit is correctly added in the encoding circuit 25.

FIG. 11 is an operation timing chart at the “encoding test” in FIG.

In the semiconductor memory, when both the CS signal and the terminal ECCE are “L” and the WE signal is “L” (write), the timing pulse synchronized with the SCLK signal is provided as in FIG. 9 (when testing the memory cell). (K times), data from Din (k information bits)
To the memory cells of memory array 3 (step 11
2) Then, at the same timing pulse (m times) as the above information bit, data from Din (m check bits)
Are sequentially written in the memory cells (step 113).

On the other hand, when the WE signal is "H" (read), as in FIG. 8 (during normal operation), after calculating the syndrome, a timing pulse (k times) synchronized with the SCLK signal causes the memory array 3 to operate.
, K information bits are read out, the decoding circuit 15 performs error correction and outputs them to Dout, and at the same time, writes them again in the memory cells (steps 131 and 132), and then the timing pulse (m
(M times), the m check bits are read from the memory array 3, the decoding circuit 15 performs error correction, and the data is written in the memory cell again (step 133).

By repeating the above read operation, the information bit in the memory array 3 is output to Dout.

In this case, ECCE is set to "L", the information bit and the check bit are written in the memory array 3 with arbitrary contents, and then the information bit is read out after the ECCE is set to "H", that is, the decoding circuit 15 performs error correction. Therefore, it is possible to test whether the decoding circuit 15 is correct. The contents of the data to be written include an error that can be corrected by the decoding circuit 15, for example. When the check bit is carried out together with the information bit correction test, the method shown in FIG. 12 is used.

That is, in the semiconductor memory, the SCLK, the terminal ECCE, and the WE signal are both in the “L” state at the first stage, as in FIG.
Din by timing pulse (k + m times) synchronized with the signal
Both the k information bits from and the m check bits are written into the memory cell (steps 112-113).

Next, in the second stage in which both the terminal ECCE and the WE signal are in the "H" state, the memory array 3 is driven by the timing pulse (k times) synchronized with the SCLK signal after calculating the syndrome, as in FIG.
After reading out and correcting the information bit from the output and outputting it to Dout, the check bit is read out and corrected by the timing pulse (m times) and written again in the memory array 3 (steps 131 to 133).

Subsequently, in the third stage in which both the CS signal and the terminal ECCE remain “L” and the WE signal remains “H”, timing pulse (synchronized with the SCLK signal after the calculation of the syndrome as in FIG. 9). (k times), the information bit is read out and output to Dout and again written to the memory array 3, and then the synchronous timing pulse (m times) reads out the check bit corrected in the second stage and outputs it to Dout. Then, the data is written again in the memory array 3 (steps 141 to 143).

It is possible to externally determine whether the check bit has been correctly corrected by the above three-step operation. A method of performing the operation without the three steps will be described with reference to FIG.

FIG. 13 is a semiconductor memory block diagram in the case where two ECC enable signal input terminals are provided.

In the figure, ECCE ₁ is a terminal that controls the timing generation circuit 56 and the encoding circuit 26 in the same manner as described above, and ECCE ₂ is a terminal that controls the decoding circuit 16 in the same manner as described above. The rest is the same as in FIG.

That is, in the check bit decoding test, first, as in the case of FIG. 11 (at the time of the decoding test), the CS signal and the terminal ECCE are written.
Set both ₁ and WE signals to "L" (logic "0") and set terminal ECCE ₂ to "H"
(Logic "1"), write the data (information and check bit) from Din to the memory array 3 and read the next
By reading the ECCE ₁ with the logic “0” and the ECCE ₂ with the logic “1”, the check bit can be directly read from the state where the decoding circuit 16 is performing the error correction. You can test in two steps. During the other tests and the normal operation, the embodiment of FIG. 6 is performed with ECCE ₁ = ECCE ₂ .

FIG. 14 is a configuration diagram of a semiconductor memory showing a fourth embodiment of the present invention. In the figure, 73 is a multi-valued (3-bit) memory array, 67 is three I / Os from the data line selection circuit 75.
Switches that connect the lines to the input side and output side of the decoding circuit and the output side of the encoding circuit, respectively. Input terminal
The number of Din and output terminals Dout is three, but the operation of each of the other circuits is basically the same as in FIG.

The encoding circuit 27 performs 3-bit encoding in the same manner as described above and writes it in the multi-valued memory, and the decoding circuit 17 performs 3-bit error correction in the same manner as described above and also in the multi-valued memory. By reading the data, the various tests described above are performed.

In this way, the test of the memory cell itself for storing the ECC enable signal and the check bit is instructed to the outside, and the test of the memory cell itself, the test of the encoding circuit, the test of the decoding circuit, etc. are made independent. Therefore, the reliability of testing can be improved as compared with the conventional case.

〔The invention's effect〕

As described above, according to the present invention, the memory cell itself, the encoding circuit, and the decoding circuit can be independently tested, so that the conventional semiconductor memory with an error correction function performs error correction. Therefore, it becomes possible to detect a hardware error that cannot be detected.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory showing a first embodiment of the present invention, FIGS. 2 to 5 are circuit configuration diagrams having an error correction function by ECC, and FIG. 6 is a second embodiment of the present invention. FIG. 7 is a configuration diagram of a semiconductor memory showing an example, FIG. 7 is a process flow chart of FIG. 6, FIG. 8 is a time chart of a normal operation in FIG. 6, and FIG. 9 is a test of a memory cell in FIG. Operation time chart, FIG. 10 is an operation time chart at the time of the coding test in FIG. 6, FIG. 11 is an operation time chart at the time of the decoding test in FIG. 6, and FIG. 12 is an inspection together with the correction test of the information bit. FIG. 13 is a configuration diagram of a semiconductor memory in which two ECC enable signal input terminals are provided, and FIG. 14 is a configuration of a semiconductor memory showing a fourth embodiment of the present invention. It is a figure. 1,6,71: Decoder section, 2,72: Word line driver, 3,73: Memory array, 4,74: Sense amplifier group, 7,75: Data section selection circuit, 7,77: Shift register section, 10 , 15,16,17: Decoding circuit, 11: Syndrome generating circuit, 12: Error position specifying circuit,
20,25,26,27: Encoding circuit, 21: Check bit generation circuit, 30:
Selector circuit, 40: Write circuit, 41: Decoder circuit, 55, 5
6,57: Timing generator, 65,66,67: Switch, ECCE: E
CC enable signal input terminal, aa: input terminal for specifying inspection bit, Din: data input terminal, Dout: data output terminal.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shinichi Ikenaga 1-280 Higashi Koigakubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Katsuhiro Shimoto 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Ltd. (56) References JP-A-60-11952 (JP, A) JP-A-58-185097 (JP, A) JP-A-56-22292 (JP, A) JP-A-55-93598 (JP , A)

Claims (4)

[Claims] 1. A coding means for adding a check bit based on an error correction code to an information bit, a plurality of word lines, a plurality of data lines, and an intersection of the plurality of word lines and the plurality of data lines. An information bit memory cell, which is provided at a predetermined position and stores the information bit, and a check bit, which is provided at a predetermined position at the intersection of the plurality of word lines and the plurality of data lines, and stores the check bit. Memory cell, data line selecting means for sequentially selecting the plurality of data lines, decoding means for correcting read data read from the information bit memory cell and the check bit memory cell, and the decoding means. In the semiconductor memory having an error correction operation stopping means for stopping the error correction operation of the above, since the timing signal is supplied to the data line selection means, the error When the control signal from the correction operation stopping means is in the first state, the timing signal corresponding to the check bit is spontaneously generated, and when the control signal is in the second state different from the first state, the timing signal is generated. A semiconductor memory comprising a timing generation means for generating a timing signal corresponding to a check bit in synchronization with an external clock. 2. An encoding means for adding a check bit based on an error correction code to an information bit, a plurality of word lines, a plurality of data lines, and an intersection of the plurality of word lines and the plurality of data lines. An information bit memory cell, which is provided at a predetermined position and stores the information bit, and a check bit, which is provided at a predetermined position at the intersection of the plurality of word lines and the plurality of data lines, and stores the check bit. Memory cell, data line selecting means for sequentially selecting the plurality of data lines, decoding means for correcting read data read from the information bit memory cell and the check bit memory cell, and the decoding means. The error correction operation stopping means for stopping the error correction operation and the timing generating means for supplying a timing signal to the data line selecting means. When the control signal from the error correction operation stopping means is in the first state, the generating means spontaneously generates a timing signal corresponding to the check bit, and the control signal is different from the first state. In the state of 2, the error correction operation of the decoding means is stopped and the control signal is set to the second state in a semiconductor memory which generates a timing signal corresponding to the check bit in synchronization with an external clock. A step of writing data from the outside of the semiconductor memory into the check bit memory cell and then reading the data stored in the check bit memory cell to test the check bit memory cell. A method for testing a semiconductor memory, comprising: 3. Encoding means for adding check bits based on an error correction code to information bits, a plurality of word lines, a plurality of data lines, and intersections of the plurality of word lines and the plurality of data lines. An information bit memory cell, which is provided at a predetermined position and stores the information bit, and a check bit, which is provided at a predetermined position at the intersection of the plurality of word lines and the plurality of data lines, and stores the check bit. Memory cell, data line selecting means for sequentially selecting the plurality of data lines, decoding means for correcting read data read from the information bit memory cell and the check bit memory cell, and the decoding means. The error correction operation stopping means for stopping the error correction operation and the timing generating means for supplying a timing signal to the data line selecting means. When the control signal from the error correction operation stopping means is in the first state, the generating means spontaneously generates a timing signal corresponding to the check bit, and the control signal is different from the first state. In the state of 2, in a semiconductor memory that generates a timing signal corresponding to the check bit in synchronization with an external clock, the control signal is set to the first state and the information bit is input to the encoding means, Thereafter, the error correction operation of the decoding means is stopped, the control signal is set to the second state, and the data stored in the check bit memory cell is read to test the encoding means. A method for testing a semiconductor memory, comprising: 4. An encoding means for adding a check bit based on an error correction code to an information bit, a plurality of word lines, a plurality of data lines, and an intersection of the plurality of word lines and the plurality of data lines. An information bit memory cell, which is provided at a predetermined position and stores the information bit, and a check bit, which is provided at a predetermined position at the intersection of the plurality of word lines and the plurality of data lines, and stores the check bit. Memory cell, data line selecting means for sequentially selecting the plurality of data lines, decoding means for correcting read data read from the information bit memory cell and the check bit memory cell, and the decoding means. The error correction operation stopping means for stopping the error correction operation and the timing generating means for supplying a timing signal to the data line selecting means. When the control signal from the error correction operation stopping means is in the first state, the generating means spontaneously generates a timing signal corresponding to the check bit, and the control signal is different from the first state. In a semiconductor memory that generates a timing signal corresponding to the check bit in synchronization with an external clock in the state of 2, the control signal is set to the second state and the memory cell for the information bit and the check bit A step of writing the data from the outside of the semiconductor memory into the memory cell, and thereafter testing the decoding means by reading the data corrected by the decoding means without stopping the error correction operation of the decoding means. A method for testing a semiconductor memory, comprising: