JPH02242440A - Instruction trace circuit - Google Patents

Abstract

PURPOSE:To perform the analysis of the factor of the execution time of a program to be traced by recording the count value of a clock signal supplied to a central processing unit corresponding to executed instruction word and instruction address. CONSTITUTION:A clock counter 1 counts an inputted clock signal 102 while a busy signal 101 representing the fact that the central processing unit is operating is being inputted, and outputs a clock counter value 109. A trace memory 2 records the instruction address 103 and the instruction word 104 of the executed instruction by making correspond to the clock counter value 109 at every input of the instruction address 103 and a sampling signal 105 outputted at every execution of one instruction at the central processing unit while a trace working display signal 113 from a trace display circuit 5 is being inputted. In such a way, it is possible to calculate the execution time including the disturbance of a pipeline in each instruction, and to perform the analysis of the factor of the execution time such as the execution time classified by every routine of the program to be traced and incremented time due to the disturbance of the pipeline, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an instruction tracing circuit, and more particularly to an instruction tracing method in an information processing apparatus having an instruction 1-receive function.

BACKGROUND ART Conventionally, in information processing apparatuses, there is a method using instruction 1 to race data as a method for measuring the dynamic characteristics of software and performing performance evaluation.

This method generates an interrupt every time one instruction is executed on the I-race program, or every time a certain number of instructions are executed, and an interrupt processing routine returns the address and instruction word of the instruction executed immediately before the interrupt. After the data is collected, the program returns to the execution of the 1-to-race program before the interrupt.

” When the tracing of the traced program is completed, the collected data is collected and analyzed.
Alternatively, it is used as input to a simulator to evaluate performance.

In such conventional information processing devices, the data collected from instruction 1 to race includes the instruction word, instruction address, and register contents of the executed instruction, but does not include the execution time of each instruction. Therefore, in devices with a cache or devices that have many factors that determine the execution time of each instruction, such as in a pipeline system, it is useful to find the execution time of each instruction and analyze the factors in the execution time of the traced program. , which has the disadvantage of requiring a large-scale simulator.

Purpose of the Invention The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and is capable of analyzing execution time factors such as the execution time of each routine of a traced program and the increase in time due to pipeline disturbances. The purpose is to provide an instruction trace circuit that can be used.

Composition of the Invention An instruction tracing circuit according to the present invention includes a clock counting means for counting clock signals supplied to a central processing unit, an instruction word and an instruction address executed in the central processing unit, and a clock counting means for counting clock signals supplied to a central processing unit; It is characterized by comprising a recording means for recording the corresponding count value of the clock counting means.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a clock counter 1 counts input clock signals 102 while a busy signal 101 indicating that a central processing unit (not shown) is in operation is input, and an ITI counter value 109 is counted. is output to trace memory 2. This tarlock signal 102 is a busy signal used by the central processing unit.

The 1-race memory 2 outputs an output every time one instruction is executed in the central processing unit while the 1-race operation display signal 113 from the 1-race display circuit 5 indicating that the 1-race operation is in progress is input. Every time a sample signal 105 indicating the sample timing of the instruction address 103 and instruction word 104 to be executed is input, the instruction address 103 and instruction word 104 of the executed instruction and the clock counter value 109 of the clock counter 1 are sequentially recorded. be done.

The instruction number counter 3 counts the sample signals 105 while the trace operation display signal 113 from the l-race display circuit 5 is input, and sends an overflow signal 111 indicating an overflow to the trace display circuit 5 and It is output to the interrupt display circuit 6. That is, the instruction number counter 3 counts the number of executed instructions, and outputs an overflow signal 111 when a preset number of instructions is counted.

Register 4 has an initial value of 11, which is not set by the interrupt interval designation signal 107, which designates the interval for the number of instructions that generate an interrupt.
2 is output to the instruction number counter 3.

When the trace display circuit 5 receives a trace start signal 106 instructing the start of a trace operation, it generates a trace operation display signal 113 indicating that a trace operation is in progress and outputs it to the trace memory 2 and the instruction number counter 3. In addition, the trace display circuit 5 is reset by the overflow signal 111 from the instruction number counter 3.

When the interrupt display circuit 6 receives the overflow signal 111 from the instruction number counter 3, it generates an interrupt signal 114 and outputs it to the central processing unit, and is reset by the input of the reset signal 108.

Next, the operation of an embodiment of the present invention will be explained with reference to FIG. The complement is set in register 4.

When a trace start instruction for starting the I-race is executed, the trace display circuit 5 is set to 1 by the trace start signal 106, and the trace memory 2 and the instruction number counter 3 from the I-race display circuit 5 are set to 1. A race operation display signal 113 is output.

When the race display circuit 5 is set to 1, the initial value 112 from the register 4 is set to the instruction number counter 3,
The instruction number counter 3 starts counting the sample signals 105.

In addition, the l/race memory 2 receives the instruction address 103, the instruction word 104, and the clock counter value 109 from the clock counter at the input timing of the sample signal 105 by inputting the in-race operation display signal 113 from the trace display circuit 5. Start recording. These recordings are performed while the address of the trace memory 2 is being updated.

Since the sample signal 105 is output every time one instruction is executed,
The instruction number counter 3 counts the number of executed instructions. Also, when the instruction number counter 3 starts counting, the register 4
Since the initial value 112 is set, the overflow signal 111 is generated in the instruction number counter 3 when the number of instructions specified by the interrupt interval specification instruction is increased by 51.

The overflow signal 111 from the instruction number counter 3 sets the interrupt display circuit 6, and the overflow signal 111 causes the I-race display circuit 5 to reset to 1, and the recording operation of 1 to race memory 2 and the instruction number counter 3 are set. 2. The interrupt signal 114 is generated by setting the interrupt display circuit 6, which stops the counting operation.
This interrupt signal 114 causes an interrupt to occur.

In the interrupt processing routine caused by the overflow of the instruction counter 3, the contents of the trace memory 2 are transferred to a trace buffer (not shown) in the main memory, a trace start instruction is executed, and control is passed to the processing before the interrupt. is,
Tracing is started again. Note that when the 1 to race buffer becomes full, the contents of the trace buffer are output to a recording medium (not shown) by the interrupt processing routine.

Through the above processing, each time the number of instructions specified by the interrupt interval specification instruction is executed, the instruction address 103 of the number of instructions corresponding to the capacity of the trace memory 2 and the instruction H? Since the clock counter value 1104 and the clock counter value 109 are recorded in the order of execution, the execution time can be calculated by dividing the difference between the clock counter value and the clock counter value of the previous instruction for each instruction.

In addition, measures to increase execution time due to pipeline disturbance can be calculated from the difference between the execution time of each instruction without pipeline disturbance determined by the instruction word and the execution time of each instruction obtained from the clock counter value as described above. It becomes possible.

Furthermore, by summing up the instruction execution time for each routine of the traced program using each instruction address in the trace data, it is possible to calculate the execution time of each routine on the race program. .

In this manner, the clock signal 102 of the central processing unit is counted by the clock counter 1, and the count value is recorded in the trace memory 2 in correspondence with the instruction address 103 and instruction word 104 of the executed instruction. ,
It is possible to calculate the execution time of each instruction including pipeline disturbances, and to analyze execution time factors such as the execution time for each routine of the 17 grams to be traced and the increased time due to pipeline disturbances.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the counted value of the clock signal supplied to the central processing unit is recorded in correspondence with the executed instruction word and instruction address, thereby This method has the advantage that it is possible to analyze execution time factors such as the execution time for each program routine and the increase in time due to pipeline disturbances.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Description of symbols of main parts 1...Clock counter 2...Trace memory 3...Instruction number counter 5...Trace display circuit 6...・Interrupt display circuit

Claims (1)

[Claims] (1) A clock counting means for counting clock signals supplied to a central processing unit, an instruction word and an instruction address executed in the central processing unit, and a count of the clock counting means corresponding to the instruction word and instruction address. An instruction tracing circuit comprising: a numerical value; and a recording means for recording a numerical value.