JPH10260872A - Computer system and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To maintain the performance analysis ability, to secure the tracing and analysis ability, and to automatically tune the system performance while saving the resource, by taking in the instruction of a program to be measured, setting the type of the instruction and the instruction in records until a branching destination appears, and summing up the number of the instructions until branching, which are contained in the records that are set, and the number of looping times. SOLUTION: A tracing task 4 sums up the records acquired from the program to be measured. An output buffer 5 preserves the records where the type of the instruction of the program to be measured, which the tracing mechanism 2 acquires, and the instruction until the branching destination appears are set. A sum-up buffer 6 sums up the number of instructions and the number of loops based on the preserved records from an output buffer 5 and stores them. They are installed in the computer system 1 and it is operated. Thus, performance analysis ability is maintained and tracing and analysis ability can be secured even in a situation that speed is accelerated, a scale is made large and it is diffused.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a computer system and a recording medium for tracing a program to be measured.

[0002]

2. Description of the Related Art Conventionally, in order to evaluate and debug the performance of a computer system, execution instructions and events occurring in the system are traced.

At this time, if all the traced data is collected, the memory capacity becomes enormous, and various measures have been taken to solve this. For example, JP-A-57-1
In JP-A-91760, a device for detecting a loop of a program, suppressing duplicate tracing of the same loop, and reducing an instruction trace amount, a special circuit for detecting a loop, and a loop detection buffer are provided. Was.

[0004]

As described above, when tracing execution instructions and the like of a computer system, if all of them are collected, the memory capacity becomes enormous. Therefore, a circuit or device for solving this problem is provided. Then, there is a problem that a configuration becomes complicated.

[0005] Further, in the conventional technology, while saving resources,
There are problems such as that it can be applied only to a specific application such as a completeness test and that the performance analysis capability cannot be secured.

[0006] The present invention solves these problems,
Even in recent years of high speed, large scale, and decentralized conditions,
The aim is to maintain performance analysis capabilities, secure trace and analysis capabilities, and automatically tune system performance while saving resources.

[0007]

Means for solving the problem will be described with reference to FIG. In FIG. 1, a trace task 4 takes in instructions of a program to be measured, and sets the type of the instruction, the instruction in a record until a branch destination appears, and counts the instructions.

[0008] The output buffer 5 is for outputting a record. Next, the operation will be described. The trace task 4 fetches the instruction of the program to be measured, sets the type of the instruction and the instruction in a record until a branch destination appears, and counts the number of instructions and the number of loops until the branch included in the set record. ing.

At this time, the address of the branch instruction, the number of instructions until branching, and the number of loops are output in a time series. Further, when sequentially setting the records in time series, the address setting is omitted when the next branch address is the same as the immediately preceding address, so that the memory capacity is reduced.

[0010] Further, when the command of the program to be measured is fetched, it is fetched at predetermined time intervals. Also,
When the instruction of the program to be measured is fetched and the instruction is an interrupt instruction, the type of the interrupt instruction and the content of the interrupt are set in the record.

When the instruction is an interrupt instruction, the date and time are set in the record. Also,
When the instruction of the program to be measured is fetched and the instruction is a transfer instruction, the transfer amount is set in a record.

[0012] In addition, one or both of the number of instructions and the number of loops up to the branch are displayed in real time. Also, the number of instructions included in a record until branching or the name including the instruction is sorted and sequentially assigned to a page from the top to improve the execution speed.

Further, the instruction of the program to be measured is fetched, the type of the instruction, the instruction is set in a record until the branch destination appears, and the instruction type indicating the branch when the branch destination appears, and the branch destination are recorded in the record. A tracing means for repeating setting and a program functioning as a means for counting the number of instructions and the number of loops included in a record set by the tracing means until branching are stored in a storage medium, and stored in the computer system of FIG. Install and run.

[0014] Therefore, even in recent high-speed, large-scale, and decentralized situations, it is necessary to maintain performance analysis capability, secure trace and analysis capability, and automatically tune system performance while saving resources. Becomes possible.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments and operations of the present invention will be sequentially described in detail with reference to FIGS. Here, the program read from the recording medium or the program read from the hard disk device as the external storage device, or the program read and transferred from the external storage device of the center is loaded into the main storage device and started. Various processes to be described are performed.

FIG. 1 shows a system configuration diagram of the present invention.
In FIG. 1, a computer system 1 performs various processes according to a program, and is an AVM (virtual computer system) for collecting trace data of a program to be measured. The computer system 1 includes a tracing mechanism 2, an OS (operating system), a VM (virtual computer) 3, and the like.

The tracing mechanism 2 is for executing an instruction of the program to be measured executed by the VM 3, here, for example. VM3 is a virtual machine, and here,
A trace task 4 for executing the program to be measured and totalizing data collected from the program to be measured, and the CPU, memory 31, LBS 32,
It is composed of a TLB 33 and the like.

The memory 31 stores a control table 34 for setting parameters and the like necessary for performing various controls. The CPUs 0, 1, 2, and 3 are processors that perform various processes in accordance with programs, and are LBSs (Local Storage Buffers), which are memories that can be accessed at high speed.
32.

TLB (Translation Look aside Buffer)
33 is a table for converting a virtual address and an address on the main memory at high speed. Trace task 4
For example, data (records) collected from the program under measurement is totaled.

The output buffer 5 is a memory or an external storage device for storing a record in which the instruction type of the program to be measured collected by the trace mechanism 2 and the instruction until the branch destination appears are set.

The tallying buffer 6 performs tallying (totaling of the number of instructions, the number of loops, etc.) based on the records stored from the output buffer 5 and stores them. FIG. 2 shows a background explanatory diagram of the present invention.

FIG. 2A shows, as shown in FIG. 1, that four CPUs are operated in parallel and the CPU capacity is 400%.
It shows the situation at the time. The "hard" at the left end indicates the capability of the hardware, and the effective capability obtained by subtracting the capability decrease due to memory access competition and the capability decrease due to other (hard MP control, instruction usage, etc.) from 400% CPU capability. It is shown.

The "hard + soft" at the left end indicates the combined ability of the hardware and the software, and further decreases due to the software ability compared to the case of "hard" only. I have. As shown in the figure, it is effective to improve the LBS hit rate, improve the TLB hit rate, reduce lock contention (contention of exclusive access to memory access), etc., as shown in the figure. . For this reason, FIG.
By performing automatic packing of related modules as shown on the right side of FIG.

FIG. 2B shows the state of automatic packing of related modules. Here, □ is a module irrelevant to the application, and ■ is a module that operates as an extension of the application.

FIG. 2B-1 shows how the module operates on the memory. In this state,
Since the modules that operate as an extension of the app in (1) operate not in the page but in a scattered manner, the LBS hit rate, T
The LB hit rate is small, and the effective performance of the CPU is low.
For this reason, the related modules are automatically packed by one of the following (a) component system (b) CPU time system (c) (a) + (b), and as shown in (b-2) of FIG. Here, the modules that operate as an extension of the application (1) are sorted so as to operate within the page, and the CPU effective performance can be increased. The instructions of the program to be measured are traced for this purpose, and based on the results, the above (a), (b),
Alternatively, the procedure for collecting data for automatic packing of the related module in either (c) will be described in detail.

FIG. 3 is a flowchart illustrating the operation of the present invention. In FIG. 3, S1 initializes the counter table for each module. To do this, set the module name, component name, start address, and end address in the counter table for each module of the program to be measured.

In step S2, the record stored in the output buffer is initialized. This is, as shown in FIG. 4 (b) described later, as the initial setting of the record:-01 is set for the type-start address is set for the branch destination.

In step S3, a sampling process is performed. This is, as shown in FIG. 7 described later, collected for each instruction for all instructions,
Alternatively, an instruction is collected every predetermined time. In step S4, an instruction code is set in the record. This sets an instruction code in a record as shown in FIG.

At S5, it is determined whether the instruction is a branch instruction or an interrupt instruction. That is, in S4, the instruction code is sequentially set in the record, and it is determined whether a branch instruction or an interrupt instruction is set in the record. In the case of YES, the process proceeds to S6 and thereafter, and setting of the next record is started. On the other hand, in the case of NO, the process returns to S3, and the setting of the instruction code of the next instruction in the record is repeated.

In step S6, it is determined whether the output buffer is full.
In the case of YES, it is determined that the output buffer is full and it is no longer possible to store a record in which an instruction code or the like is set, so the process proceeds to S7. In the case of NO, the process proceeds to S10.

In S7, since the output buffer is found to be full, a new trace process is performed. For example, for a record stored in the output buffer of FIG. 4C described later, the number of instructions is accumulated, the number of loops is accumulated, and a process of totaling as shown in the totaling buffer of FIG. 4D is performed.

In step S8, a counting process for each module is performed. This counts the number of instructions for each module name, as shown in FIG. 6 described later. A step S9 returns the output buffer pointer to the head. In this case, since the tabulation is performed based on the records in the output buffer in S7 and S8 and stored in the tabulation buffer, the pointer is returned to the top so that the next record is stored from the top of the output buffer.

Step S10 stores the record in the output buffer. This stores the record of FIG. 4B described above in the output buffer. In S11, it is determined whether the instruction is an interrupt instruction. In the case of YES, the processing of S12 to S14 is performed. On the other hand, in the case of NO, since the instruction is other than the interrupt instruction, S15 and S16 are performed.

Since S12 has been determined to be an interrupt instruction,
Set 02 to the record type. In step S13, a branch destination of the record, an interrupt code, and an interrupt detail code are set.

In step S14, the record is stored in the output buffer. These steps S12, S13 and S14 correspond to (c) of FIG.
As shown in (2), the type is set as branch destination interrupt instruction / interrupt code detailed code 02 24 0A 2F 05 and stored in the output buffer. Then, the process returns to S3 and repeats.

On the other hand, in S15, since it is determined that the instruction is not an interrupt instruction, 01 is set in the record type. S
16 sets the branch destination of the record. These S15,
In step S16, as shown in (c) of FIG. 4, the type is set to branch destination instruction 01 18 5A46 and stored in the output buffer. Then, the process returns to S3 and repeats.

As described above, for the program to be measured, the type of instruction, branch destination address, and instruction code are stored in the record until a branch instruction or an interrupt instruction appears based on the initially set module name, component name, start address, and end address. And store it in the output buffer. When the output buffer becomes full, record information can be totaled and stored in the totaling buffer for storage.

FIG. 4 is an explanatory diagram of a trace according to the present invention.
FIG. 4A shows an example of the measured program M1. Here, the left margin indicates the address, and the left margin in the rectangle indicates the instruction code.

FIG. 4B shows an example of a record. Here, from the left side, the type, branch destination (branch destination address), and instruction code are set in a record until a branch instruction or an interrupt instruction appears and is stored. Here it is).

FIG. 4C shows an example of the output buffer. Here, in the case of a branch instruction, the instruction type 01, the branch destination (start address), and the instruction code are set and stored in the record from the top. In the case of an interrupt instruction, the instruction type 02, the branch destination (start address), the instruction code, and the detailed code 05 are set and stored in the record from the beginning, as shown in FIG. Also, the time may be entered in the record.

FIG. 4D shows an example of a totaling buffer. This is because when the output buffer in FIG. 4C becomes full, the number of instructions of the instruction code is totaled for each record, the number of loops is totaled, and the type, the branch destination, the number of instructions, and the number of loops are combined. Are sequentially set. Here, the instruction address is set as it is at the head of the branch destination, and thereafter only the last two digits are set to save the memory capacity of the totaling buffer.

As shown at the right end, the module name M
The number of instructions is displayed in real time in association with 1, and the progress is notified to the operator. FIG. 5 shows a flowchart of the new trace processing of the present invention. This shows the detailed processing flowchart of S7 in FIG. 3 described above.

In FIG. 5, S21 sets an instruction record creation flag to OFF. In step S22, one record is extracted from the output buffer. In step S23, the type is determined. This means that, for example, one record, for example, a record is extracted from the output buffer of FIG.
The type is determined to be “01” (instruction record). Type is 0
If it is determined to be 1 (instruction record), the process proceeds to S24. On the other hand, if the type is 02 (interrupt record), the process proceeds to S33.

S24 is 01 (instruction record) in S23
Then, the number of instructions is counted. In step S25, the total is counted up. In S24 and S25, for example, in the case of the record 01 185A46 in FIG. 4C described above, the number of instructions is counted as 2 of 5A46, and the cumulative total is counted up.

In step S26, the command record creation flag is set to O
One of N / OFF is determined. When it is ON (when it was previously turned ON in S31), the process proceeds to S27. OFF
In the case of, the process proceeds to S29.

In step S27, it is determined whether the number of instructions in the output buffer is equal to the number of instructions in the totaling buffer. This is to determine whether or not a loop has occurred.
In the case of YES, it has been determined that a loop has occurred, so S
At 28, the number of loops is incremented by 1, and the process returns to S22. On the other hand, in the case of NO, it is determined that no loop has occurred, so the flow proceeds to S29.

At S29, an instruction record is being created at S26 =
Since it is determined that the loop is not executed even if the command is OFF or the command record is being created = ON, the pointer of the totaling buffer is advanced.

In step S30, the branch destination, the number of instructions, and the number of loops are set in the counting buffer. A step S31 sets the command record being created = ON. In step S32, the number of loops is set to zero. Then, the process returns to S22 and is repeated.

Type 01 of S23 (instruction record)
In the case of (1), the number of instructions and the number of loops can be totaled for one record extracted from the output buffer through S24 to S32.

In step S33, since the type 02 (interrupt record) of step S23 has been determined, the pointer of the totaling buffer is advanced. A step S34 stores the interrupt record in the tally buffer.

A step S35 sets the command record being created = OFF. In the case of the type 02 (interrupt record) in S23 described above, one record extracted from the output buffer is stored in the totaling buffer as it is in S33 to S35.

FIG. 6 is a flowchart showing a counting process for each module according to the present invention. This corresponds to S8 in FIG.
It is a detailed process flowchart of. In FIG. 6A, S41 initializes a variable I = 1.

In the step S42, it is determined whether or not the condition 1 is satisfied. That is, it is determined whether the branch destination of the counting destination buffer calculated in the flowchart of FIG. 5 described above satisfies the following condition 1 shown in the drawing. If YES, the number of instructions is added to the I-th counter in S44. On the other hand, if NO, the variable I is incremented by 1 in S43, and S42 is repeated.

Condition 1: (branch destination of total buffer ≧ start address of counter table for each module) AND (branch destination of total buffer ≦ end address of counter table for each module) By the above procedure, the module shown in FIG. As shown in the separate counter table, the number of counters for each module name is totaled.

FIG. 7 shows a flowchart of the sampling process according to the present invention. This shows the detailed processing flowchart of S3 in FIG. 3 described above. In FIG. 7, S51 determines whether the sampling mode is set. In the case of YES, an instruction is sampled from the program to be measured every predetermined time in S52. On the other hand, in the case of NO, all instructions are sampled from the program to be measured for each instruction. And the already described FIG.
To S4.

As described above, if the sampling mode is set, instructions are sampled at predetermined time intervals, and if the sampling mode is canceled, all instructions are sampled one by one, and the trace processing after S4 in FIG. Can be arbitrarily switched.

FIG. 8 is a diagram for explaining transfer length collection according to the present invention. This shows how the transfer length is set in the record by taking an example of executing the transfer instruction MVC 0 (5, 2), 0 (1) in FIG. 8A.

FIG. 8B shows the transfer state of FIG. 8A. The transfer instruction shown in FIG. 8A transfers the data in the 5-byte area indicated by the register 1 to the register 2
5 schematically shows that the instruction is a command to be transferred to the 5-byte area shown in FIG.

FIG. 8C shows records stored in the output buffer. Here, as shown in the figure, two records of the type "03" representing the transfer record are output as shown in the figure following the type "01" representing the instruction record at the head. Here, “05” at the end of the record of the second type “03” indicates the transfer length.

As described above, when the instruction is a transfer instruction, the transfer length is added to the transfer record (type 03). As a result, the transferred transfer length can be set in the record.

FIG. 9 is a flow chart for explaining the operation of the present invention (trace end processing). In FIG. 9, S61
Determines the method. This is to determine the sorting method for the module-by-module counter table of FIG. 6B, which is tabulated in accordance with S8 of the flowchart of FIG.

(A) If the component type is determined, the counter table for each module is sorted using the component name as a key in S62 (the second key is a counter,
That is, if the component names are the same, the components are sorted by the counter value.) For example, the component names are sorted like COMP-01 COMP-02 COMP-03. By sorting by component name, it is possible to improve the hit rate (see FIG. 2) by grouping similar names together (arranging components having similar names on the same page).

(B) If it is determined that the CPU time method is used, the counter table for each module is sorted in ascending order using the counter as a key in S63 (the second key is the component name, ie, if the counter values are the same, the component is Sort by name). By sorting by CPU time (number of instructions), modules that use a lot of instructions can be grouped together (modules that use a lot of instructions are grouped and arranged on the same page) to improve the hit rate (see FIG. 2). Become.

(C) When the methods (a) and (b) are used together, the counter table for each module is sorted in ascending order using the counter as a key in S64 (the second key is the module name, that is, the counter value is the same). When the module name is a key, the module-specific counter table is sorted (the second key is a counter, that is, when the module names are the same, the counter value is sorted).

In step S66, a packing list is created from the module-specific counter table. This specifies a module name for each page as follows (packing list) (M1, M2, M3...).

In step S67, the packing list is output to system parameters. As described above, the components are sorted based on the component name, the counter value, and the module name based on the module-specific counter table in FIG.
It is possible to create an optimal packing list for each and output it to a system parameter, arrange an optimal module in a page, and improve the hit rate.

[0067]

As described above, according to the present invention,
A count table for each module by fetching the instruction of the program to be measured, setting the instruction type and the instruction in a record until a branch destination appears, and counting the number of instructions and the number of loops included in the set record until branching, etc. And the packing list is created by sorting by module name, counter value, and component name.This saves resources even in recent high-speed, large-scale, and decentralized situations. While maintaining the performance analysis capability, the trace and analysis capability can be secured, and the system performance can be automatically tuned. As a result, (1) the amount of trace can be reduced to about 1/10 of the conventional amount. (2) It is easy to know how many times the vehicle has traveled on the same route as the number of loops. (3) Operation can be simplified. (4) Time series analysis and progress can be displayed. (5) Performance evaluation (instruction count) and debugging (such as coverage test) can be performed simultaneously. (6) System performance can be automatically tuned.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of the present invention.

FIG. 2 is a background explanatory diagram of the present invention.

FIG. 3 is a flowchart illustrating the operation of the present invention.

FIG. 4 is an explanatory diagram of a trace according to the present invention.

FIG. 5 is a flowchart of a new trace process of the present invention.

FIG. 6 is a flowchart of a counting process for each module according to the present invention.

FIG. 7 is a flowchart of a sampling process according to the present invention.

FIG. 8 is an explanatory diagram of transfer length collection according to the present invention.

FIG. 9 is a flowchart illustrating the operation of the present invention (trace end processing).

[Explanation of symbols]

 1: Computer system 2: Tracing mechanism 3: VM (virtual computer) 31: Memory 32: LBS 33: TLB 4: Trace task 5: Output buffer 6: Total buffer

Claims (10)

[Claims] In a computer system for tracing a program to be measured, an instruction of the program to be measured is fetched, and a type of the instruction,
Trace means for repeating setting an instruction in a record until a branch destination appears; and means for counting the number of instructions and the number of loops until branching included in the record set by the trace means. Computer system. 2. The computer system according to claim 1, wherein the address of the branch instruction, the number of instructions until branching, and the number of loops are output in chronological order. 3. The method according to claim 1, wherein when sequentially setting the record in time series, the address setting is omitted when the next branch address is the same as the immediately preceding address.
Alternatively, the computer system according to claim 2. 4. The method according to claim 1, wherein when the instruction of the program to be measured is acquired, the instruction is acquired at predetermined time intervals.
4. The computer system according to claim 3, wherein: 5. The method according to claim 1, wherein when the instruction of the program to be measured is fetched, if the instruction is an interrupt instruction, the type of the interrupt instruction and the content of the interrupt are set in a record. 5. The computer system according to claim 4. 6. When the instruction is an interrupt instruction,
6. The computer system according to claim 5, wherein a date and time are set in said record. 7. The transfer method according to claim 1, wherein when the instruction of the program under measurement is fetched, if the instruction is a transfer instruction, the transfer amount is set in a record. Computer system. 8. The computer system according to claim 1, wherein one or both of the number of instructions and the number of loops until the branch is taken is displayed in real time. 9. Sorting by the number of instructions included in the record before branching or the name including the instruction,
9. The computer system according to claim 1, further comprising means for sequentially allocating pages from the top. 10. A tracing means for fetching an instruction of a program to be measured and repeatedly setting the type of the instruction and the instruction in a record until a branch destination appears, and a tracing means included in the record set by the tracing means. A storage medium storing a program functioning as a means for counting the number of instructions and the number of loops.