JP2005165825A - Trace information recorder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform tracing in a system having a large number of CPUs used therein. <P>SOLUTION: A trace information recorder records trace information to analyze a program execution process including a plurality of instructions to be performed by the CPUs in the system where the CPUs are mounted. The recorder is provided with: an interface to be connected to a bus to which status signals to be externally outputted by the CPUs and the CPUs are connected; a condition monitor means for storing a trace start condition and a trace termination condition, monitoring the generation of the start and termination conditions, and generating a trace performance signal; a recording control means for starting/terminating tracing on the basis of a tracing execution signal generated by the condition monitor means, and recording the trace information in a trace area during tracing execution period; and the trace area for recording the trace information. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a trace information recording apparatus for executing CPU tracing in a system in which a plurality of CPUs are mounted.

  One method for debugging a program of a system in which a CPU is mounted is to trace an instruction execution history. Furthermore, when a plurality of CPUs are mounted, it is necessary to record information that makes the synchronization relationship between the CPUs clear. There is a trace technology that focuses on such cooperative operation by a plurality of CPUs (see, for example, Patent Documents 1 and 2). In these technologies, a trace device is provided for each CPU, and each trace device can operate synchronously. The trace information of the CPU to be traced is recorded together with the time, and the last traced information is rearranged in order of time. This is to make it easier to grasp the synchronization relationship.

JP-A-5-128079 Japanese Patent Laid-Open No. 10-260864

  However, since these trace information is recorded independently for each CPU to be traced, the number of monitoring units and recording units for tracing is required by the number of CPUs, and a system in which many CPUs are used from the viewpoint of circuit scale. It was not suitable for tracing. When the CPU has a cache, tracing is difficult only by bus observation.

  The present invention has been made in view of the above problems, and the object of the present invention is to reduce the increase in the scale of the trace circuit even when taking a trace of a large number of CPUs, and to unify regardless of the presence or absence of a CPU cache. It is an object of the present invention to provide a trace information recording apparatus that can be traced by a typical method.

  In order to achieve the above object, the invention according to claim 1 is a trace information record for recording trace information for analyzing the execution progress of a program including a plurality of instructions executed by a CPU of a system in which a plurality of CPUs are mounted. In the device, the status signal output by the CPU to the outside, the interface connected to the bus to which the CPU is connected, the start condition and end condition of the trace, and the occurrence of the start condition and end condition are monitored. Condition monitoring means for generating a trace execution signal, recording control means for starting and ending trace based on the trace execution signal generated by the condition monitoring means, and recording trace information in the trace area during the trace execution period, and trace And a trace area for recording information.

  According to a second aspect of the present invention, in the first aspect of the present invention, an input signal to the CPU is also input to the trace information recording device.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, a time measuring unit for generating time information is provided, and the recording control unit is generated by the time measuring unit when recording the trace information in the trace area. The time information is also recorded.

  Invention of Claim 4 provides the information selection means which memorize | stores the information for selecting the trace information used as recording object in the invention in any one of Claims 1-3, and produces | generates a trace information selection signal, The recording control means records the trace information corresponding to the trace information selection signal during the trace execution period.

  According to a fifth aspect of the invention, in the invention according to any one of the first to fourth aspects, the recording control unit records a change state of the trace information only when the trace information changes.

  The invention according to claim 6 is the invention according to any one of claims 1 to 5, wherein the recording control unit sets an identifier for the trace information and records the changed trace information together with the identifier. And

  According to the present invention, since it is not necessary to have the same number of bus interfaces as the CPUs by tracing a plurality of CPUs, an increase in the scale of the trace circuit can be reduced even when tracing a large number of CPUs. In addition, tracing can be performed by a unified method regardless of whether or not the CPU has a cache.

  Embodiments of the present invention will be described below with reference to the accompanying drawings.

<Embodiment 1>
FIG. 1 is a configuration diagram of a trace information recording apparatus according to Embodiment 1 of the present invention.

  In FIG. 1, 100 is a trace information recording device, 101 is an interface for fetching a status signal output from the CPU to the outside, 102 is a memory for storing the start condition and end condition of the trace, and the start condition and end condition. Condition monitoring means for monitoring occurrence and generating a trace execution signal, and 103 starts / ends trace based on the trace execution signal generated by the condition monitoring means 102, and trace information is displayed in the trace area during the trace execution period. 104 is a trace area for recording the trace information written by the record control means 103, 111 is a first CPU of a system in which a plurality of CPUs are mounted, and 112 is the first CPU. 2 is a CPU, and 113 is an n-th CPU.

  The operation of this embodiment will be described below with reference to FIGS.

  FIG. 5 shows an example of transition of the program counter of each CPU and data on the bus. BUS ADDR is an address on the bus, BUS DATA is data on the bus, BUS R / W is a signal indicating whether the bus transaction is a read or write, BUS Master ID is an ID indicating the bus master, REQ is a bus transaction request signal, ACK is An acknowledge signal of the bus transaction, CPU 111 PC indicates a program counter of CPU 111, CPU 112 PC indicates a program counter of CPU 112, and CPU 113 PC indicates a program counter of CPU 113, respectively.

  The CPUs 111 to 113 have a signal for outputting the value of the program counter to the outside, and the signal indicating the program counter value is connected to the trace information recording apparatus 100. The trace information recording apparatus 100 is connected to the program counter output signals of the CPUs 111 to 113 and the bus via the interface 101. In the condition monitoring unit 102, the bus access and the program counter values of the CPUs 111 to 113 which are the conditions for asserting the trace execution signal and the conditions for deasserting the trace execution signal are recorded, and the monitoring target signal satisfies the assertion condition. The trace execution signal is asserted until the deassertion condition is satisfied.

  For example, the trace start condition is set when the program counter of the CPU 113 is not 0, and the trace end condition is set when the CPU 112 writes to the register of the CPU 111. The recording control means 103 is stopped while the trace execution signal is deasserted. When the trace execution signal is asserted, the value of the program counter of the CPUs 111 to 113, the address of the bus transaction by the CPUs 111 to 113, data, Read / write and master ID are written in the trace area. That is, the CPU 113 PC becomes 1 at T2, and the trace start condition is satisfied, so that recording of trace information is started from t2. Assuming that A2 in FIG. 5 indicates the address of a certain resource in the CPU 111, t11 (or t12) is a write access from the CPU 112 to the CPU 111, so the recording of the trace information is finished at this point.

  When debugging, if all the initial values of the CPU resources are known, the program counter value at each time can be identified if the CPU executes the instruction, the branch is established, and the data captured by the CPU is known. Is possible. Instead of having a program counter output signal, the CPUs 111 to 113 output an instruction execution signal and a branch establishment signal that are asserted for one clock cycle every time instruction execution starts and every branch establishment of the program. The same effect can be obtained when the trace start / end conditions and the trace target.

  FIG. 6 is a diagram illustrating an example of an instruction execution signal and a branch establishment signal.

  In FIG. 6, an instruction corresponding to PC = 13 is executed at t1, and the PC transits. At t2, a branch is established by an instruction with PC = 15, so that PC = A5 at t3, and PC = B1 at t5. However, it is assumed that the program ends with the last execution of the instruction PC = B0 at t4. If the instruction execution signal is asserted, the PC value advances by one instruction at the next timing, and does not change if it is deasserted. If the branch establishment signal is asserted, the branch destination address can be specified by analyzing the program, and at the next timing, a transition is made to the PC value indicating the branch destination.

<Embodiment 2>
FIG. 2 is a configuration diagram of the trace information recording apparatus according to the second embodiment.

  In FIG. 2, 200 is a trace information recording device, 201 is an interface that captures a status signal output to the outside by the CPU and an input signal common to the input signal to the CPU, and 202 is a trace start condition and end. Condition monitoring means for storing a condition and monitoring occurrence of a start condition and an end condition to generate a trace execution signal. Reference numeral 203 denotes a trace start / end based on the trace execution signal generated by the condition monitoring means 202. Recording control means for recording the trace information in the trace area during the trace execution period, 204 is a trace area for recording the trace information written by the recording control means 203, and 111 is a system in which a plurality of CPUs are mounted 1 is the first CPU, 112 is the second CPU, 11 Is the CPU of the n.

  In this embodiment, by recording an input signal to the CPU, it is possible to easily identify factors such as branching, temporary stop, and operation restart in the CPU. The common input signal to the CPU and the trace recording device corresponds to an interrupt signal, a resume signal serving as a trigger for returning from the suspended state to the operating state, and the like.

<Embodiment 3>
FIG. 3 is a block diagram of a trace information recording apparatus according to Embodiment 3 of the present invention.

  300 is a trace information recording device, 301 is an interface that captures a status signal output by the CPU to the outside and an input signal common to the input signal to the CPU, and 302 stores the start condition and end condition of the trace. And a condition monitoring unit that generates a trace execution signal by monitoring occurrence of a start condition and an end condition, and 303 starts and ends the trace based on the trace execution signal generated by the condition monitoring unit 302 to execute the trace. Recording control means for recording the trace information in the trace area during the period, 304 is a trace area for recording the trace information written by the recording control means 303, and 305 is a time measuring means.

  In the present embodiment, time information is recorded together when recording trace information. In particular, status signals such as instruction execution signals and branch establishment signals are recorded with time information added to information that can identify the identifier and change of the target signal only when a change occurs, or a bus transaction is completed. At the time, the trace area is reduced by adding time information to the address, data, read / write, and master ID and recording. This embodiment also includes the case where only the changed signal is set by setting an identifier for each trace information.

<Embodiment 4>
FIG. 4 is a configuration diagram of the trace information recording apparatus according to the fourth embodiment.

  Reference numeral 400 denotes a trace information recording apparatus, 401 denotes an interface that captures a status signal output by the CPU to the outside and an input signal that is common to the input signal to the CPU, and 402 stores a trace start condition and an end condition. And a condition monitoring means for generating a trace execution signal by monitoring the occurrence of the start condition and the end condition, and 403 starts and ends the trace based on the trace execution signal generated by the condition monitoring means 402 to execute the trace. Recording control means for recording the trace information designated by the information selection means 405 during the period in the trace area, 404 is a trace area for recording the trace information written by the recording control means 403, and 405 is information to be traced Selection information, and the consumption of information when recording each selection information. Is information selecting means for outputting a signal for designating the trace information to the recording control unit 403 stores the betting amount and format.

  In this embodiment, only information necessary for debugging is traced among a plurality of CPUs or bus transactions. In particular, in a system in which multiple CPUs are mounted, when all the CPUs are not operating synchronously or related to each other, tracing all the information unnecessarily makes the trace information complicated and enormous. Inefficient. By limiting the trace information, the trace area is reduced and debugging is made more efficient.

  The present invention is applicable to a trace information recording apparatus that performs CPU tracing in a system in which a plurality of CPUs are mounted.

It is a block diagram of the trace information recording device which concerns on Embodiment 1 of this invention. It is a block diagram of the trace information recording device which concerns on Embodiment 2 of this invention. It is a block diagram of the trace information recording device which concerns on Embodiment 3 of this invention. It is a block diagram of the trace information recording device concerning Embodiment 4 of this invention. It is a figure which shows the example of the input signal to a trace recording apparatus. It is a figure which shows the example of an instruction execution signal and a branch establishment signal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Trace recording apparatus 101 Interface 102 Condition monitoring means 103 Recording control means 104 Trace area 111 1st CPU
112 second CPU
113 nth CPU
DESCRIPTION OF SYMBOLS 120 Bus 200 Trace recording apparatus 201 Interface 202 Condition monitoring means 203 Recording control means 204 Trace area 300 Trace recording apparatus 301 Interface 302 Condition monitoring means 303 Recording control means 304 Trace area 305 Time measuring means 400 Trace recording apparatus 401 Interface 402 Condition monitoring means 403 Recording control means 404 Trace area 405 Information selection means

Claims (6)

In a trace information recording device for recording trace information for analyzing the execution progress of a program including a plurality of instructions executed by a CPU of a system in which a plurality of CPUs are mounted,
A status signal output from the CPU to the outside, an interface connected to the bus to which the CPU is connected, a trace start condition and an end condition, and a trace execution signal by monitoring the occurrence of the start condition and the end condition Condition monitoring means for generating trace information, recording control means for starting and ending the trace based on the trace execution signal generated by the condition monitoring means, and recording the trace information in the trace area during the trace execution period, and recording the trace information And a trace information recording apparatus, wherein the trace information recording apparatus comprises:   2. The trace information recording apparatus according to claim 1, wherein an input signal to the CPU is also input to the trace information recording apparatus.   3. A time measuring means for generating time information is provided, and the recording control means records the time information generated by the time measuring means together when recording the trace information in the trace area. Trace information recording device.   Information selection means for storing information for selecting trace information to be recorded and generating a trace information selection signal is provided, and the recording control means records the trace information corresponding to the trace information selection signal during the trace execution period. The trace information recording apparatus according to claim 1, wherein the trace information recording apparatus is a recording apparatus.   5. The trace information recording apparatus according to claim 1, wherein the recording control unit records a change state of the trace information only when the trace information is changed.   6. The trace information recording apparatus according to claim 1, wherein the recording control unit sets an identifier for the trace information, and records the changed trace information together with the identifier.

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