JP2000348007A - System and method for synchronizing operation tracing time for multi-processor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate trace data using common time among processors. SOLUTION: A micro-counter register 25 in a synchronous control board 20 registers time which is counted by the order of micro-seconds and which is common to processors 1 to (n). Respective processors 1 to (n) refer to the micro-counter register 25 in case of need through a common bus 30. At the time of tracing, the generation time of events generated in each processor is read from the micro-counter register 25, the entry of trace information which is made to correspond to trace data at every event is generated, the entries of trace information are arranged on a time sequence where time is clocked and are stored in a main storage device 10 as trace information 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operation trace time synchronizing method and method for a multiprocessor system, and more particularly, to measuring an elapsed time using a common time between processors and measuring the time for each event. The present invention relates to an operation trace time synchronization method and method for a multiprocessor system used for displaying trace result information and the like.

[0002]

2. Description of the Related Art Conventionally, in a multiprocessor system, as shown in FIG.
To 10n respectively correspond to clock tick counters 111.
To 11n, and this counter outputs time-lapse information in units of microseconds.

At this time, clock tick counters 111 to
Although the count values indicated by 11n may coincide in units of seconds, they usually do not coincide in units of microseconds.

[0004] A retrospective search of the known art related to the present invention from past patent applications reveals that, first, Japanese Patent Application Laid-Open No. 3-113647.
In the system disclosed in Japanese Patent Application Laid-Open Publication No. H10-260, in a system having a plurality of processors, a tracer installed in each processor traces the processing in each processor using a common clocking means for each processor, and the trace result is stored in each processor. A technique for accumulating data in a RAM installed in a RAM is disclosed.

Japanese Patent Application Laid-Open No. 7-36735 discloses that
There is disclosed a debugging apparatus in which a tracer for extracting an event generated as a result of execution of a multiprocessor system executing a program to be debugged from a common bus and storing the event is provided.

Further, Japanese Patent Laid-Open Publication No. Hei 10-260864 discloses a technique in which event information emitted from a microprocessor is stored in a trace memory by a trace device (having a time information section) connected to a common bus. I have.

[0007]

However, in the prior art, since the count values indicated by the clock tick counters 111 to 11n do not match in units of microseconds, they are displayed using a common time among the processors. It is difficult to display the event information of each processor to be displayed and to arrange the event information generated in each processor in time series.

For example, the counter value of the trace information in each processor is reversed between the preceding and following data, or the counter value at the start of a certain process whose execution time is measured is larger than the counter value at the end of the process. In such a case, there is a problem that the execution time of the above processing becomes negative.

For this reason, for example, in a debugging operation using a tracer of a program executed on a multiprocessor system, it is difficult to accurately and temporally grasp the causal relationship of trace results output from each processor. Had become.

If it is desired to measure the execution time of a specific process, the process is started by only one processor, and if it is to be ended, the processing time consumed by the difference between the start and end counter values can be measured. Although it is easily possible, when the processing is executed in the middle of another processor, only the counter value using a different time on each processor (however, a different time in the order of microsecond) can be referred to. Therefore, the measurement result of the consumed processing time becomes incorrect.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a means for measuring an elapsed time by using a common time between processors.

In the technique disclosed in Japanese Patent Application Laid-Open No. 3-113647, the method of using the time that is commonly clocked between the processors is limited to a method closed to the individual processors. It does not disclose how to measure the elapsed time of processing spanning between processors or to use the trace results of each processor in a time-series arrangement in a common storage device. In addition, a specific configuration of a clock means for clocking a common time between the processors is not disclosed.

The technique disclosed in Japanese Patent Application Laid-Open No. 7-36735 requires installation of a commonly used tracer. It does not disclose measuring the elapsed time (in microseconds) using a common time between the processors. Further, the tracer detects only the event information released from each multiprocessor to the common bus, and detects the progress of the process closed in each multiprocessor as event information and cannot include the progress in the trace information. .

Furthermore, the technique disclosed in Japanese Patent Application Laid-Open No. 10-260864 requires a new installation of a commonly used tracer. Also, what the tracer detects is
It is only the event information released from each multiprocessor to the common bus, and the progress of the process closed in each multiprocessor is detected as event information and cannot be included in the trace information.

The present invention has been made in view of the above-described problems in the conventional multiprocessor system, and it is not necessary to use elapsed time information measured using a common time between processors. It is an object of the present invention to provide an operation trace time synchronization method and a method thereof for a multiprocessor system which can be performed.

[0016]

An operation trace time synchronization method for a multiprocessor system according to the present invention comprises:
A plurality of processors, a main storage device shared by the plurality of processors, and a timing device for timing a time common to the plurality of processors are connected by a common bus, and the timing device counts time. And a counting means for counting the time counted by the time counting means, wherein each of the plurality of processors generates trace data each time a predetermined event occurs, and an operation trace when the event occurs Time input means for inputting time from the numerical means, and trace information storage means for creating trace information by associating the trace data with the trace time, and storing the trace information in the main storage device; It is characterized by having.

In the operation trace time synchronization method for a multiprocessor system according to the present invention, in the operation trace time synchronization method for a multiprocessor system described above, the timing means may include a clock cycle and the timing of the timing means. A conversion ratio storage unit that stores a conversion ratio with a period; a clock monitoring unit that monitors the clock and generates an interrupt every period of the clock; and a count value is incremented by 1 each time the interrupt occurs. A counter that resets the count value when the count value reaches the conversion ratio, and an adding unit that adds one to the number set by the numerical unit each time the counter is reset. It is characterized by the following.

Further, in the operation trace time synchronization method for a multiprocessor system according to the present invention, in the above operation trace time synchronization method for a multiprocessor system, the trace information storage means stores the trace information in the main storage. When existing trace information is stored in the main storage device, the trace information and the existing trace information are arranged in the order of the operation trace time.

An operation trace time synchronization method for a multiprocessor system according to the present invention is an operation for a multiprocessor system in which a plurality of processors and a main storage device shared by the plurality of processors are connected by a common bus. In the trace time synchronization method, a clocking step of clocking time, a counting step of counting the time counted by the counting step in a counting means, and each of the plurality of processors trace data every time a predetermined event occurs. A time input step of inputting an operation trace time at the time of occurrence of the event from the numeral means; and a step of generating the trace data and the trace. Trace information is created in association with the time, and the trace information is And trace information storing step of storing the 憶 apparatus, characterized by having a.

In the operation trace time synchronizing method for a multiprocessor system according to the present invention, in the above operation trace time synchronizing method for a multiprocessor system, the clocking step includes a clock cycle and a clocking of the clocking step. A step of storing a conversion ratio with a period in a conversion ratio storage unit; a step of monitoring the clock; and a step of monitoring a clock for generating an interrupt every cycle of the clock; and a step of: A counting step of adding 1 and resetting the count value of the counter when the count value reaches the conversion ratio, and increasing the number set by the number setting means by 1 each time the counter is reset. And an adding step of adding.

Further, the operation trace time synchronizing method for a multiprocessor system according to the present invention is the operation trace time synchronizing method for a multiprocessor system, wherein the trace information storing step includes the step of storing an existing trace in the main storage device. If trace information exists,
The trace information and the existing trace information are arranged in the order of the operation trace time.

In the present invention, a plurality of processors,
In a multiprocessor system in which a main storage device shared by the processors and a main storage device are arranged on a common bus, further, by connecting a clock device for supplying elapsed time information in units of microseconds to the common bus, Of processors that can supply the elapsed time information in microsecond units can be commonly used.

More specifically, they are connected by a common bus,
When a plurality of processors operating individually need elapsed time information in units of microseconds, each processor is connected to the common bus and is provided with a counter register in units of microseconds in a commonly installed timing device. , It is possible to obtain common elapsed time information among the processors.

As a result, the occurrence times of the events occurring in each processor can be grasped in a microsecond order and in a unified manner, so that it is easy to arrange them in a unique time series.

Further, the value of the counter register is incorporated into trace information in association with trace data for each event generated in each processor, and the trace information is
By arranging the values of the counter register in a time series to be carved and storing them in the main storage device, it is possible to grasp the trace data corresponding to the event in a time series.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an overall configuration of a multiprocessor system according to an embodiment of the present invention.

The multiprocessor system according to the present embodiment includes a plurality of processors 1 connected to a common bus 30.
, A synchronous control board (time measuring device) 20, a main storage device 10 shared by the processors 1 to n, and a common bus 30.
Having.

In addition to the above, a board for communication or a board for accessing a peripheral device such as a disk may be connected to the common bus 30, but is omitted because it has no direct relation to the present invention. I do.

The processors 1 to n can perform processing independently or in parallel.

The main storage device 10 is a storage device common to the processors 1 to n for storing an instruction group for the processors 1 to n to perform processing and data necessary for the above processing. In the present embodiment, the main storage device 10 also stores trace information 11 described later.

The processors 1 to n perform processing using the instructions and data loaded in the main storage device 10 and store the processing results in the main storage device 10.

The synchronization control board 20 includes processors 1 to n
Is a processing unit that measures the time common to the microseconds in the order of microseconds and causes the processors 1 to n to refer to the time.
, A clock counter 24, a microsecond counter control unit 23, and a microsecond counter register 25 that stores the time in microsecond units.

The trace information 11 is an example of the use of the common time in units of microseconds. The trace information 11 includes trace data for each event generated in each of the processors 1 to n together with the event occurrence time (operation trace time). This is a table arranged on the series. However, processors 1 to
When n performs the time-series arrangement, a time common to the processors 1 to n, that is, the value of the microsecond counter register 25 is used as the time at which the time series is carved.

The microsecond ratio storage unit 22 stores a ratio for converting the number of clocks (common to the system) supplied to the synchronization control board 20 into a time lapse in microsecond units. It is.

The clock monitoring unit 21 is a monitoring unit that monitors a clock common to the above-mentioned systems and generates an interrupt to the microsecond counter control unit 23 when the clock changes by one period.

The microsecond counter control unit 23 is started by an interrupt from the clock monitoring unit 21, and has a final purpose of incrementing the microsecond counter register 25 every microsecond.

The clock counter 24 is a counter which is incremented each time the clock changes by the microsecond counter control unit 23. When the value reaches the value of the microsecond ratio storage unit 22, the time elapses by one microsecond. At this point, the microsecond counter control unit 2
3 is reset.

The microsecond counter register 25 is incremented by one by the microsecond counter control unit 23 every time one microsecond elapses, that is, each time the clock counter 24 is reset, and holds the time elapse in microsecond units. Register (storage unit). The processors 1 to n can access the above registers in the same manner as the main storage device 10 or in a separate address space.

FIG. 2 is a table showing the configuration of trace information 11 stored in main storage device 10 of the multiprocessor system according to the embodiment of the present invention.

The table shown in FIG. 2 has entries for storing trace data of each event. Each entry contains the operation trace time when the event occurred,
Trace data including an event type and accompanying information is stored.

FIG. 3 is a flowchart showing the operation of the microsecond counter control unit 23 of the multiprocessor system according to the embodiment of the present invention.

Hereinafter, the microsecond counter control unit 23 of the multiprocessor system according to the present embodiment will be described with reference to FIGS.
, That is, the operation of setting the elapsed time information (counter value) in the microsecond counter register 25 will be described.

The clock monitoring unit 21 is provided for the synchronization control board 2
The clock supplied to 0 is monitored, and when it changes, the microsecond counter control unit 23 is started.

First, in step S1, the microsecond counter control unit 23 increments the clock counter 24 (ie, adds 1).

Next, in step S2, the value of the clock counter 24 is compared with the value of the microsecond ratio storage unit 22. If the two values do not match, the process ends, and if the values are the same, the following process is performed.

First, in step S3, the clock counter 24 is reset to zero.

Next, in step S4, the microsecond counter register 25 is incremented.

In the above procedure, the microsecond counter register 25 is incremented by one every time one microsecond elapses.

FIG. 4 shows a microsecond counter register 25 of the multiprocessor system according to the embodiment of the present invention.
5 is a flowchart showing a processing operation of each processor which reads out a value of the data and uses the value for trace data.

Each of the processors 1 to n may generate an event to be stored as trace data in the course of executing the instruction. In such a case, each of the processors 1 to n traces the information on the event in association with the operation trace time using the time commonly measured between the processors by the synchronous control board 20. The data is stored in the main storage device 10 as data.
The time that is commonly measured is the value of the microsecond counter register 25 (counter value).

In the description below, it is assumed that an event has occurred in the processor 1, but the same operation is performed when the event has occurred in the other processors 2 to n.

First, when a predetermined event occurs, the processor 1 reads the value of the microsecond counter register 25 of the synchronous control board 20 connected to the common bus 30 as an operation trace time in step S10.

Next, in step S11, the processor 1
Edits data (for example, processor number, event type, and attached information) indicating the nature of the event that has occurred, and creates trace data from the edited result.

Finally, in step S12, the processor 1 creates an entry of trace information by associating the operation trace time with the created trace data, and stores the entry in the trace information 11 in the main storage device 10. Record as information for the entry.

At this time, if there are other entries already recorded in the trace information 11, the operation trace time of those entries is compared with the operation trace time of the entry to be recorded. , It is possible to arrange all the trace information entries in a time series of the operation trace time.

In the above-described embodiment, the time measured commonly by the processors, that is, the value (counter value) of the microsecond counter register 25 is used as trace information. The multiprocessor system does not necessarily need to limit the counter value to the above application, and can use the counter value for other applications.

[0058]

According to the present invention described above, all the processors in the system can refer to the same microsecond counter register in common, so that the operation between the processors is managed in one time series. It becomes possible.

It is also possible to measure the elapsed time of a specific process or the occurrence time of a specific event at a common time between processors.

Further, by connecting the synchronization control board, it is possible to extract and refer to the elapsed time information in units of microseconds as a counter value without depending on the clock built in each processor. In addition, it is possible to measure and display the execution time of each processor for the processing executed across a plurality of processors.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an operation trace time synchronization method for a multiprocessor system according to an embodiment of the present invention.

FIG. 2 is a table showing a configuration of trace information 11 stored in a main storage device 10 of an operation trace time synchronization method for a multiprocessor system according to an embodiment of the present invention.

FIG. 3 is a flowchart showing an operation of a microsecond counter control unit 23 of the operation trace time synchronization method and method for the multiprocessor system according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating an operation trace time synchronization method and method for a multiprocessor system according to an embodiment of the present invention;
5 is a flowchart showing an operation of a process of reading out the value of “.” And using it for trace data.

FIG. 5 is a block diagram showing an overall configuration of a conventional multiprocessor system.

[Explanation of symbols]

 1 to n processor 10 main storage device 11 trace information 20 synchronization control board 21 clock monitoring unit 22 microsecond ratio storage unit 23 microsecond counter control unit 25 microsecond counter register 30 common bus

Claims (6)

[Claims] 1. A plurality of processors, a main storage device shared by the plurality of processors, and a timing device for timing a time common to the plurality of processors are connected by a common bus, and Counting means for counting time, and counting means for counting the time counted by the time counting means, wherein each of the plurality of processors generates trace data every time a predetermined event occurs, and Time input means for inputting an operation trace time at the time of occurrence from the numeral means; and trace information for creating trace information by associating the trace data with the trace time, and storing the trace information in the main storage device Storage means; and an operation trace time synchronization method for a multiprocessor system. 2. The clock unit includes: a conversion ratio storage unit that stores a conversion ratio between a clock period and a clock period of the clock unit; and a clock that monitors the clock and generates an interrupt at each clock period. A monitoring unit; a counter for incrementing the count value by 1 each time the interrupt occurs; and a counter for resetting the count value when the count value reaches the conversion ratio; and a counter for resetting the counter each time the counter is reset. 2. The operation trace time synchronization method for a multiprocessor system according to claim 1, further comprising: an adding means for adding one to the number set by the means. 3. The trace information storage means, when storing the trace information in the main storage device, if there is existing trace information in the main storage device, the trace information and the existing trace information. Are arranged in the order of the operation trace times.
Or an operation trace time synchronization method for the multiprocessor system according to 2. 4. An operation trace time synchronization method for a multiprocessor system in which a plurality of processors and a main storage device shared by the plurality of processors are connected by a common bus, wherein a time counting step is performed. A counting step of counting the time counted by the time counting step in a counting means; each of the plurality of processors generates a trace data every time a predetermined event occurs; and A time input step of inputting an operation trace time at the time of occurrence of the event from the numeral means; and each of the plurality of processors creates trace information by associating the trace data with the trace time. A trace information storing step of storing information in the main storage device. Operation time synchronization method for a multiprocessor system. 5. The clocking step includes: storing a conversion ratio between a clock cycle and a clocking cycle of the clocking step in a conversion ratio storage unit; monitoring the clock; and generating an interrupt every clock cycle. A clock monitoring step of causing the counter to increment by one each time the interrupt occurs, and a count step of resetting the count of the counter when the count reaches the conversion ratio; and 5. The operation trace time synchronizing method for a multiprocessor system according to claim 4, further comprising: an adding step of adding one to the number set by the number setting means each time the number is reset. 6. In the trace information storing step, when existing trace information exists in the main storage device, the trace information and the existing trace information are stored in the main storage device.
6. The operation trace time synchronization method according to claim 4, wherein the operation trace times are arranged in the order of the operation trace times.