JPH01289377A - Vertical driving pulse generating circuit - Google Patents

Abstract

PURPOSE:To generate a vertical driving pulse in accordance with a different broadcasting system without receiving an influence with an external noise by providing the gate period inherent to the vertical synchronizing signal of first and second broadcasting systems. CONSTITUTION:A broadcasting system discriminating circuit 15 to discriminate whether a vertical synchronizing signal to come is a first broadcasting system or a second broadcasting system is provided and a gate signal selecting circuit 17 to impress the first and second frequency-dividing output signals of a vertical counting-down circuit 10 as a control signal in accordance with the discriminating output of the broadcasting system discriminating circuit 15 to a gate circuit 9. Thus, the gate circuit is provided respectively inherently to the vertical synchronizing signal of the first and second broadcasting systems. Thus, the influence of a noise to mix into the signal of respective broadcasting systems can be reduced to the minimum limit.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a vertical drive pulse generation circuit for a TV (television) receiver. relates to a vertical drive pulse generation circuit with improved noise resistance.

(b) Conventional technology An automatic television broadcasting system that has a function of opening a gate (window) and allowing the vertical synchronization signals of two different broadcasting systems (for example, NTSC and PAL systems) to pass through during the expected arrival period. The discrimination device was published in Japanese Patent Application Laid-Open No. 59-193.
It is described in Publication No. 679. FIG. 9 is a circuit diagram showing the gate circuit part of the automatic discrimination device for the television broadcasting system, in which a counter (
2), a gate circuit (4) that allows the vertical synchronization signal from the input terminal (3) to pass in response to the gate control signal from the counter (2), and and a pulse generating circuit (5) that generates a reset pulse that resets the counter (2).

After the counter (2) is reset, it counts the horizontal synchronization signal from the terminal (1), and the gate circuit (4) is cut off until the period when the vertical synchronization signal is expected to arrive. This prevents noise from the input terminal (3) from affecting the subsequent circuit.

Then, the count value of the counter (2>) is NTSC system and P
When the expected arrival count of the AL type vertical synchronizing signal reaches n-240, a gate control signal is generated to make the gate circuit (4> conductive).

In this state, if a regular vertical synchronization signal has arrived, n=262.5 is the NTSC system, or n=31
At 2.5, the vertical synchronizing signal of the PAL system passes through the gate circuit (4) and is applied to the pulse generating circuit (5), and the output terminal of the pulse generating circuit (5) receives a reset pulse according to the vertical synchronizing signal. occurs and resets the counter (2).

Then, in response to the reset, a vertical drive pulse is generated at the output terminal (6) of the counter (2) and is supplied to a deflection circuit (not shown). After the counter (2) is reset, it counts again and repeats the same operation as described above.

Note that when no vertical synchronization signal is applied to the input terminal (3), a pulse is generated from the counter (2) at n=340, and the pulse is generated from the counter (2) via the pulse generation circuit (5).
2) can be applied. Therefore, in this state, the counter (2) is in a self-resetting state of 7! I (a state in which the TV screen is flowing vertically).

Therefore, according to the circuit shown in FIG. 9, by providing a gate that allows the vertical synchronization signal to pass only during a specific period, it is possible to prevent malfunctions of the downstream circuit due to noise contained in the video signal.

(c) Problems to be solved by the invention By the way, the gate circuit (4) in FIG.
Since it can be used in both the PAL and PAL formats, the start of the gate period is set to n=240. n-240 is because the vertical synchronization signal of the NTSC system normally arrives at n=262.5. However, P.A.
When receiving an L-type vertical synchronization signal, the arrival of the vertical synchronization signal is usually n=312.5, so if the gate circuit (4) is opened from n-240, noise resistance will deteriorate. There was a problem. In other words, if noise is mixed into the PAL signal and the noise is present at a position earlier than the generation timing of the vertical synchronization signal, the noise will pass through the gate circuit (4) and cause the counter (2) to malfunction. There was a problem with it getting too crowded.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and is a gate circuit that allows vertical synchronization signals of the first and second broadcasting systems to pass from an input terminal in accordance with a control signal. is reset in response to the vertical synchronization signal from the gate circuit, and counts signals with a frequency that is an integral multiple of the horizontal synchronization signal frequency, and calculates a first broadcast signal corresponding to a period in which the arrival of the vertical synchronization signal of the first broadcasting method can be expected. A vertical countdown circuit that generates a frequency-divided output signal and a second frequency-divided output signal corresponding to a period during which the vertical synchronization signal of the second broadcasting method is expected to arrive, and a vertical countdown circuit that generates a frequency-divided output signal of the second broadcasting method, a broadcasting method discriminating circuit for discriminating whether the broadcasting method is a broadcasting method or a second broadcasting method, and the first and second frequency-divided output signals of the vertical countdown circuit are used as control signals in accordance with the discrimination output of the broadcasting method discriminating circuit. and a gate signal selection circuit that applies the signal to the gate circuit.

(f) Function According to the present invention, gate periods are provided for the vertical synchronization signals of the first and second broadcasting systems, so that the influence of noise mixed into the signal of each broadcasting system is minimized. It can be lowered.

Furthermore, according to the present invention, the gate periods of the first and second broadcasting systems are partially overlapped, so that when vertical synchronization signals arrive alternately before and after the determination limit point of the broadcasting system, It can also be determined that the broadcasting method is one of the two. Therefore, it is possible to prevent the vertical countdown circuit from going into a self-resetting state, and it is possible to maintain a stable synchronized state.

Further, according to the present invention, it is possible to detect that the vertical countdown circuit is in a self-resetting state, and to provide a wide gate corresponding to both the first and second broadcasting systems according to the detected output. Therefore, in this case, the synchronous pull-in speed can be increased.

(f) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which (7) is an input terminal to which NTSC and PAL video signals are applied, and (8) is the input terminal (7). ), (9) is a gate circuit that passes the vertical synchronization signal from the synchronization separation circuit (8) according to a control signal, and (10) is a clock terminal. (
(12) is a vertical countdown circuit that counts the clock signal of frequency 2f, I (f14 is the horizontal synchronization signal frequency) from 11) and generates the first to eighth output signals (≠, to φ,); An input selection circuit (13) selectively outputs the vertical synchronization signal from the gate circuit (9) and the first and second output signals φ and φ8 from the vertical countdown circuit (10) according to a control signal; Selection circuit (1
A reset pulse generation circuit (14) generates a reset pulse of a predetermined pulse width in response to the output signal of (2), after the vertical countdown circuit (10) is reset in response to the reset pulse, 8H (H is (15) operates in accordance with the third output signal φ from the vertical countdown circuit (10). 50/, which starts and compares the phase of the reset pulse with the fourth output signal 44 from the vertical countdown circuit (10) to determine whether the incoming vertical synchronization signal is 50 Hz or 60 Hz; 60 discrimination circuit,
(16) is the first signal from the vertical countdown circuit (10).
5th output signals 41 to 41 to 41 to 41 to 41 to 41 to 41 to 41 to 41 to 41 to 41 to 41 to 41 to 41 to 41 to 41 to 41 to 41 to 41 to 30 are to determine whether or not the vertical countdown circuit (10) is out of synchronization in accordance with the reset pulse from the reset pulse generation circuit (13) and the discrimination output from the 50760 discrimination circuit (15). and (17) detects the sixth and seventh output signals ≠ and φ from the vertical countdown circuit (10) according to the discrimination output of the 50/60 discrimination circuit (15). A first switch (18) that switches and outputs an eighth output signal from the vertical countdown circuit (10) and an output signal of the first switch (18) according to the detection output of the out-of-synchronization detection circuit (16). and a second switch (19) for switching output.
) is applied to the gate circuit (9) as a control signal.

The vertical countdown circuit (10) has 10 stages of T-
It consists of an FF (T-type flip-flop circuit) and a decoder circuit, and the frequency of the 2rH clock signal applied from the clock terminal (11) is divided by the T-FF, and the divided output is decoded and output. be. And the first
The output signal φ1 is a signal generated at 296H of one vertical period after the vertical countdown circuit (10) starts counting, the second output signal ≠ is a signal generated at 356H, and the third output signal φ is generated at 224H. a fourth output signal φ,
is the signal generated at 288H, the fifth output signal≠, is 1°5
The signal generated at H, the sixth output signal φ, is 2 from 224H.
The signal generated during 96H, the seventh output signal φ, is 268H.
The eighth output signal φ8, which is a signal generated between 356H and 356H, is 2
This is a signal generated between 24H and 356H.

Now, in the case of the NTSC system, the period of the vertical synchronization signal from the broadcasting station is 262.5H, and in the case of the PAL system, the period is 3H.
It is 12.5H. Therefore, in the present invention, the gate period of the NTSC system in the gate circuit (9) is set to be between 224H and 296H, and the gate period of the PAL system is set between 268H and 356H. Further, the timing (discrimination limit point) serving as a reference for discrimination between the NTSC system and the PAL system in the 50/60 discrimination circuit (15) is set to 288H.

Next, the operation will be explained. In the circuit shown in Fig. 1, when there is no signal, no video signal is applied to the input terminal (7), so the vertical countdown circuit (10) is not reset by an external signal, and the vertical countdown circuit (10) is not reset by an external signal;
The f'n clock signals are sequentially counted. When the count progresses to 356H, the second output signal φ is generated from the vertical countdown circuit (10), and the out-of-synchronization detection circuit (10) is generated.
6) is applied. Then, the out-of-synchronization detection circuit (16
) generates an output signal of "L" level indicating that the vertical countdown circuit (10) is out of synchronization,
The third switch (20) in the signal selection circuit (12) is switched to the contact a side, contrary to the illustration. Therefore, the second output signal φ from the vertical countdown circuit (10) is applied to the reset pulse generation circuit (13) via the first OR gate (21> and the third switch (20), A pulse is applied to the vertical countdown circuit (10). Said reset pulse is applied to the clock terminal (11).
), the pulse width is set to a short value (one period of the clock signal 2f'), so the vertical countdown circuit (10) starts counting immediately after being reset. resume. Then, the second output signal φ is generated from the vertical countdown circuit (10) again, and the same operation as described above is repeated. At this time, the vertical countdown circuit (10) performs a self-resetting operation because no signal is input from the outside. ing.

In this application, this state is referred to as an out-of-synchronization state,
Any other state is called a synchronous state.

Then, in response to the "L" level output signal of the out-of-synchronization detection circuit (16), the second switch (19) in the gate signal selection circuit (17) is switched to the contact side opposite to that shown in the figure.

Then, the eighth output signal φ from the vertical countdown circuit (10) is applied to the gate circuit (9) via the second switch (19). Therefore, the gate circuit (9
) has a wide gate period from 224H to 356H.

In this state, if an NTSC or PAL video signal is applied to the input terminal (7), the vertical synchronization signal in the video signal is separated by the synchronization separation circuit (8) and passes through the gate circuit (9). is applied to the input selection circuit (12). Here, the third switch (20) in the input selection circuit (12) receives the switching control signal from the out-of-synchronization detection circuit (16) regardless of the switching control signal from the 50/60 discrimination circuit (15). Since it is switched preferentially in response to this, a state opposite to that shown in the figure (contact a side) is maintained. For that reason,
The vertical synchronization signal from the gate circuit (9) passes through the first OR gate (21) and the third switch (20) and is applied to the reset pulse generation circuit (13). Then, a reset pulse corresponding to the vertical synchronization signal is transmitted from the reset pulse generation circuit (13) to the vertical countdown circuit (10).
, 50/60 discrimination circuit (15) and desynchronization detection circuit (16).

By the way, the 50760 discrimination circuit (15) is enabled to take in the reset pulse in response to the third output signal ≠ from the vertical countdown circuit (10), and compares the phases of the reset pulse and the fourth output signal φ. The out-of-synchronization detection circuit (16) is configured to generate a discrimination output after counting the phase comparison result output to a predetermined value (for example, 4 times) with a counter.
When an output signal of rH level indicating 60 Hz is applied from 5), the third output signal 4. In response to the arrival of the reset pulse, it becomes possible to take in the reset pulse from then on, and when the reset pulse is counted a predetermined number of times by the counter, an output signal of r HJ level indicating a synchronized state is generated. Further, when the reset pulse does not arrive, r indicates that the synchronization is out of synchronization in response to the arrival of the first output signal φ1.
Generates an output signal of L, level. Further, the out-of-synchronization detection circuit (16) includes a 50/60 discrimination circuit (15).
) to 50Hz, when the output signal of level "rL" indicating that the frequency is 50Hz is applied, in response to the arrival of the fourth output signal i4,
After that, it becomes possible to take in the reset pulse, and when the reset pulse is counted a predetermined number of times by the counter, an output signal of rH level indicating a synchronized state is generated.

Further, when the reset pulse does not arrive, the second output signal φ indicates that the synchronization is out of synchronization.
It is configured to generate an output signal of L level.

Here, assuming that a vertical synchronizing signal of the NTSC system is currently being received, a phase comparison is performed between the reset pulse corresponding to the vertical synchronizing signal and the fourth output signal φ4, but the phase of the reset pulse is different from the phase of the fourth output signal φ4. Since the phase is faster than that of the output signal φ, when the phase is compared a predetermined number of times, the 50/60 discrimination circuit (15) generates an output signal of level rH,
Switch the first switch (18) to contact a side. Further, in accordance with the rH level output signal of the 50/60 discrimination circuit (15), the out-of-synchronization detection circuit (16) takes in the third output signal φ, a reset pulse after application,
When a predetermined number of times is counted, an output signal of "H" level is generated and the second switch (19) is switched to the contact a side. Then, the sixth output signal φ is applied to the first and second switches (18) and (
19) to the gate circuit (9).

This situation is shown in FIG. 2, where the sixth output signal 4° is the second
The clock pulse shown in Figure (A) is shown as in Figure 2 (B). When a vertical synchronizing signal of negative polarity as shown in FIG. 2 (c) arrives, an output signal as shown in FIG. ) and is applied to the reset pulse generating circuit (13), and the reset pulse shown in the second diagram *) is generated at its output terminal. Then, since the vertical countdown circuit (10) is reset in response to the reset pulse,
The sixth output signal φ in FIG. 2(b) attains the "L" level at time t.

In addition, the output terminal (14) of the vertical countdown circuit (10)
), a vertical drive pulse of a constant width (8,5H) as shown in FIG. 2(f) is generated in response to the rise of the reset pulse.

Therefore, according to the circuit shown in FIG. 1, when receiving an NTSC vertical synchronization signal, a unique gate period (224
296H), it is possible to obtain a vertical drive pulse synchronized with the vertical synchronization signal.

Next, assuming that a PAL vertical synchronization signal is being received, the phase of the reset pulse applied to the 50/60 discrimination circuit (15) is slower than the phase of the fourth output signal φ, so the 50/60 The discrimination circuit (15) generates an "L" level output signal and switches the first switch (18) to the contact side. Further, in response to the "L" level output signal of the 50/60 discrimination circuit (15), the out-of-synchronization detection circuit (16) takes in the reset pulse after the application of the fourth output signal φ4, and after counting a predetermined number of times. , r H, generates an output signal of level. Therefore, the seventh output signal≠ is now applied to the gate circuit (9) via the first switch (18) and the second switch (19).

This situation is shown in FIG. 3, where the seventh output signal φ.

The difference between the clock pulse shown in Fig. 3(A) and the clock pulse shown in Fig. 3(A) is
B) is shown as follows. When a negative polarity vertical synchronizing signal as shown in FIG. 3(A) arrives, an output signal as shown in FIG. 3(d) is generated at the output terminal of the gate circuit (9), and the input selection circuit (12) is further output. It passes through and is applied to the reset pulse generation circuit (13), and the reset pulse shown in FIG. 3 (main) is generated at its output terminal. Then, the vertical countdown circuit (10) is reset according to the set pulse, so that
The seventh output signal≠7 in FIG. 3(b) becomes rL'' level at time 1+. Further, at the output terminal (14) of the vertical countdown circuit (10), a vertical drive pulse of a constant width (8, 5H) as shown in FIG.

Therefore, according to the circuit shown in FIG. 1, when receiving a PAL vertical synchronization signal, a unique game
6H) to obtain a vertical drive pulse synchronized with the vertical synchronization signal.

In other words, in the present invention, in the case of the NTSC system, the gate is set to a unique value such as <224H to 296H as shown in Fig. 4, and in the case of the PAL system, it is set to a unique value of 268H to 356H, thereby improving noise resistance. I can do it.

Next, from the state where PAL broadcasting is being received, to NTSC.
A case will be explained in which the switching is made to receive a broadcast using the same system. In the case of the PAL system, the gate circuit (9) is the seventh
The output signal φ varies between 268H and 356H, but the vertical synchronization signal of the NTSC system is 262.5H.
The signal cannot pass through the gate circuit (9). Therefore, the reset pulse generation circuit (13) does not generate a reset pulse, the vertical countdown circuit (10) continues counting without being reset, and the count reaches 356.
When the signal reaches H, the second output signal φ is applied to the OR gate (21), resulting in a self-resetting state. On the other hand, since no reset pulse is applied to the out-of-synchronization detection circuit (16) even after the arrival of the fourth output signal φ, an "L" level output signal indicating out-of-synchronization is generated in response to the arrival of the second output signal ≠. is generated, and the second switch (19) is switched to the contact side. Therefore, the eighth output signal φ is output from the second switch (
19) to the gate circuit (9>), and the gate period has a wide range as shown in FIG.
The structure is such that the second switch (19) is immediately switched in response to the arrival of the second switch (19). Note that the third switch (20) is switched to the a side. Then, the vertical synchronization signal of the NTSC system can pass through the gate circuit (9) in the second period, and the vertical countdown circuit (9) can pass through the gate circuit (9) in accordance with the vertical synchronization signal.
10) is reset. Therefore, a vertical drive pulse synchronized with the vertical synchronization signal can be immediately obtained at the output terminal (14).

If the out-of-synchronization detection circuit (16) did not exist, the 50/60 discrimination circuit (
15) is 50Hz (for example, 4
However, in the present invention, when even one occurrence of out-of-synchronization is detected, the gate period is immediately expanded, so synchronization can be quickly achieved.

In addition to the vertical synchronizing signal of television broadcasting, for example, a vertical synchronizing signal from a VTR may be applied to the input terminal (7) in FIG. The vertical synchronization signal from the VTR is used during special playback (
(double speed playback, still image playback), the cycle becomes unstable,
For example, there are cases where the signal exists while fluctuating around 288H, which is the limit point for distinguishing between the NTSC system and the PAL system (the positions of points A and B in FIG. 4 are repeated every vertical period).

In such a case, if the gate period of the NTSC method is 224
H ~ 288H, PAL method gate period is 288H ~ 3
If it is set to 56H, there is a problem that vertical synchronization will not be applied every vertical cycle1.For example, if the PAL system is initially determined, and the gate period is between 288H and 356H, Suppose that here,
If a vertical synchronization signal arrives before 288H, since that signal is outside the gate period, the vertical countdown circuit (10) will not be reset and will self-reset at 356H, causing the television screen to flash. ,
In the present invention, the gate period of the NTSC system and the gate period of the PAL system are determined at the discrimination limit point (28
They overlap around 8H). By doing so, the vertical countdown circuit (10) can maintain a synchronized state even in the case described above, and the television screen can be prevented from drifting.

Next, a specific circuit example of the circuit shown in FIG. 1 will be explained. Fifth
The figure is a circuit diagram showing a specific circuit example of the input selection circuit (12) and reset pulse generation circuit (13) of FIG.
-FF (R8 type flip-flop circuit) <22>, the OR gate (23) and the AND gate (24) represent the input selection circuit (12), and the D-FF (D type flip-flop circuit) (25) represents the reset Pulse generation circuit (1
3) is shown. Assuming that a regular vertical synchronization signal of the NTSC system and PAL system is now arriving, the vertical synchronization signal passes through the gate circuit (9) and passes through the R3-FF (2
2) and set its Q output to "H" level. And said rH.

The level signal passes through the OR gate (23) and the D-FF (
25) is applied to the D input. A clock signal is applied from the terminal (26) to the C input of the D-FF (25), and in response to the fall of the clock signal, its Q output becomes rH, level, and the next clock signal falls. In response to the drop, the Q output becomes "L" level. Therefore,
A reset pulse with a constant width is obtained at the output terminal (27). Note that, depending on the reset pulse, RS -FF (
22) is reset and returns to its state.

In addition, when the synchronization is out of synchronization, the out of synchronization detection circuit (16
) generates an output signal of r L J level, so the AND gate (24) is closed. Then, Ao Gate (2
3) has the Q output of R8-FF (22) and the terminal (28)
The second output signal φ, from the first
It is possible to prohibit the output signal φ from being captured.

Furthermore, when the NTSC vertical synchronization signal arrives,
When signal loss occurs once, 50/60 discrimination circuit (15)
is rH, level, and the out-of-synchronization detection circuit (16) is
Since each outputs the "H" level, the terminal (29)
A first output signal φ, from the gate is applied to the OR gate (23) via the AND gate (24). In addition, in the same case as described above in the PAL system, the 50/60 discrimination circuit (15)
Since an output signal of level L is generated, the AND gate (24) is closed and the second output signal φ from the terminal (28) is applied to the OR gate (23).

FIG. 6 is a circuit diagram showing a specific circuit example of the 50/60 discrimination circuit (15) of FIG. 1. Assuming that an NTSC vertical synchronization signal is being received now, the first R8-FF (31) is set in response to the third output signal i from the terminal (30), and its Q output becomes "HJ level". , the first AND gate (32) is opened.Therefore, the reset pulse from the reset pulse generation circuit (13) passes through the first AND gate (32>), which consists of T-FFs (33) and (34). The reset pulse is applied to the first counter (digital).When four reset pulses are counted, the second counter (digital) is applied.
The output of (36) becomes "H" level, and the second R8-F
Set F(37). Therefore, the output terminal (38) becomes rH level, and it is determined that the NTSC system is being received.

Also, assuming that a PAL vertical synchronization signal is being received, the reset pulse is not applied when the first R3-FF (31) is in the set state, so the first AND gate (
The output of 32) maintains the level r L , and the fourth
When the output signal φ4 is applied, the first R9-FF (31) is reset, its Q output becomes rH level, and the third AND gate (39) is opened. Therefore, the reset pulse passes through the third AND gate (39) and T-FF (4
0) and (41). Then, as in the previous case, the fourth AND gate (
The output of 41) becomes rH, level and the second R5-FF (
37) and inverts the output terminal (38) to "L" level.

FIG. 7 is a circuit diagram showing the out-of-synchronization detection circuit (16) of FIG. 1. If we are currently receiving an NTSC vertical synchronization signal, the output signal of the 50/60 discrimination circuit (15) will be at the "H" level, so the first and third antagonists) - (43) and ( 44) is open state, second and fourth
The AND gates (45) and (46) are closed, and in response to the third output signal from the terminal (47), the output of the first AND gate (43) becomes rH'' level and is passed through the OR gate (48). Applied to the first R8-FF (49). Then, the Q output of the first R3-FF (49) becomes rH,
level, and the reset pulse from the reset pulse generation circuit (13) is applied to the quaternary counter (婬〉) consisting of T-FF (50) and (51〉).Then, when four reset pulses are counted, The output of the AND gate (53) becomes the HJ level, and the second R8-FF (54) is set, and its Q output is set to the rHJ level.
Since the third AND gate (44) of R8-FF (49) is open, the fourth output signal≠4 or the fifth output signal φ
, will be reset accordingly. Therefore, the AND gate (5
5) is between 224H and 288H, or between 224H and 1.
A reset pulse can be passed for 5H.

If the vertical synchronization signal is lost in this state, the first output signal from the ~ terminal (56) will be output from the AND gate (57).
is applied to Since the other two inputs of the AND gate (57) are both at the rH level, the first output signal i
, passes through the OR gate (58) and resets the quaternary counter (婬) and the second R8-FF (54). Therefore, the Q output of the second R3-FF (54) is immediately reversed and “L”
” level.

Next, if a PAL vertical synchronization signal is being received, the output of the 50760 discrimination circuit (15) will be at the "L" level, so the first and third AND gates (43) and (44
) is in the closed state, and the second and fourth AND gates (45
) and (46) are in the open state. Therefore, the terminal (59
) in response to the fourth output signal -4 from the first R3-FF (4
9) is completely set, and its Q output becomes rH level. Therefore, the reset pulse passes through the AND gate (55), and as described above (7) JI's 2nd RS
-FF (54) Q output signal rH level.

Note that the first R3-FF (49) is the third AND gate (44
) is in an open state, it is reset in response to the second output signal φ or the fifth output signal φ. Therefore, the AND gate (55) is between 288H and 356H, or 288H.
It is possible to pass the reset pulse from H to 1.5H.

In this state, if the vertical synchronization signal is missing, the second output signal φ from the terminal (60) will be changed to the OR gate (58
) through the quaternary counter (ascending) and the second R8-FF (
54) to reset each of them. Therefore, the Q output of the second R8-FF (54) is immediately inverted to the rL level. In addition, 50/60 for ANDGATE (57)
Since the "L" level output signal of the discrimination circuit (15) is applied, its output is "L" level.

FIG. 8 is a circuit diagram showing the gate signal selection circuit (17) of FIG. 1. Now, the 50/60 discrimination circuit 15) is l''
Assuming that the out-of-sync detection circuit (16) is generating an output signal of rH'' level, the sixth output signal i from the terminal (61) is connected to the AND gate (62), the NOR gate (63) and It passes through the AND gate (64) and is applied to the gate circuit (9). In addition, a 50/60 discrimination circuit (1
5) is at "L" level, and the out-of-synchronization detection circuit (16) is at "L" level.
Assuming that an output signal of "H" level is being generated, the terminal (
The seventh output signal φ from the AND gate (66)
, passes through the NOR gate (63) and the AND gate (64) and is applied to the gate circuit (9). Further, when the out-of-synchronization detection circuit (16>) goes to the "L" level, only the eighth output signal φ1 from the terminal (67) is applied to the gate circuit (9).

In the explanation of FIG. 1, the case of the NTSC system and the PAL system was explained, but the present invention is not limited to this, and can be applied to broadcast systems with different vertical periods (for example, the NTSC system and the SECAM system). It can be applied to anything.

(G) Effects of the Invention As described above, according to the present invention, it is possible to provide a unique gate period for the vertical synchronization signals of the first and second broadcasting systems with different vertical periods, so that they are not affected by external noise. It is possible to generate vertical drive pulses according to different broadcasting systems.

Further, according to the present invention, the two gate periods are made to overlap near the discrimination limit points of the first and second broadcasting systems. Therefore, even a vertical synchronization signal that arrives near the discrimination limit point can be captured without expanding the gate period, and stable vertical synchronization can be achieved.

Furthermore, according to the present invention, when the out-of-synchronization detection circuit detects out-of-synchronization, it switches to a wide gate period that allows both the first and second vertical synchronizers to pass through, so that the transition from self-resetting to synchronization pull-in is possible. The time can be significantly reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams for explaining FIG. 1, and FIG. 4 is a characteristic diagram for explaining FIG. 1. Figure, Figure 5, Figure 6, Figure 7
8 and 8 are circuit diagrams showing a specific example of the circuit shown in FIG. 1, and FIG. 9 is a circuit diagram showing a gate circuit portion of a conventional automatic discrimination device for television broadcasting system. (7)...Input terminal, (8)...Synchronization W! circuit, (9)...gate circuit, (10)...vertical run)/down circuit, (11)...clock terminal,
(12)...Input selection circuit, (13)...Reset pulse generation circuit, (14)...Output terminal, (1
5)...50/60 discrimination circuit, (16)...out-of-synchronization detection circuit, (17)...gate signal selection circuit.

Claims (4)

[Claims] (1) A gate circuit that passes the vertical synchronization signals of the first and second broadcasting systems from the input terminal according to the control signal, and a gate circuit that is reset according to the vertical synchronization signal from the gate circuit and adjusts the frequency of the horizontal synchronization signal. Counts signals with frequencies that are integral multiples, and generates a first frequency-divided output signal corresponding to a period during which the vertical synchronization signal of the first broadcasting system is expected to arrive, and at the same time predicting the arrival of the vertical synchronization signal of the second broadcasting system. a vertical countdown circuit that generates a second frequency-divided output signal corresponding to a period in which the vertical synchronization signal is applied; a gate signal selection circuit that applies the first and second frequency-divided output signals of the vertical countdown circuit as control signals to the gate circuit in accordance with the discrimination output of the broadcasting scheme discriminating circuit; A vertical drive pulse generation circuit characterized in that a unique gate period is provided for each vertical synchronization signal. (2) The vertical drive pulse generation circuit according to claim 1, wherein the gate period of the first frequency-divided output signal and the gate period of the second frequency-divided output signal are made to overlap. (3) The broadcast system discrimination circuit performs a phase comparison between the signal corresponding to the vertical synchronization signal from the gate circuit and the third frequency-divided output signal from the vertical countdown circuit, which serves as a criterion for determining the first and second broadcast systems. 2. The vertical drive pulse generation circuit according to claim 1, comprising a comparison circuit. (4) A gate circuit that passes the vertical synchronization signals of the first and second broadcasting systems from the input terminal according to the control signal, and a gate circuit that is reset according to the vertical synchronization signal from the gate circuit and adjusts the frequency of the horizontal synchronization signal. a vertical countdown circuit that counts signals of integral multiple frequencies and generates a fourth frequency-divided output signal corresponding to a period during which vertical synchronization signals of the first and second broadcasting systems are expected to arrive; an out-of-synchronization detection circuit that detects that it is not reset in response to the vertical synchronization signal from the gate circuit and is in a self-resetting state; A vertical drive pulse generation circuit comprising a window selection circuit that applies a frequency-divided output signal as a control signal to the gate circuit.