JPH0514831A - Field frequency discrimination circuit - Google Patents

Abstract

PURPOSE:To drastically reduce the possibility of the erroneous discrimination of the temporary discrimination of field frequency. CONSTITUTION:A vertical counter 3 counts the n (integer)-fold pulses of horizontal frequency, and is reset synchronously with a vertical synchronizing signal. A window pulse generation circuit 5' generates a narrow and a wide width window pulse W50n, W50w/W60n, W60w respectively at a timing corresponding to the vertical synchronizing signal of a television signal having the field frequency of 50 or 60Hz by using the output of the counter 3. A switching circuit 11 selects one pair of every one window pulse corresponding to 50 or 60Hz among the window pulses W50n, W50w/W60n, W60w, and these pulses and a vertical sampling pulse Vp1 are compared with each other by comparators 6a, 6b, and a result is held by a holding circuit 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field frequency discriminating circuit suitable for application to, for example, a television receiver capable of receiving multi-system broadcasting, a monitor receiver of a VTR or the like.

[0002]

As is well known, the PAL system and SECAM
System with color subcarrier frequency of 4.43 or 3.5
A VTR capable of recording and reproducing a multi-system television signal such as an 8 MHz NTSC system has been developed. In the monitor receiver used for such a VTR, a field frequency discriminating circuit for discriminating a difference in field frequency between television signals of each system is provided, and the receiving mode is switched based on the discriminated output.

FIG. 4 shows a conventional field frequency discriminating circuit. The input television signal has a field frequency of 50 Hz, "50/625 system" with 625 scanning lines per frame, 60 Hz field frequency, "60/525 system with 525 scanning lines per frame" Two types are to be supplied.

The terminal 1 has a frequency n which is an integral multiple of the horizontal frequency.
A reference clock having fH is input and supplied to the vertical counter 3. A vertical sync signal VSync obtained by a vertical sync separation circuit (not shown) is input to the terminal 2 and supplied to the vertical sampling circuit 4. The vertical sampling circuit 4 resets the vertical sampling output Vp1 serving as a reference for field frequency discrimination and the vertical counter 3 in synchronization with the vertical synchronizing signal, and has a pulse width rising from the trailing edge of the vertical sampling output Vp1 shown in FIG. A reset pulse Vp2 having the above is generated from the vertical synchronizing signal. The vertical counter 3 constitutes a counter that counts nfH in synchronization with the vertical synchronization signal, and decodes the output of the counter to nfH.
A decode pulse having an arbitrary phase and width with H accuracy can be obtained. In the window pulse generation circuit 5, two types of phase comparison window pulses W50 (for 50 Hz) having the phases and widths as shown in FIGS. 5 (a) and 5 (b) are used as decode pulses.
, W60 (for 60Hz) is output. W50 and W60 respectively perform phase comparison with the vertical sampling output Vp1 in the phase comparison circuits 6a and 6b an arbitrary number of times, and supply the phase coincidence output to the holding circuit 7 from the output of the comparison circuit in which the phases coincide with the arbitrary number of times. When the holding circuit 7 inputs one of the phase-matched outputs, it holds the previous state until the other phase-matched output is input even in the non-input state, so that the field frequency discrimination output output from the terminal 8 can be stably obtained. I am configuring.

Here, the pulse widths of the window pulses W50 and W60 generated by the window pulse generation circuit 5 are:
It is often determined by the vertical sync signal pull-in range of the television receiver and the monitor receiver. That is, when a vertical synchronizing signal is input within the pull-in range, a wide pulse width is required to cover the entire pull-in range so that the mode of the system can be determined without fail. In W50 and W60 in FIG. 5, the range A to B must correspond to the pull-in range.

[0006]

However, the fact that the pulse width of the phase comparison window pulse is wide means that noise can be easily picked up. When the reception state is not stable, temporary misjudgment is likely to occur, and the screen may be danced, resulting in an unsightly screen. As a solution to the erroneous discrimination, it is conceivable to increase the number of phase comparisons between the window pulse and the vertical sampling output or narrow the pulse width of the window pulse, but in the former case, the time required for discriminating the field frequency is increased. In the latter case, the field frequency cannot be discriminated even within the pull-in range of the vertical synchronizing signal, or the pull-in range must be narrowed in order to avoid this, and both are preferable as the field frequency discriminating circuit. Absent.

The present invention provides a field frequency discriminating circuit capable of greatly reducing the possibility of erroneous discrimination without increasing the time required for discrimination and narrowing the pull-in range of the vertical synchronizing signal. The purpose is to provide.

[0008]

The present invention is based on a vertical counter that counts pulse signals having a frequency that is an integral multiple of a horizontal cycle signal and is reset in synchronization with a vertical synchronizing signal, and an output of the vertical counter. At least two window pulses having a constant pulse width are generated at the timing corresponding to the vertical synchronizing signal of the television signal having the first field frequency.
First window pulse generating means for generating a window pulse group having different pulse widths, and a constant pulse at a timing corresponding to a vertical synchronizing signal of a television signal having a second field frequency based on the output of the vertical counter. A second window pulse generating means for generating at least two window pulse groups having different pulse widths, and one of the first and second window pulse generating means from the window pulse group. Switch means for selecting one set each for each pulse, and means for comparing the phase of the window pulse selected by the switch means with the phase of the vertical synchronizing signal an arbitrary number of times.

[0009]

By the above means, the pulse width of the phase comparison window pulse can be switched according to the reception state, and a stable and quick discrimination output can be obtained even under a weak electric field or when switching channels.

[0010]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows an embodiment in which the present invention is applied to a field frequency discrimination circuit for television signals of "50/625 system" and "60/525 system".
The same parts as those in FIG. 4 are designated by the same reference numerals.

At the terminal 1, the output of an oscillator (not shown) which oscillates at a frequency that is an integral multiple of the horizontal frequency and is phase-controlled with the horizontal synchronizing signal or its frequency-divided output is used as the reference clock n.
It is input as fH and is supplied to the vertical counter 3. A vertical sync signal component VSync obtained by a vertical sync separation circuit (not shown) is input to the terminal 2 and supplied to the vertical sampling circuit 4. The vertical sampling circuit 4 resets the vertical sampling output Vp1 serving as a phase reference for field frequency discrimination shown in FIG. 2 and the reset pulse Vp2 having a pulse width for resetting the vertical counter 3 in synchronization with the vertical synchronizing signal component VSync. Generate more. As a result, the vertical counter 3 constitutes a counter that counts the reference clock nfH in synchronization with the vertical synchronizing signal, and decodes the output of the counter to obtain a decode pulse having an arbitrary phase and width with an accuracy of nfH.

In the window pulse generating circuit 5 ', as the decode pulse, a narrow pulse width W50n and a wide pulse width W50w for the "50/625" mode shown in FIG.
Vertical sampling output V such as W60n with narrow pulse width and W60w with wide pulse width for "60/525" mode
A narrow window pulse and a wide window pulse are generated and output at a phase where p1 is expected to arrive. However, the pulse width of the wide window pulse in each mode should not be less than the pull-in range of the vertical synchronizing signal, and the pull-in range in FIG.

Wide window pulse W50w obtained above
・ W60w is switched depending on the receiving condition of the input signal. Switching is performed by supplying a control signal to the switching circuit 11 based on the state detection circuit 9 and the switching logic 10.

FIG. 3 shows a state detection circuit 9 and a switching logic 10.
And a specific configuration example of the switching circuit 11,
This will be described below.

The state detection circuit 9 detects the state of the vertical synchronizing signal as follows, for example, and outputs the detection output to the switching logic 10 of the next stage. The narrow window pulses W50n and W60n obtained from the window pulse generation circuit 5'are ORed to the OR gate 12 and the wide window pulses W50w and W60w are ORed.
Supply to the gate 13 respectively. One output of the OR gate 12 is input to the AND gate 15 via the NOT gate 14 together with the output of the OR gate 13 and the vertical sampling output Vp1. The output of the AND gate 15 exists outside the narrow window pulse W50n or W60n and inside the wide window pulse W50w or W60w. The detection output VpOUT of the vertical sampling output Vp1.
Becomes On the other hand, the other output of the OR gate 12 is input to the AND gate 16 together with the vertical sampling output Vp1,
It becomes the detection output VpIN of the vertical sampling output Vp1 existing inside the narrow window pulse W50n or W60n.

The switching logic 10 conditions in which state the narrow or wide window pulse is selected, receives the state detection output obtained from the state detection circuit 9 in the preceding stage, and switches to the switching circuit 11 for switching. The control signal of is output. The detection outputs of this embodiment correspond to VpIN and VpOUT. The detection output VpIN is supplied as a reset pulse of a counter composed of two-stage toggle flip-flops (T-FF) 17 and 18, and the detection output VpOU is supplied.
T is supplied to the T terminal of the T-FF 17 as a counter clock pulse. Since both Q outputs of the T-FFs 17 and 18 are input to the AND gate 19 together with VpOUT, the gate 19 has Vp1 of W50n or W60n.
Vertical sampling output V under the condition that there existed four consecutive vertical periods outside W5w and inside W50w or W60w.
It outputs a pulse equivalent to p1. The RS-FF 20 obtains the output of the gate 19 as the set pulse and the output of the AND gate 16 as the reset pulse. A control signal for switching which is at "Lo" level is output unless is satisfied.

The switching circuit 11 includes a switching logic 1
When receiving the control signal for switching output from 0,
It is a means for actually switching which combination of the wide window pulse W50w / W60w and the narrow window pulse W50n / W60n is used as the phase comparison window pulse for field frequency discrimination. RS-FF2
The control signal for switching obtained with the Q output of 0 is AN
D gate 21 has W50w and AND gate 23 has W60
In addition to w, if "Hi" level, gate, "L"
If it is o "level, it operates so as to mask. Since the output of the AND gate 21 and W50n are input to the OR gate 22, and W50w has a phase relationship including W50n, the output of the OR gate 22 is If the control signal for switching is "Hi" level, W50w is output, and if it is "Lo" level, W50n is output, and the control signal for switching is also input to the OR gate 24 by inputting the output of the AND gate 23 and W60n. If is "Hi" level, W60w is output, and if "Lo" level, W60n is output.

As described above, the state detection circuit 9, the switching logic 10 and the switching circuit 11 allow the window pulse W50 having a narrow width depending on the state of the input television signal.
n, W60n and wide window pulse W50w, W60w
Which combination is used as the phase comparison window pulse for field frequency discrimination is selected. The selected window pulse for discriminating each field frequency is supplied to each of the phase comparators 6a and 6b, and thereafter, the field frequency can be discriminated automatically by performing the same processing as in the conventional technique.

When a generally-received "50/625 system" or "60/525 system" television signal is used as input, the vertical sampling output must always include the phase included in the narrow window pulse. Have a relationship. In such a case, a narrow pulse is selected as the phase comparison window pulse for field frequency discrimination, so when there is a lot of noise due to a weak electric field or channel switching, or when the phase of the vertical synchronization signal is not stable. Even if the vertical sampling output occurs other than the normal phase, the possibility that the field frequency is erroneously determined by operating to mask the vertical sampling output is extremely low. Further, since the number of comparisons of the subsequent phase comparison circuit is not manipulated, the time required for field discrimination does not increase.

On the other hand, for example, when a television signal other than the above-mentioned method, which has an irregular sync signal in which the number of scanning lines per field is different from usual (provided that it is within the pull-in range of vertical sync), is input, The vertical sampling output is in phase corresponding to the outside of the narrow pulse and the inside of the wide pulse. In this case, the phase comparison window pulse for field frequency discrimination selects a wide pulse, so if the wide pulse and the pull-in range are the same, the field frequency cannot be discriminated even though it is in the pull-in range. Don't

The present invention is not limited to the above-described embodiment. For example, the state detection circuit 9, the switching logic 10 and the switching circuit 11 in FIG. 3 are for discriminating the field frequency according to the state of the input television signal. Any means can be used as long as it is for switching the phase comparison window pulse, and its specific configuration can be variously modified. For example, the state detection circuit 9 may include standard signal / non-standard signal discriminating means, and a narrow window pulse may be used for a standard signal and a wide pulse may be used for a non-standard signal. Since many standard signal / non-standard signal discriminating means have been proposed, a concrete circuit example will be omitted here.

[0022]

As described above, according to the present invention,
Realization of a very good circuit suitable for integrated circuits that can discriminate the field frequency without error even under a noisy condition such as a weak electric field or channel switching and when the phase of the vertical synchronizing signal is not stable. Can be achieved.

[Brief description of drawings]

FIG. 1 is a system circuit diagram of an embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining FIG.

FIG. 3 is a system circuit diagram more specifically showing a main part of FIG.

FIG. 4 is a conventional system diagram.

5 is a waveform diagram used to explain FIG. 4. FIG.

[Explanation of symbols]

3 ... Vertical counter 4 ... Vertical sampling circuit 5 '... Window pulse generation circuit 9 ... Status detection circuit 10 ... Switching logic 11 ... Switching circuit

Claims (2)

[Claims] 1. The television by supplying a vertical synchronizing signal and a horizontal synchronizing signal of either one of the television signals having first and second field frequencies having different field frequencies from each other. If the field frequency of the John signal is the first and second
In the field frequency discriminating circuit for discriminating which one of the field frequencies, a vertical counter for counting pulse signals having a frequency that is an integral multiple of the horizontal period signal and resetting in synchronization with the vertical synchronizing signal; A first pulse generating a window pulse group having a constant pulse width and generating at least two kinds of window pulse groups having different pulse widths at a timing corresponding to the vertical synchronizing signal of the television signal having the first field frequency using the output of the counter. A window pulse generating means and an output of the vertical counter are used to generate a window pulse having a constant pulse width at a timing corresponding to a vertical synchronizing signal of the television signal having the second field frequency, and at least two types of windows having different pulse widths. Second window pulse generator for generating a pulse group When, from among the window pulse groups, the first and second
1 of each of the window pulse generating means
A field frequency discriminating circuit comprising: switch means for selecting one set for each pulse, and means for comparing the phase of the window pulse selected by the switch means with the phase of the vertical synchronizing signal an arbitrary number of times. 2. The state detecting means for detecting that the vertical synchronizing signal of the television signal having the first and second field frequencies is in an arbitrary phase range for every vertical period, and the state. 2. The field frequency discriminating circuit according to claim 1, wherein the field frequency discriminating circuit is controlled by a switching means for adding an arbitrarily set specific condition to the output of the detecting means.