JPH0419747B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Industrial Application Field The present invention relates to a countdown-type vertical drive pulse generation circuit used in television receivers, etc., and particularly relates to a countdown type vertical drive pulse generation circuit used in television receivers, etc. The present invention relates to a vertical drive pulse generation circuit that can determine whether the pulse is correct or not and can generate a correct vertical drive pulse.

(b) Prior Art A countdown type vertical drive pulse generation circuit is described in Japanese Patent Publication No. 7786/1986. Figure 2 shows the circuit, in which a clock signal with twice the frequency of the horizontal synchronizing signal supplied to terminal 1 is divided into 1/525 by frequency divider 2, and is divided into a frequency with a predetermined pulse width. An output signal is generated at terminal 3.
Further, the composite synchronization signal inputted to the terminal 4 is synchronized and separated by the vertical synchronization separation circuit 5. The NAND gate 6 compares the phases of the output signal of the vertical synchronization separation circuit 5 and the frequency-divided output signal of the frequency divider 2, and resets the octal counter 7 when the phases match. When the octal counter 7 is reset, its output is
The reset signal selection circuit 8 is set to the side that receives the divided output signal of the frequency divider 2. Therefore, frequency divider 2
is accurate to 1/52 regardless of external vertical synchronization signal.
Performs frequency division by 5 operation. Furthermore, when the frequency-divided output signal of the frequency divider 2 and the vertical synchronizing signal are not synchronized, the octal counter 7 counts the vertical synchronizing signal without being reset by the NAND gate 6, and when it counts eight times, it counts the vertical synchronizing signal. The output of the advance counter 7 is used to set the reset signal selection circuit 8 to the side that receives the output signal of the vertical synchronization separation circuit 5. Therefore, the frequency divider 2 performs a frequency division operation according to the vertical synchronization signal.

Therefore, according to the circuit shown in FIG. 2, even when the frequency-divided output signal of the frequency divider 2 and the vertical synchronization signal are in an asynchronous state, the vertical synchronization signal is counted eight times by the octal counter 7, and the eighth vertical synchronization signal is counted eight times by the octal counter 7. Frequency divider 2 with synchronization signal
It is possible to synchronize the frequency-divided output signal and the vertical synchronization signal.

(C) Problems to be Solved by the Invention However, the circuit shown in Fig. 2 does not have a normal vertical period of 262.5H (H is one period of the horizontal synchronizing signal) from the broadcasting station at terminal 4, or a video tape recorder or the like. When a vertical synchronization signal from a personal computer or the like is applied, there is a problem that synchronization is disturbed. For example, when a vertical synchronization signal with a pulse width of 3H and a period of 262H is applied to terminal 4, the phase comparison by the NAND gate 6 determines that the phases match because the pulse width of the vertical synchronization signal is as long as 3H. . Then, octal counter 7 is reset, and according to its output, 262.5H is sent to frequency divider 2.
It starts to reset periodically, and the playback screen gradually shifts. Eventually, the phases of the signals applied to the NAND gate 6 no longer match, and when the octal counter 7 counts the vertical synchronization signal eight times, the frequency divider 2 comes to be reset in accordance with the vertical synchronization signal. Then, the NAND gate 6 again judges that the phases match. For this reason, the NAND gate 6 repeatedly judges whether or not the phases match, causing the problem that the playback screen moves up and down.

(d) Means for Solving the Problems The present invention has been made in view of the above points, and includes a vertical synchronization separation circuit that synchronously separates a composite synchronization signal to generate a vertical synchronization signal, and a horizontal synchronization signal. a vertical countdown circuit that receives a clock signal with N times the frequency and divides the frequency of the clock signal to generate a pseudo vertical synchronization signal; a selection circuit that switches and outputs the two vertical synchronization signals; and an output of the selection circuit. A reset pulse generation circuit that generates a reset pulse for the vertical countdown circuit in response to a signal, and a phase comparison between the divided output signal of the vertical countdown circuit and the reset pulse, and switches the selection circuit in accordance with the phase difference. It is characterized by having a phase comparison circuit.

(E) Effect According to the present invention, a phase comparator compares the reset pulse applied to the frequency dividing circuit according to the vertical synchronization separation output signal with the pulse of a predetermined period generated from within the frequency dividing circuit. , since the period of the vertical synchronization signal is determined, it is not affected by the pulse width of the vertical synchronization separation output.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention.
9 is a vertical synchronization separation circuit that synchronously separates the composite synchronization signal input to terminal 10 and extracts the vertical synchronization signal; 11 counts the clock of 2f _H (f _H is the frequency of the horizontal synchronization signal) applied to terminal 12; first
A vertical countdown circuit that generates the fifth output signals (φ ₁ to φ ₅ ); 13 is a vertical synchronization separation circuit 9;
14 is a reset pulse generation circuit that generates a reset pulse of a predetermined pulse width in accordance with the output signal of the input selection circuit ₁₃ ;
15 is a delay circuit that delays the second output signal φ ₂ ;
16 is a gate circuit that passes a vertical synchronization signal according to the fourth output signal φ ₄ ; 17 is the gate circuit 16;
A holding circuit 18 holds the output signal of the reset pulse generating circuit 14 and the delay circuit ₁₅ , or the output signal of the holding circuit 17 and the first output signal. ₁ , and a phase comparison circuit 19 that compares the phases of the two outputs of the signal selection circuit 18 and controls switching of the input selection circuit 13 and the signal selection circuit 18 based on the output signal. It is a circuit.

The vertical countdown circuit 11 has 10 stages of T-
It consists of an FF (FF: flip-flop circuit) and a decoder, and uses the 2f _H signal supplied from terminal 12 as a clock to divide the frequency by the 10 stages of T-FF, and decodes and outputs the divided output of each. The first output signal _φ1 is 4H after being reset.
The second output signal φ ₂ is a signal that becomes “H” level after 261.5H, the third output signal φ ₃ is a signal that becomes “H” level from 8H to 17H, The fourth output signal φ ₄ is a signal that is at the “H” level from 261H to 1.5H, and the fifth output signal φ ₅ is a signal that generates a vertical drive pulse at the “H” level at the output terminal 20 for 8H from reset. It is.

In the case of the NTSC system, the period of the vertical synchronization signal from the broadcasting station is 262.5H. On the other hand, the period of a vertical synchronizing signal from an external device other than the broadcasting station, such as a video tape recorder or a personal computer, fluctuates due to various causes. Therefore, in this specification, a signal including a vertical synchronization signal with a period of 262.5H is referred to as a television signal,
A signal that includes a vertical synchronization signal with a period other than the above is referred to as a video signal.

Next, the operation will be explained. For example, in the circuit shown in FIG. 1, if it is assumed that the phase comparison circuit 19 is generating an "L" level output signal, the input selection circuit 13 will perform vertical synchronization separation in response to a control signal from the phase comparison circuit 19. The vertical synchronizing signal of the circuit 9 is selectively output, and the signal selection circuit 18 is selectively outputting the signals of the delay circuit 15 and the reset pulse generating circuit 14. In this state, when the video signal is input from the terminal 10 to the vertical synchronization separation circuit 9, the synchronously separated vertical synchronization signal is applied to the reset pulse generation circuit 14 via the input selection circuit 13. Therefore, a reset pulse having a predetermined pulse width corresponding to the vertical synchronization signal is applied to the reset terminal of the vertical countdown circuit 11,
A vertical drive pulse corresponding to the reset pulse is generated at the output terminal 20. After the vertical countdown circuit 11 is reset, a second output signal φ ₂ is generated after a predetermined period of time has elapsed, and this signal is sent to the delay circuit 1.
5 to the signal selection circuit 18. Then, a reset pulse corresponding to the next vertical synchronization signal is also generated from the reset pulse generation circuit 14 and applied to the signal selection circuit 18. In that case, since the signal selection circuit 18 is switched as described above by the control signal from the phase comparison circuit 19, the two signals pass through as is.

Now, if the input signal applied to the terminal 10 is a video signal, the phases of the two signals do not match,
The output signal of the phase comparison circuit 19 remains unchanged at the "L" level.

Next, if the input signal applied to the terminal 10 is a television signal, the phases of both signals match, and the output signal of the phase comparison circuit 19 is inverted to the "H" level.
Therefore, the input selection circuit 13 outputs the second output signal φ ₂
The signal selection circuit 18 is switched to take in the holding circuit 17 and the first output signal φ ₁ .

As a result, the second output signal φ ₂ is applied to the reset pulse generation circuit 14, so that the vertical countdown circuit 11 performs a self-resetting operation, is not affected by an external vertical synchronization signal, and performs a constant cycle. A vertical drive pulse is generated at the output terminal 20.

By the way, the vertical synchronization signal from the vertical synchronization separation circuit 9 is applied to the gate circuit 16 to which the fourth output signal φ ₄ is applied as a control signal (so-called window signal).
It passes through and is applied to the holding circuit 17. The holding circuit 17 generates an "H" level signal when the vertical synchronizing signal is applied, and the "H" level signal is sent to the phase comparator circuit 19 via the signal selection circuit 18 together with the first output signal _φ1 . applied. At this time, since the vertical synchronization signal of the television signal has arrived from the vertical synchronization separation circuit 9, the phases of the two signals in the phase comparator circuit 9 match, and the output remains held.

In this state, when switching to an external device or another channel is performed, the synchronously separated vertical synchronizing signal and the fourth signal generated by the vertical countdown circuit 11
The phase relationship with the output signal φ ₄ is disturbed, and the vertical synchronizing signal cannot pass through the gate circuit 16. or,
When the electric field is weak, the vertical synchronization signal is lost. In this state, the output of the holding circuit 17 becomes "L" level in response to the third output signal φ ₃ , and the signal selection circuit 18 sends the "L" level signal and the first output signal φ ₁ to the phase circuit 19. Apply. At this time,
The phases of both signals in the phase comparator circuit 19 become inconsistent, and its output is inverted to the "L" level again. As a result, the vertical countdown circuit 11 is reset by the vertical synchronization signal arriving from the outside, and a vertical drive pulse synchronized with the reset signal is obtained at the output terminal 20.

Therefore, according to the circuit shown in FIG. 1, when a video signal has arrived, the vertical countdown circuit 11 is reset in accordance with the vertical synchronization signal in the video signal, and a corresponding vertical drive pulse is obtained. and when a television signal arrives, the vertical countdown circuit 1
1 is reset, and a corresponding vertical drive pulse can be obtained.

FIG. 3 is a circuit diagram showing a specific example of the circuit shown in FIG. 1, in which 21 is an input selection circuit, 22 is a D-FF representing a reset pulse generation circuit, 23 is a signal selection circuit, and 24 is a phase comparison circuit. There is.

In FIG. 3, S- of the phase comparator circuit 24
Assuming that the Q output of RFF 25 is at "L" level and the output is at "H" level, the output is applied to one end of AND gates 26, 27 and 28, and the Q output is applied to one end of AND gates 29, 3.
0 and 31. In this state, when the vertical synchronization signal shown in FIG.
Since the sixth output signal φ ₆ having a high level is applied, an “H” level signal is applied to the OR gate 33 at the rising timing of the vertical synchronizing signal. Since the seventh output signal from 296H to "H" level is applied to the OR gate 33,
An "H" level signal is applied to the D input of the D-FF 22 at the rising timing. D-
The C (clock) terminal of FF22 is shown in Figure 4 A.
Since the 2f _H signal is applied and the D-FF 22 performs a falling operation, the "H" level signal is transferred to the Q output at the falling timing of 261.5H. Therefore, the vertical countdown circuit 34 is reset in response to the Q output, the sixth output signal φ ₆ becomes "L" level, and the AND gate 28
and is applied to the D terminal of the D-FF 22 via the OR gate 33. Therefore, at the next falling edge of the _2fH clock, that is, at 262H, an "L" level signal is transferred to the Q output, so that a signal with a pulse width of 0.5H as shown in FIG. 4C is generated as a reset pulse. The reset signal is applied to the NAND gate 35 along with the 2f _H clock pulse shown in FIG. 4A, and a pulse as shown in FIG. applied.

On the other hand, from the vertical countdown circuit 34
The second output signal φ ₂ as shown in FIG. 4H rising at 261.5H is applied to the D terminal of the D-FF38, and is delayed by 0.5H by the 2f _H clock pulse, so that the pulse width as shown in FIG. 4H is 0.5H. Signal is AND gate 2
D of D-FF37 via 6 and OR gate 39
Applied to the terminal. Therefore, C of D-FF37
At the falling timing of the signal shown in FIG. 4D applied to the terminal, the "L" level signal shown in FIG. 4 applied to the D terminal is transferred to the Q output. Therefore, the Q output of D-FF37 is at "L" level,
The Q output becomes "H" level, and the third output signal φ ₃
is applied to the octal counter 41 via the AND gate 40, and when counted eight times, the octal counter 41 resets the S-RFF 25 and the hexadecimal counter 42. Therefore, the Q output of the S-RFF 25 maintains the "L" level and the Q output maintains the "H" level. As a result, the vertical countdown circuit 34
generates a vertical drive pulse at the output terminal 43 in response to the vertical synchronization signal of the video signal.

Next, when the vertical synchronization signal of the television signal whose rising edge is between 261.5H and 262H as shown in FIG. 5B comes from the vertical synchronization separation circuit 32, the vertical synchronization signal is D via AND gate 28 and OR gate 33
- Applied to the D terminal of FF22. For this reason, D-
At the fall of 262H of the clock signal shown in FIG. It will look like Figure C. Therefore, a signal as shown in FIG.
It is applied to the C terminal of 37.

On the other hand, as in the case described above, the second
The output signal φ ₂ is applied to the D terminal of D-FF38,
The Q output becomes as shown in FIG. 5 and is applied to the D terminal of the D-FF 37 via the AND gate 26 and the OR gate 39. Therefore, at the falling timing of the signal shown in Figure 5 D applied to the C terminal of the D-FF37, the "H" level signal shown in Figure 5 applied to the D terminal is transferred to the Q output. Ru. Therefore, the Q output of the D-FF 37 becomes "H" level and the output becomes "L" level, and the third output signal φ ₃ is applied to the hexadecimal counter 42 via the AND gate 44 and counted 16 times. , hexadecimal counter 42 sets S-RFF 25 and resets octal counter 41. Therefore, S-RFF
The Q output of 25 becomes "H" level, the output becomes "L" level, and their states are reversed. As a result, the second output signal φ ₂ is applied to the D terminal of the D-FF 22 via the AND gate 31 and the OR gate 33, and the S-
The Q output of the RFF 45 is applied via the AND gate 29, and the first output signal φ ₁ is applied to the NOR gate 36.
is now applied through the AND gate 30. Since the second output signal φ ₂ is applied to the D terminal of the D-FF 22, the vertical countdown circuit 34
A vertical drive pulse with a period of 262.5H is generated at the output terminal 43.

On the other hand, in this state, the rise from the vertical synchronization separation circuit 32 is from 261.5H to 262H as shown in Figure 6B.
When a vertical synchronizing signal slightly shifted from the
It is gated by the output signal φ ₄ and applied to the set input S of S-RFF 45. Therefore, S-
The Q output of the RFF 45 is as shown in FIG.
Applied to the D input of FF37. Further, the vertical countdown circuit 34 is reset by a reset pulse corresponding to the second output signal φ ₂ as shown in FIG. 6E, and the first output signal φ ₁ as shown in FIG. 6 is applied to the C terminal of the D-FF 37. , at the falling edge of the first output signal _φ1, that is, at the timing of 4H, the Q output is set to the "H" level. Since the Q output has already reached the "H" level in the above-described operation, its state does not change, and the S-RFF 25 continues to receive the television signal. Furthermore, S-
The RFF 45 is reset at 8H by the third output signal _φ3 .

In this state, switching to an external device or another channel is performed, and a vertical synchronization signal with a long period and out of phase as shown in FIG.
, the vertical synchronizing signal cannot pass through the AND gate 46, and the Q output of the S-RFF 45 becomes "L" level. For this reason, D-FF37's D
Since the terminal is always at the "L" level and the first output signal φ ₁ is applied to the C terminal, an "L" level signal is generated at the Q output at the fall of 4H. Therefore, the third output signal φ ₃ is applied to the octal counter 41 via the AND gate 40,
When counted eight times, the S-RFF 25 and hexadecimal counter 42 are reset. Therefore, S-RFF
25 has a Q output of "L" level and an output of "H" level so as to take in a vertical synchronizing signal from the outside again.

The hexadecimal counter 42 and the octal counter 41 count the third output signal φ ₃ from the AND gates 44 and 40 16 times and 8 times, respectively, and then generate an output signal with a predetermined pulse width. Performing a counting operation. In addition, when the output of the S-RFF 25 selects the vertical synchronization signal that arrives at the "H" level, the seventh output signal φ ₇ controls the vertical countdown circuit 34 at a cycle of 297H when the vertical synchronization signal does not arrive. This is a signal for resetting.

(G) Effects of the Invention As described above, according to the present invention, in order to discriminate between a television signal and a video signal, phase comparison is performed between the reset pulse of the vertical countdown circuit and the frequency-divided output of the vertical countdown circuit. Therefore, the vertical drive pulse can be stably obtained without being affected by the pulse width of the incoming vertical synchronization signal, and there is no problem that the playback screen will flow even when receiving signals from external equipment.

Also, as in the embodiment, after determining that a television signal is being received by phase comparison, the vertical countdown circuit is set to self-reset operation, and a window is opened for vertical synchronization signals arriving from the outside. Since it is determined whether or not the vertical synchronization signal exists within the window, the sensitivity of the determination can be changed.
Abnormal switching can be prevented.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional synchronizing device, FIG. 3 is a circuit diagram showing a specific example of the circuit shown in FIG. 5 and 6 are waveform charts for explaining FIG. 3, respectively. 9... Vertical synchronization separation circuit, 11... Vertical countdown circuit, 13... Input selection circuit, 14...
Reset pulse generation circuit, 15...Delay circuit, 1
8... Signal selection circuit, 19... Phase comparison circuit.

Claims (1)

[Claims] 1 A vertical synchronization separation circuit that synchronously separates a composite synchronization signal and generates a vertical synchronization signal, and a horizontal synchronization signal N
(N is an even number) times the frequency of the clock signal,
A first frequency-divided output signal is generated by dividing the frequency of the clock signal to generate a vertical drive pulse of a regular vertical period by self-resetting, and a second frequency-divided output signal is generated at a timing before the reset timing of the regular vertical period. a vertical countdown circuit that generates a frequency output signal; an input selection circuit that switches and outputs the vertical synchronization signal or the first frequency-divided output signal; and a reset of the vertical countdown circuit according to the output signal of the input selection circuit. a reset pulse generation circuit that generates a pulse; a delay circuit that delays the second frequency-divided output signal so that the reset timing is at a regular vertical cycle in the vertical countdown circuit; and an output signal of the reset pulse generation circuit. The output signal of the delay circuit is compared in phase, and depending on the phase mismatch, the first input selection circuit takes in the vertical synchronization signal, and depending on the phase match, the first input selection circuit takes in the first frequency-divided output signal. and a phase comparator circuit that controls to take in the vertical countdown circuit, and resets the vertical countdown circuit in response to the vertical synchronization signal or the first frequency-divided output signal to generate a vertical drive pulse. Vertical drive pulse generation circuit.