JP5554714B2 - Integrated circuit incorporated in non-volatile programmable memory with variable coupling - Google Patents

Description

  The present invention relates to a nonvolatile memory having a variable coupling that can be programmed a plurality of times. The present invention is particularly applicable to each application where it is desirable to customize each electronic circuit.

  One-time programmable (OTP) and multi-time programmable (MTP) memories have recently been introduced for effective use in many applications where customization is required in both digital and analog settings. These applications include data encryption, reference trimming, manufacturing ID, security ID, and many other applications. Nevertheless, incorporating OTP and MTP memory usually consists of several additional processing steps.

  A new form of OTP is disclosed in Patent Document 1, the contents of which are incorporated herein by reference. In this disclosure, a new type of single layer poly-nonvolatile memory device structure is disclosed that can operate as either an OTP (one time programmable) or MTP (multitime programmable) memory cell. The device structure is fully compatible with advanced CMOS logic processes and in the worst case requires minimal additional steps to perform. A unique aspect of the device is that the floating gate of the memory cell structure is electrically hard coupled through one of each S / D junction of the transistor, while the conventional single layer poly-non-volatile The memory cell requires an additional interconnect layer to couple to the floating gate, or the floating gate has virtually no electrical coupling to any of the existing electrical signals or minimal electrical coupling. Need to do.

  Another important feature is that it is implemented with an NMOS device structure, whereas conventional single layer poly OTP is typically implemented with a PMOS device structure. This means that the device can be formed simultaneously with each other n-channel device on the wafer.

  Another advantage of the NMOS device structure is that it functions in the same way as an EPROM device, i.e., the device is programmed from a conducting state to a non-conducting state. (Most commonly used PMOS OTP devices are programmed from a non-conducting state to a conducting state.) In order to verify that a PMOS device then exits the manufacturing plant and becomes non-conducting, The need for additional masking steps associated with PMOS OTP devices can be eliminated. In addition, because the programming mechanism of the NMOS device with channel hot electron injection is self-regulating, the energy consumption during programming in the present invention is different from the case of PMOS with channel thermionic programming. Self-controlled.

  A further advantage of the aforementioned device is the fact that multi-layer functionality can be incorporated very easily simply by adopting various forms of variable electrical coupling as will be explained below. The performance with OTP and MTP cells that can store n bits (rather than just one bit) appears to be unique to the devices described above.

  Patent Document 2 discloses the introduction of another NMOS type OTP, the contents of which are incorporated herein by reference. The device in this reference is programmed by channel hot-hole-injection. The disclosure teaches that the device is programmed to a conductive state after channel hot hole injection. However, it is unclear whether the device actually operates according to the method claimed by each inventor. That is, it is not clear that the channel current will begin to induce hot hole injection because the state of the floating gate is unknown and there is no effective means to couple the voltage to the floating gate. NMOS devices use channel currents to initiate hot hole injection only when the floating gate potential is sufficient to operate the device or when the threshold voltage is always low initially so that channel current conduction is possible. Shed. The only way to establish either situation is to introduce additional processing steps to modify each operating characteristic of the NMOS. Next, assuming that the channel is initially conducting and each hot hole is injected, each hole injected onto the floating gate makes the device more conductive. As such, the device basically moves from a conductive state to a high conductive state (to pass a channel current for hot hole injection). This is not an optimal operation for a memory device.

  Another prior art device described in U.S. Patent No. 6,057,086 (incorporated herein by reference) illustrates a slightly different approach to the challenge of supplying a program supply voltage to the floating gate embodiment of an OTP device. doing. In this design, the coupling ratio to the erasable floating gate 416 is increased by increasing the drain boundary length L1 relative to the source side length L1, as shown in FIG. Increasing the amount of channel current by increasing the coupling ratio results in a further increase in charge injection into the floating gate. However, the disadvantage of this cell is the fact that the cell and channel 412 must be asymmetric and the coupling is only controlled using the length range of each active region. Because of these limitations, it does not appear to be scalable to a multilayer structure. Furthermore, it is clear that it is only implemented as a P-channel device.

  Thus, it is clear that floating gate type programmable memories that can address these deficiencies in the prior art have been needed for many years.

<Cross-reference to related applications>
This application claims the benefit of US Provisional Patent Application No. 60 / 987,869 filed on November 14, 2007, based on Section 119 (e) of the US Patent Act, the contents of which are hereby incorporated by reference. This is incorporated into the description. This application claims the benefit of US patent application Ser. Nos. 12 / 264,029, 12 / 264,060 and 12 / 264,076, all filed on Nov. 3, 2008, and is a part of each application. This is a continuation application, the contents of which are incorporated herein by reference.

This application further includes the following applications, “INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING” (attorney case number JONK 2008-4) , "METHOD OF MAKING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING" (agent case number JONK 2008-5) application number , "METHOD OF OPERATING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING" (agent case number JONK 2008-6) , And INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE MULTIPLE-TIME PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING (attorney case number JONK 2008-7) Each of which is filed on the same day and is incorporated herein by reference.

US patent application Ser. No. 12/264029 US Pat. No. 6,920,067 US Patent Publication No. 2008/0186772

  The object of the present invention is therefore to overcome the above-mentioned limitations in the prior art.

  Accordingly, a first aspect of the invention relates to a programmable multi-state non-volatile device located on a substrate, the device being located on the substrate and a gate for a transistor device associated with a logic gate and / or volatile memory. A floating gate made of a material that is also used as a source, a source region, a drain region, and an n-channel coupling the source region and the drain region, the drain region being applied to the drain Overlying most of the gate so that a program supply voltage can be applied to the floating gate by capacitive coupling, the device is further configured to store more than one bit of information with the program supply voltage.

  In this multi-state embodiment, the device is preferably configured such that only a portion of the drain region receives a read voltage during a read operation. That is, a part or all of the drain region can be biased during a program operation for changing the amount of information stored in the device. In some cases, the device can be read by a bias voltage applied to the drain region that is adjusted according to a time to determine a threshold voltage of the floating gate.

  In another preferred embodiment, the floating gate is erasable so that the device can be reprogrammed. Preferably, the floating gate is erasable by an erase voltage applied to the source region.

  In some applications, the device can be integrated as part of a programmable array incorporated into each separate logic circuit and / or each memory circuit within the integrated circuit. Such a circuit is one of a data encryption circuit, a reference trimming circuit, a manufacturing ID, and / or a security ID, or any other circuit that requires customized non-volatile data. Also good.

  In some embodiments, the capacitive coupling is performed in a first trench located in the substrate. These trenches may be part of an embedded DRAM array. The amount of coupling can be adjusted as desired based on selective control of the gate (interconnect mask, source / drain diffusion mask, or both).

  Another structure includes a second programmable device coupled to an array of pairs of latches, where data and its complement are stored in the pair of latches.

  It is desirable to use a variable program supply voltage to program the device to a multi-level state. As a result, a plurality of bits of data are written by the program supply voltage.

  Another aspect of the present invention relates to a multi-level one-time programmable (MOTP) device located on a substrate, the device being interoperable for transistor devices located on the substrate and associated with logic gates and / or volatile memory. A floating gate made of a material that is also shared by the connection gate and / or another gate, a source region, and a drain region that overlaps a portion of the floating gate and has at least a first drain region and a second selectable drain region The variable capacitive coupling between the drain region and the floating gate can be realized by one or more selection signals respectively applied to the first drain region and the second drain region, and by the variable capacitive coupling, The floating to the variable amount of channel thermoelectrons from the first drain region and the second drain region Permanently by changing the threshold value of the over bets, to store multi-bit data in the OTP device.

  A further aspect of the invention relates to the fact that, in some embodiments, the device is in a multi-level (multi-bit) program state defined by the amount of charge stored on the floating gate by a variable program supply voltage.

  Another aspect of the invention relates to a method of forming the multilevel non-volatile programmable memory device described above.

  Yet another aspect of the invention relates to a method of operating the multilevel non-volatile programmable memory device described above. In a preferred embodiment, the amount of capacitive coupling is based on varying a plurality of N (N> 1) independent drain regions selected to overlap the floating gate and / or a program supply voltage level. It can be adjusted by changing

  If N = 2, the threshold value of the floating gate can be set to one of three or four different values as required. When N = 3, the threshold value of the floating gate can be set to one of eight different values. In order to read the state of the device, it is preferable that the read voltage is controlled to be a value in a range that changes in time corresponding to each threshold state of the floating gate.

  Multi-state devices are preferably programmed with channel thermionics that change the voltage threshold of the floating gate and are erased by interband tunneling hot hole injection. In some embodiments, the device is configured such that a plurality of different regions of the first drain region and the second drain region can be coupled to the gate during program and read operations, respectively. For example, during the program operation, one or both of the first drain region and the second region are biased, or neither is biased, and the first region and the second region are biased. Only one of them can be biased during a read operation. Similarly, one or both of the first region and the second region can be biased during the erase operation.

  The preferred embodiment of the multi-state device is n-channel, but p-channel is also possible. In some applications, the floating gate can be implemented as a multilevel structure, as part of a thin film transistor, or can be placed in a non-planar structure.

  Another aspect of the present invention relates to a single bit NV memory that shares similar structural, formation and operational characteristics as the multi-state device described above.

  Yet another aspect relates to a one-time programmable (OTP) device that includes an interconnect gate and / or another gate for a transistor device located on a substrate and associated with a logic gate and / or volatile memory. Similarly, a floating gate made of a common material, a source region, and a drain region overlapping at least a part of the floating gate and having at least a first drain region and a second selectable drain region, the drain region and the floating region The variable capacitance coupling between the gate and the gate can be realized by one or more selection signals respectively applied to the first drain region and the second drain region, and the first drain region can be realized by the variable capacitance coupling. And a variable amount of channel thermoelectrons from the second drain region permanently change the threshold of the floating gate. And stores the data in the OTP device.

  The OTP device can be configured in the same structure and operation as the multi-level device described above. That is, the amount of capacitive coupling can be adjusted based on controlling / selecting the amount of overlap with multiple N (N> 1) independent drain regions or floating gates, or using a variable program supply voltage. .

  The device is preferably formed by a mask / CMOS process used to form other logic devices and / or memory n-channel devices in the processing circuitry, embedded in the processing circuitry. In some cases, non-volatile programmable memory devices are used to store one or more identification codes for the die / wafer.

  It will be appreciated from the detailed description that the invention can be practiced in many different embodiments. Moreover, those skilled in the art will readily recognize that each such different embodiment will include only one or more of the above-described objects of the invention. Accordingly, lack of one or more of such properties in any particular embodiment should not be construed as limiting the scope of the invention. Although described in the context of a non-volatile memory array, it will be apparent to those skilled in the art that the present teachings can be used in any application.

1 is a comprehensive view of a preferred embodiment of a non-volatile memory cell of the present invention. 1 is a cross-sectional side view of a preferred non-volatile memory cell. It is an electric circuit diagram which shows the electrical relationship of the structure of a suitable non-volatile memory cell. Figure 2 illustrates a prior art non-volatile memory cell using a floating gate for OTP applications. FIG. 3 is an electric circuit diagram showing a preferred embodiment of a latch circuit configured with each NV memory cell of the present invention. FIG. 3 is a comprehensive view of a preferred embodiment of a non-volatile memory cell of the present invention that utilizes variable coupling. It is an electric circuit diagram which shows the electrical relationship of each structure of the suitable non-volatile memory cell using a variable coupling.

  The present disclosure relates to a new type of non-volatile memory device structure (preferably single layer poly) operable as either an OTP (one time programmable) or MTP (multitime programmable) memory cell utilizing variable capacitive coupling. . The preferred device structure is fully compatible with advanced CMOS logic processes and in the worst case requires minimal additional steps to perform.

A unique aspect of the device is that the floating gate of the memory cell structure is electrically hard coupled through an indefinite number of S / D junctions of the transistor, while the conventional single layer poly-nonvolatile memory The cell requires an additional interconnect layer to couple to the floating gate, or the floating gate has virtually no electrical coupling to any of the existing electrical signals or minimal electrical coupling. Need to do. Further, unlike US Patent Publication No. 2008/0186772, the coupling ratio can be made more specific and accurate. That is, by accurately controlling the coupling ratio (by area average), ie, the amount of charge, the final programmed Vt is directly proportional to the product of the coupling ratio and the drain voltage. The coupling ratio can be more accurately controlled so that the coupling ratio is determined or set by the desired programming threshold level (V _t ) of the memory cell. Thus, different because each binding ratios produce a programmed different V _t, it is possible to design that readily expanded to a multi-level version of the OTP.

  FIG. 1 shows a top view of the layout of a preferred structure used in the present invention. FIG. 2 shows a representative cross-sectional view of the device structure. It will be understood that these figures are not intended to be enlarged, but have been made clear by omitting some aspects of the device.

  The device includes a standard NMOS transistor 100, which is modified so that the device gate (which is poly in the preferred embodiment) 110 is not electrically connected to a power source. The device drain 120 is preferably curved near the N-type well 130 already commonly present in conventional advanced CMOS processes, and is preferably joined by the N-type well 130. As an alternative, the N-well 130 can be replaced with an n-type diffusion layer introduced so as to be directly under the poly floating gate. A conventional source region 125 is similarly utilized.

  The floating gate poly 110 has an overlap region 140 that extends beyond the standard transistor channel region 135 and overlaps the active region extending from the drain junction surface. The active region portion 141 surrounded by the N-Well region serves as an effective capacitive coupling with the floating gate. Thus, any voltage applied to the drain junction is effectively coupled onto the floating gate.

  As shown in the electrical circuit diagram of FIG. 3, when the coupling ratio of the drain to the floating gate (determined by the ratio of the area of the gate channel region to the poly extension area overlapping the drain extension region) is sufficiently high, It is possible to effectively ensure and have a high drain voltage value ratio.

  As shown in FIGS. 1 and 2, an important advantage of the preferred embodiment is that it is formed from the same layers conventionally used to activate each n-type channel device in a CMOS process. The only difference is that the poly (or possibly metal) gate layer is not interconnected to each such separately formed active device or coupled to the gate signal. Each other source / drain implant is also part of a CMOS conventional process. Therefore, in most applications, the present invention can be integrated without additional processing costs because the only alternative is an existing mask for each relevant layer of the wafer being processed.

  Another optional variation of this device structure is to create a capacitor region on the trench sidewall that couples the drain and gate. This greatly reduces the area between the drain and gate coupled to the capacitor. This reduction in cell area comes at the expense of significantly complicating the manufacturing process. In addition, however, in applications where the present invention is integrated with certain types of DRAM architectures (especially embedded), conventional processing steps for such memories are incorporated to avoid additional processing costs. Is possible. Other techniques for coupling voltage to the floating gate and achieving the desired coupling ratio will be apparent to those skilled in the art.

  Although the floating gate is shown as a single polysilicon layer, those skilled in the art will appreciate that other materials can be used as well. For example, some applications utilize other structures / device configurations that are part of other major underlying logic / memory structures, but can also be used for the purpose of creating some floating gates. It may be possible. In this regard, it should be noted that each floating gate can usually be formed from a number of different materials, including by techniques in which each impurity is embedded / diffused in a dielectric / insulating layer.

  Further, although the preferred embodiment shows the NVM cell as part of a conventional outer and planar FET structure on the substrate, it will be apparent to those skilled in the art that other shapes / architectures including non-planar structures can be utilized. Will. Therefore, the present invention can be used in each SOI substrate in multi-gate (FINFET type) orientation and vertical / non-planar structures in thin film structures, at each other level of the device than the substrate. In such latter case, the floating gate is built and oriented perpendicular to the substrate.

  A preferred operation of the device 100 will be described. The non-volatile device structure preferably comprises the physical characteristics of a conventional I / O transistor that is implemented in an advanced CMOS logic process. At present, such I / O transistors nominally operate at 3.3V, but it is understood that this value will change with subsequent generations in the manufacturing industry.

  This type of I / O transistor typically has a threshold voltage of 0.5V to 0.7V with a standard electrical gate oxide thickness of 70A. With a drain coupled to the floating gate with a coupling ratio of 0.90 and a read drain voltage of 1.0V applied to the device, the floating gate will be effectively coupled at a voltage of approximately 0.90V. This is sufficient to activate the unprogrammed NMOS device 100, and the channel current can be sensed by common means of sense circuitry that confirms the state of the device. It will be appreciated by those skilled in the art that specific coupling ratios, read voltages, etc. can vary from application to application, and can be configured based on the desired device acting on each characteristic.

  The device is in an unprogrammed state, which is characterized in the preferred embodiment by a low resistance coupling between the source and drain through the channel region 135. . This means that the channel region 135 can be made substantially uniform and the current flow is reliable. Although the preferred embodiment is shown in a symmetric cell / channel shape, it is understood that the invention can be used in an asymmetric shape as shown in the aforementioned US Patent Publication No. 2008/0186772. Will.

  In order to put the device into the programmed state, the device must be blocked by decreasing each carrier in the channel region and further increasing the threshold voltage. For this, it is possible to apply a drain voltage of 6.0V, which effectively couples a voltage of about 5.4V to the floating gate. This bias condition sets the device to channel thermionic injection regime. Each electron injected into the floating gate effectively increases the threshold voltage of the device. If a subsequent read voltage of 1.0V is applied again on the drain, the device will not conduct current as a result of its high threshold voltage, thus determining the second state of the device. It will be appreciated by those skilled in the art that the specific coupling ratio, program voltage, etc., as well as each characteristic read, can vary from application to application and can be configured based on the desired device acting on each characteristic.

  The above-described prior art is mainly a one-time programmable device because a mechanism for releasing the charge on the floating gate is not disclosed. In contrast, some embodiments of the present invention allow multi-time programming. For this reason, a canceling operation can be introduced to remove or neutralize each electron injected into the floating gate. The mechanism for removing or neutralizing each electron is preferably by band-to-band tunneling hot hole injection from the other uncoupled interface 125 of the device. A suitable bias condition is as follows. The non-coupling junction surface (source junction surface) induces an interband tunneling current in the junction surface by applying a bias of 6V. The band-to-band tunneling current injects hot holes into the floating gate and neutralizes each electron stored on the floating gate. Thus, the device is (re) programmed from a non-conducting or low conducting state to a conducting state. The device can then channel current if a subsequent read voltage is applied to the connecting interface during the read operation. It will be appreciated that programming from a low conduction state to a conduction state may have a limited work readout window.

  As an optional additional step, the floating gate is more negatively charged to facilitate the erase operation and increase the interband tunneling current, resulting in higher interband tunneling current across the source interface. The joint surface can be supplied with a negative voltage.

Accordingly, it is preferable that each work characteristic is as follows.

  In some embodiments, additional protection can be performed to ensure that the OTP and MTP devices are sufficiently resistant to the loss of charge stored on the floating gate. To this end, the device can be configured in a pair of latches 500, as shown in FIG. 5, where the data and its complement are stored in the latches, effectively doubling the margin in the stored data. To. As shown therein, upper device 510 couples node 530 to a first voltage reference (Vcc), while second lower device 520 couples the node to a second voltage reference (Vss). By charging the upper device floating gate, the upper device 510 is programmed to a non-conductive state, and the node 530 is reliably pulled down to Vss by the lower device 520, indicating a first logical data value (0). Similarly, by charging the lower device floating gate, the lower device 520 is programmed to a non-conductive state, and the node 530 is reliably pulled up to Vcc by the upper device 510, indicating a second logical data value (1). Become.

  Another useful advantage of the preferred embodiment of the present invention is that each conventional single layer poly OTP is typically implemented with a PMOS device structure, but this embodiment is implemented with an NMOS device structure. . This means that the device can be formed simultaneously with each other n-channel device on the wafer. Another advantage of the NMOS device structure in the present invention is that it functions in the same way as an EPROM device, i.e., the device is programmed from a conducting state to a non-conducting state. In contrast, the prior art type device of US 2008/0186772 and each other commonly used PMOS OTP device is programmed from a non-conducting state to a conducting state. Thus, this aspect of the present invention can eliminate the need for an additional masking step generally associated with PMOS OTP devices to ensure that the PMOS devices exit the manufacturing plant and become non-conductive.

  In addition, because the programming mechanism of the NMOS device with channel hot electron injection is self-regulating, the energy consumption during programming in the present invention is different from the case of PMOS with channel thermionic programming. Self-controlled.

  Thus, as shown herein, the particular configuration of the floating gate is not critical. All that is required is that it be structurally and electrically configured to control channel conduction and capacitively coupled to an electrical source of charge carriers. It can be changed to a specific shape according to the desired layout or mask. In some cases, it is desirable to mount the floating gate as a multilayer structure, for example. Furthermore, since capacitive coupling is a function of each material used, the present invention allows for great flexibility so that the configuration of the floating gate can be modified and integrated into a specific process to accommodate it as desired. . Each cell array constructed in accordance with the present teachings can include each floating gate of a different shape and size such that each cell having a threshold cell can be formed.

Variable Coupling In other embodiments of the present invention, the effective coupling ratio of device 100 can be different or varied between read, program and / or erase operations. That is, although not shown in FIGS. 1 and 2, the drain region 120 coupled to the floating gate can be divided into one or more separate sub-regions. This detail is shown in FIGS. 6A and 6B. Each sub-region 121, 122, etc. can be manufactured or controlled so that the amount of overlap with the floating gate is different. By selectively applying different voltages to one or more such sub-regions, different types of performance can be achieved for read / program / erase operations. For example, it may be desirable to have a very low power (but somewhat slower) program or erase operation. This can be achieved by creating a combined area for such a first type of operation that is smaller than the nominal area used during the second type (read) operation.

  6A and 6B, the variable coupling geometry is done by changing the drain diffusion size (in the diffusion mask) and keeping the floating gate size constant, but the same effective result is the drain It will be apparent to those skilled in the art that this can be achieved by changing the size of the floating gate while keeping the diffusion constant. For example, the floating gate region 122 can provide the same result by reducing its size. By adjusting the size of each floating gate, each diffusion region can be shared as well, so that adjacent floating gates 122 ′ (for other cells) can be coupled to the drain region 120. Other combinations of these technologies can be used as well and can be selected based on design / performance requirements.

  In particular, the variable coupling aspects of the present invention can be used for both PMOS and NMOS OTPs. Different coupling ratio selections are also available to provide different voltages on floating gates that are multi-state preserved, ie multi-level OTP potential.

  In another embodiment, of course, drain coupling is accomplished by instead adjusting the program supply voltage, and the program supply voltage applied to a particular cell is adjusted to write different states to the floating gate. Since the drain is coupled to the floating gate, the variable program supply voltage should be supplied to the floating gate. For example, the drain voltage can be adjusted to have three, four or more different levels. This results in a different type of variable capacitive coupling, which is more complex from a write perspective, but may be useful in some applications.

  A variation of the multi-level OTP for NMOS implementation is that the NMOS is programmed to an off state, except when using different levels of each floating gate voltage through different drain voltages applied to sense the state, It must be taken into account that being somewhat off is very similar to being fully off. However, in such a situation, different drain voltages may improperly reduce read disturb tolerance and can be replaced here.

  For other choices of multi-level performance, read operations detect multi-state cells because different drain-to-gate capacitance selections are used to select programming states (through different overlapping areas). Can be performed by the same single drain overlap. For example, a total of 2 bits can be implemented due to two different drain overlaps. In such an implementation, drain 1 can be set to have a coupling ratio that is several times the coupling ratio of drain 2 (a multiple of 2 is preferred in this case).

  As shown in the following table, a program supply voltage that applies a voltage of 0 V to drain 1 and a voltage of 6 V to drain 2 writes the first state to the cell based on the first charge amount applied to the gate. It will be. If instead all drains are programmed, the added charge will be higher, corresponding to the second state, etc.

  A total of four different combinations (0 (no drain), 1x (drain 2), 2x (drain 1), 3x (both drain 1 and drain 2)) correspond to four different threshold voltages, Two different logic states can be achieved in this simple array.

  As shown in Table 2 below, the preferred method of reading the state of the cell is to apply a read voltage to both drain 1 and drain 2. As a result, the amount of cell current that is inversely proportional to the amount of charge on the floating gate is detected. As mentioned above, the charge on the floating gate is a linear function of the amount of coupling applied during programming. Thus, the 0, 1x, 2x and 3x states in the cell can be detected by the relationship with the read current. In this embodiment, the read drain voltage is preferably selected to be about 1 volt. This has the advantage of preventing any kind of read disturb or leakage caused by the drain.

  As an alternative to reducing decoding during the read operation, the read can always be done on the drain node by the 2x drain, which is the highest coupling ratio in this embodiment. In such a case, it is not possible to differentiate between all four different states, but may be a good tradeoff in some applications.

  Similarly, as shown in Table 2, as a further alternative to reading the multi-level cell state, the combined charge contributions from overlapping portions assembled by biasing each (or combination) of each drain by gradually changing the voltage Determine (coupled charge contribution). Gradually into the drain (from 0 to any threshold sufficient to bring the gate to the highest threshold state) until the threshold voltage is achieved or decoded within a specific time interval at a specific voltage level to confirm the state of the cell Bias with increasing voltage (to the target voltage). Thus, all or some of the drains can be biased during the program operation, but only a single drain can be read to determine the state of the cell (although other drains can be biased as described above). Need to be biased in. The specific range of read drain voltage depends on the specific cell structure, such as the desired operating characteristics, and can be determined by periodic inspection. Also in this embodiment, it is not possible to differentiate between all four different states, but it may be a good trade-off in some applications. Other embodiments for programming and reading the cell will be apparent to those skilled in the art.

  Of course, other coupling ratios are possible, but the detection margin / differentiation may not be excellent, subject to the constraints of choosing a different ratio that is not a multiple of 2. However, in some cases it may be desirable to set each overlap to an arbitrarily higher / lower magnification, which has the effect of reducing the detection margin between two adjacent states in any output range. Let's go. However, if the sensitivity of the detection range is unequal, this would be a good option (ie if it is easier to detect the difference between 1x and 2x than between 4x and 5x, Or vice versa). Further, in some cases, it may be desirable to reduce the number of valid logic states by discarding one of each combination that results in an odd number of logic states. For example, a multi-bit cell can simply have three programmed drain couplings of {0, drain 1, drain 2} and {drain 1 + drain 2} will be ignored.

  Although two separate coupling ratios are shown in FIG. 6A and three separate coupling ratios are shown in FIG. 6B, it will be understood that other splits and combinations can be performed in accordance with the present teachings. For example, in the case of FIG. 6B, eight different programming states can be realized by utilizing three different levels of charge coupling. For example, different combinations of drains having 1x, 2x and 4x coupling ratios can be combined, or some other ratio combination. Furthermore, other selections can be made with fewer logic states at the expense of higher margins between the states. Other variations of the invention will be apparent to those skilled in the art.

  The above descriptions are merely exemplary embodiments of each proposed invention. The protection afforded this invention includes and applies to embodiments that differ from the above-described embodiments, but it is understood that such embodiments fall within the scope of the claims.

Claims (44)

A floating gate made of a material located on a substrate and used as a gate for a transistor device associated with at least one logic gate or volatile memory;
A source area,
A drain region;
An n-channel coupling the source region and the drain region;
The floating gate has an overlapping region extending beyond the n-channel and overlapping an active region extending from a drain junction surface of the drain region;
The drain region, the program supply voltage to program the device is applied to the drain region, so that it can be applied to the floating gate by spatial capacitive coupling is between the floating gate and the drain region overlapping Overlaps most of the gate in the region ,
Further, the device is a programmable multi-state non-volatile device located on a substrate configured to store more than one bit of information with the program supply voltage.   The drain region includes a plurality of drain regions, and only a single drain region of the plurality of drain regions receives a read voltage to determine the state of the device. Programmable devices.   The drain region includes a plurality of drain regions, and biases a part or all of the plurality of drain regions during a program operation for changing the amount of information stored in the device. The programmable device according to claim 1, wherein   The programmable device of claim 1, wherein the floating gate is erasable.   The programmable device of claim 4, wherein the device is reprogrammable.   The programmable device according to claim 4, wherein the floating gate is erasable by an erasing voltage applied to the source region.   The programmable device of claim 1, wherein the device is part of a programmable array incorporated into each separate logic circuit and / or each memory circuit in an integrated circuit.   8. The programmable device of claim 7, wherein the device is associated with at least one of a data encryption circuit, a reference trimming circuit, a manufacturing ID, or a security ID.   2. The programmable device according to claim 1, wherein the spatial capacitive coupling is performed between a part of the floating gate covering the substrate and a first trench located on the substrate and including a part of the drain region. device.   The programmable device of claim 9, wherein the set of second trenches in the substrate is used as an embedded DRAM.   The programmable device of claim 1, further comprising a second programmable device coupled to an array of pairs of latches, wherein data and its complement are stored in the pair of latches.   The programmable device according to claim 1, wherein the drain region is read by a bias voltage applied to the drain region that is adjusted until a threshold voltage of the floating gate is determined.   The programmable device of claim 1, wherein the device is programmed to a multi-level state with a variable program supply voltage. A floating gate made of a material containing impurities that functions as a charge storage position, and is used as an insulating layer for each other non-programmable device located on the substrate;
A source area,
A drain region comprising a first drain region and a second drain region;
An n-channel coupling the source region and the drain region ;
The floating gate has an overlapping region extending beyond the n-channel and overlapping an active region extending from a drain junction surface of the drain region;
The drain region, the program supply voltage to program the device is applied to the drain region, so that it can be applied to the floating gate by spatial capacitive coupling is between the floating gate and the drain region overlapping Overlaps most of the gate in the region ,
Further, the device is a multi-level programmable device located on a substrate configured such that a plurality of bits of data can be written by the program supply voltage. A floating gate located on the substrate and made of material shared by at least one logic gate or transistor device associated with a volatile memory and / or another gate;
A source area,
A drain region overlapping at least a portion of the floating gate and having at least a first drain region and a second selectable drain region ;
An n-channel coupling the source region and the drain region ;
The floating gate has an overlapping region extending beyond the n-channel and overlapping an active region extending from a drain junction surface of the drain region;
Spatial variable capacitive coupling between the drain region and the floating gate is imparted to the floating gate to achieve the variable capacitive coupling between the drain region and the floating gate in the overlap region. The operation voltage can be realized by one or more selection signals respectively applied to the first drain region and the second selectable drain region,
The variable capacitive coupling causes a variable amount of channel thermal electrons from the first drain region and the second selectable drain region to permanently change the threshold value of the floating gate to store multi-bit data in the OTP device. Multi-level one-time programmable (MOTP) device located on the substrate. A multi-level programmable memory device having a gate, an n-type impurity source, and an n-type impurity drain on a silicon substrate,
An n-type channel for coupling the impurity source and the impurity drain ;
The gate has an overlapping region extending beyond the n-type channel and overlapping an active region extending from a drain junction surface of the impurity drain;
The n-type impurity drain applies a variable program supply voltage applied to the n-type impurity drain to program the device to the gate by a spatial capacitive coupling between the gate and the n-type impurity drain. And overlapping a majority of the gates in the overlap region so that multi-level logic states can be stored in the device,
The gate adapts to function as a floating gate so that the device is in a multi-level program state defined by the amount of charge stored on the gate by the variable program supply voltage;
Furthermore, the charge on the floating gate can be erased such that the device can be reprogrammed. A multi-level one-time programmable (MOTP) memory cell having a gate, an n-type impurity source, and an n-type impurity drain on a silicon substrate,
An n-type channel for coupling the impurity source and the impurity drain ;
The gate has an overlapping region extending beyond the n-type channel and overlapping an active region extending from a drain junction surface of the impurity drain;
The n-type impurity drain is configured to overlap a variable portion of the gate in the overlapping region so that a voltage applied to the n-type impurity drain to program the cell can be applied to the gate by spatial capacitive coupling. And
The multi-level one-time programmable memory cell, wherein the gate is configured such that the MOTP cell is in a programmed state defined by a charge state of the gate, the charge state corresponding to a plurality of bits of data. A floating gate made of a material located on a substrate and used as a gate for a transistor device associated with at least one logic gate or volatile memory;
A source area,
A drain region comprising a first drain region and at least one other second drain region ;
A channel for coupling the source region and the drain region ;
The floating gate has an overlapping region extending beyond the channel and overlapping an active region extending from a drain junction surface of the drain region;
The drain region, the program supply voltage to program the device is applied to the drain region, so that it can be applied to the floating gate by spatial capacitive coupling is between the floating gate and the drain region overlapping Overlaps most of the gate in the region ,
Further, the device is a programmable non-volatile located on a substrate configured such that a plurality of different regions of the first drain region and the second drain region can be coupled to the gate, respectively, during programming and reading operations. device.   The programmable device of claim 18, wherein the device is n-channel.   The programmable device of claim 18, wherein the device is a p-channel.   The device is configured to bias one or both of the first drain region and the second drain region during a program operation, or neither, and the first drain region The programmable device of claim 18, wherein only one of the second drain region is configured to be biased during a read operation.   The device is configured such that neither the first drain region nor the second drain region is biased during a program operation, or both are biased, and the first drain region is erased during an erase operation. The programmable device of claim 18, configured to bias one or both of the region and the second drain region.   The device is configured to bias or not to either or both of the first drain region and the second drain region during a program operation, and to perform the first operation during a read operation. The programmable device of claim 18, wherein one or both of the first drain region and the second drain region are configured to be biased.   The device is configured to change at least one of a program operation, a read operation and / or an erase operation during operation by changing a coupling of the first drain region and the second drain region to the gate. The programmable device of claim 18, wherein:   The programmable device of claim 18, wherein the floating gate is erasable.   26. The programmable device of claim 25, wherein the device is reprogrammable.   26. The programmable device according to claim 25, wherein the floating gate is erasable by an erasing voltage applied to the source region.   The programmable device of claim 18, wherein the device is part of a programmable array embedded in each separate logic circuit and / or each memory circuit in an integrated circuit.   30. The programmable device of claim 28, wherein the device is associated with one of a data encryption circuit, a reference trimming circuit, a manufacturing ID, and / or a security ID.   The programmable device of claim 18, wherein the capacitive coupling is performed in a first trench located in the substrate.   31. The programmable device of claim 30, wherein the set of second trenches in the substrate is used as an embedded DRAM.   The programmable device of claim 18, further comprising a second programmable device coupled to the array of pairs of latches, wherein data and its complement are stored in the pair of latches.   A bias voltage applied to one of the at least one other second drain region that is adjusted before determining a threshold voltage of the first drain region and / or the floating gate. The programmable device of claim 18, wherein the drain region is read.   The programmable device of claim 18, wherein the floating gate is a multi-level structure.   The programmable device of claim 18, wherein the device is part of a thin film transistor.   The programmable device of claim 18, wherein the floating gate is disposed in a non-planar structure.   The programmable device according to claim 18, wherein the floating gate is formed of at least one structure other than the device, and includes each impurity as a charge accumulation position. A floating gate made of a material containing impurities that functions as a charge storage position, and is used as an insulating layer for each other non-programmable device located on the substrate;
A source area,
Drain region and
An n-channel coupling the source region and the drain region ;
The floating gate has an overlapping region extending beyond the n-channel and overlapping an active region extending from a drain junction surface of the drain region;
The drain region, the program supply voltage to program the device is applied to the drain region, so that it can be applied to the floating gate by spatial capacitive coupling is between the floating gate and the drain region overlapping Overlaps most of the gate in the region ,
Further, the device is a programmable device located on a substrate configured to allow a variable program supply voltage to be coupled to the gate during a program operation to provide a variable threshold for the programmable device. One time programmable (OTP) device,
A floating gate located on the substrate and made of material shared by at least one logic gate or transistor device associated with a volatile memory and / or another gate;
A source area,
A drain region overlapping at least a portion of the floating gate and having at least a first drain region and a second selectable drain region;
An n-channel coupling the source region and the drain region ;
The floating gate has an overlapping region extending beyond the n-channel and overlapping an active region extending from a drain junction surface of the drain region;
Spatial variable capacitive coupling between the drain region and the floating gate is imparted to the floating gate to achieve the variable capacitive coupling between the drain region and the floating gate in the overlap region. Can be realized by one or more selection signals applied to the first drain region and the second selectable drain region, respectively.
A substrate with a variable amount of channel thermoelectrons from the first drain region and the second selectable drain region that permanently changes a threshold value of the floating gate and stores data in the OTP device due to the variable capacitive coupling. One time programmable (OTP) device located above. A one-time programmable (OTP) memory device incorporated on a silicon substrate with at least one other additional logic device or non-OTP memory device,
a. A drain region spatially capacitively coupled to the floating gate ; and an n-channel coupling the source region and the drain region , wherein the floating gate extends beyond the n-channel and the drain It has an overlapping region that overlaps the active region extending from the drain junction surface of the region,
b. Any and all regions and structures of the OTP memory device are simply derived from the corresponding regions and structures used as components of the at least one other additional logical device or non-OTP memory device,
c. The amount of spatial capacitive coupling between the floating gate and the drain region is such that the variable capacitance coupling is achieved in the drain region so as to achieve the variable capacitive coupling between the drain region and the floating gate in the overlapping region. A memory device characterized in that it can be varied during at least one different program, erase, or read operation by an applied voltage applied to the floating gate. A multi-level one-time programmable (MOTP) memory cell incorporated on a silicon substrate with at least one other additional logic device and / or non-OTP memory device,
a. A drain region spatially capacitively coupled to the floating gate ; and an n-channel coupling the source region and the drain region , wherein the floating gate extends beyond the n-channel and the drain It has an overlapping region that overlaps the active region extending from the drain junction surface of the region,
b. Any and all regions and structures of the MOTP memory cell are simply derived from corresponding regions and structures used as components of the at least one other additional logic device or non-MOTP memory device,
c. The amount of spatial capacitive coupling between the floating gate and the drain region is applied to the floating gate so as to achieve the variable capacitive coupling between the drain region and the floating gate in the overlapping region. The memory cell can be changed according to a voltage applied during a program operation for storing a plurality of bits of data in a single MOTP memory cell.   The programmable device of claim 1, wherein the applied program supply voltage causes a current to flow through a transistor channel region between the source region and the drain region.   The programmable device of claim 1, wherein the spatial capacitive coupling is achieved by covering a region of an n-type well or n-type diffusion layer under the floating gate.   The programmable device of claim 1, wherein the device is programmed without applying the program supply voltage applied to the drain region via another device external to the device.

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