JP4557950B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device having nonvolatile memory cells, and particularly suitable for integration in a semiconductor chip together with peripheral circuits composed of logic circuits.

  In recent years, there has been an increasing demand for nonvolatile semiconductor memory devices capable of programming data after manufacturing a semiconductor chip at a low cost on the user side for constructing a semiconductor system. Such a nonvolatile semiconductor memory device needs to be integrated on a semiconductor chip together with a CPU (Central Processor Unit), an MPU (Micro Processor Unit), etc. in order to ensure higher security.

  2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory device that can be electrically erased, a device using a stacked gate structure transistor including a control gate electrode and a floating gate electrode as a memory cell is known.

  As described above, it is known that a nonvolatile semiconductor memory device using a transistor having a stacked gate structure has high reliability. However, its specification, element structure, and manufacturing process are unique to the nonvolatile semiconductor memory device. However, since the consistency with other logic products is poor, a large increase in the process and cost are caused when integrating in the same semiconductor chip together with peripheral circuits composed of logic circuits such as CPU and MPU.

  Conventionally, as a nonvolatile semiconductor memory device that can be easily integrated in the same semiconductor chip together with a peripheral circuit composed of a logic circuit, a device described in Non-Patent Document 1, for example, is known.

  FIG. 15 shows an element cross-sectional structure of the memory cell described in Non-Patent Document 1, and FIG. 16 shows an equivalent circuit of the memory cell array.

  As shown in FIG. 15, a plurality of N-type wells (N-well, only one is shown in the figure) 62 are formed on a P-type semiconductor substrate (P-sub) 61. A source region 63 and a drain region 64 made of a P + type diffusion layer are formed in each of the plurality of N-type wells 62, and a gate electrode 65 is formed on the substrate between the source and drain regions. A cell transistor 66 composed of a P-channel MOS transistor is formed in the mold well 62. The gate electrode 65 of the cell transistor 66 is not electrically connected anywhere and is in a floating state in terms of potential.

  In each N-type well 62, a contact region 67 made of an N + type diffusion layer for making contact with the N-type well is formed. This contact region 67 is connected to the bit line BL together with the source region 63. The drain region 64 of the cell transistor is connected to the node of the ground potential via a selection transistor 68 made of an N channel MOS transistor. The gate electrode of the selection transistor 68 is connected to the word line WL.

  A large number of memory cells having an element structure as shown in FIG. 15 are formed to constitute a memory cell array. In this memory cell array, as shown in FIG. 16, a plurality of word lines WL and bit lines BL are extended so as to intersect each other, and memory cells MC are arranged at the intersections of each word line WL and each bit line BL. Has been. Each memory cell MC has a configuration in which a cell transistor 66 whose gate electrode is not electrically connected anywhere and is in a floating state as described above and a selection transistor 68 are connected in series. Yes. In FIG. 16, a region surrounded by a broken line corresponds to the N-type well 62 in FIG.

  In the nonvolatile semiconductor memory device having such a configuration, after manufacturing the semiconductor chip, the entire surface of the chip is irradiated with ultraviolet rays, so that the gate electrodes of the cell transistors 66 of all the memory cells MC are initialized to have no charge. The threshold value of the cell transistor 66 is set to a constant negative value.

  At the time of data writing, a voltage of about 5 V, for example, is applied to the selected bit line BL. As a result, the N-type well 62 connected to the selected bit line BL is also set to about 5V at the same time. Further, an “H” level potential is applied only to the selected word line WL, the selection transistor 68 is turned on, and 0 V is transferred to the P + type diffusion layer which is the drain region 64 of the cell transistor 66. At this time, the other word lines are grounded to 0 V, and the selection transistor 68 is turned off. In the selected cell transistor 66 located at the intersection of the selected bit line and the selected word line, both the N-type well 62 and the source region 63 are around 5V, and the drain region 64 is 0V.

  After the ultraviolet irradiation, since the threshold value of the cell transistor 66 is a negative value, the cell transistor 66 is turned on, a current flows between the drain region 64 and the source region 63, and a part becomes hot electrons. Electrons are injected into the gate electrode 65 through the gate insulating film. As a result, the threshold voltage of the cell transistor 66 rises to a positive value. For example, this is a “0” storage state.

  In the cell transistor 66 that does not want to inject electrons, the potential of the bit line BL connected to the cell transistor is set to 0 V, and the negative threshold voltage at the time of ultraviolet irradiation is maintained as it is. For example, this is a “1” storage state.

  In reading data, a predetermined positive potential is applied to the selected bit line BL, a predetermined positive potential is applied to the selected word line WL, and the selection transistor 68 is turned on. When electrons are not injected into the gate electrode 65 of the cell transistor 66 and the state is still irradiated with ultraviolet rays, the threshold voltage of the cell transistor 66 is negative, so that it is turned on, and between the source and drain Through the bit line BL.

  On the other hand, when electrons are previously injected into the gate electrode 65 and written, and the threshold voltage is shifted to a positive polarity, the cell transistor 66 is turned off and no current flows through the bit line BL.

  As described above, when data is read, the cell transistor is divided into an on state and an off state depending on whether or not the data is written, and a current flows through the bit line BL or does not flow accordingly. Then, whether or not a current flows through the bit line BL is determined by the sense amplifier, and data “0” and “1” are detected.

  However, this nonvolatile semiconductor memory device has the following problems. First, the first problem is that electrical erasure cannot be performed. That is, for erasing by ultraviolet irradiation, it is necessary to use a package with a window in which quartz glass that transmits ultraviolet rays is fitted, but such a package is very expensive.

  The second problem is that the cell area increases because it is necessary to provide an N-type well independently for each memory cell. For this reason, a memory device having a very large bit capacity cannot be formed on a semiconductor chip.

Note that Patent Document 1 discloses a semiconductor memory device in which a memory cell includes a selection transistor and a storage transistor having an electrically floating charge storage layer.
A. Bergemont et al., 2000 Non-Volatile Semiconductor Memory Workshop, pp. 86-89, "A Non-Volatile Memory Device with True CMOS Compatibility" JP-A-6-204487

  As described above, the conventional nonvolatile semiconductor memory device that does not require a transistor having a stacked gate structure has problems such as an inability to perform electrical erasure and an increase in cell area.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to be easily integrated on a semiconductor chip in combination with a peripheral circuit composed of a logic circuit and to perform electrical erasure. It is possible to provide a non-volatile semiconductor memory device having a small cell area.

The nonvolatile semiconductor memory device according to the present invention includes a selection transistor composed of a MOS transistor having a gate electrode, a source line connected to one end of the selection transistor, and a gate electrode of the selection transistor , extending in a first direction. A first cell transistor composed of a MOS transistor having the same polarity as the selection transistor, one end connected to the other end of the selection transistor, a gate electrode, and one end connected to the other end of the selection transistor A second cell transistor connected to the other end of the first cell transistor and made of a MOS transistor having the same polarity as the selection transistor, and a second direction connected to the other end of the second cell transistor and intersecting the first direction comprising a memory cell array formed on a semiconductor substrate and a extended bit line A diffusion region having the same conductivity type as the source / drain region of the cell transistor is formed in the channel region of the second cell transistor, and the gate electrodes of the first and second cell transistors are connected to each other and electrically The channel region of the second cell transistor is in a floating state without being connected to the first cell transistor, and the dimension of the channel region of the second cell transistor is larger than the dimension of the channel region of the first cell transistor in the second direction. To do.

The nonvolatile semiconductor memory device of the present invention is connected to a selection transistor composed of a MOS transistor having a gate electrode, a bit line connected to one end of the selection transistor and extending in a first direction, and a gate electrode of the selection transistor And a word line extended in a second direction intersecting the first direction , a gate electrode, one end connected to the other end of the selection transistor, and comprising a MOS transistor having the same polarity as the selection transistor. A second cell transistor having a one-cell transistor, a gate electrode, one end connected to the other end of the first cell transistor, the MOS transistor having the same polarity as the selection transistor, and the other end of the second cell transistor; And a memory cell array formed on a semiconductor substrate including a source line connected to A diffusion region having the same conductivity type as that of the source / drain region of the cell transistor is formed in the channel region of the first cell transistor, and the gate electrodes of the first and second cell transistors are connected to each other. The channel region of the first cell transistor has a dimension in the first direction larger than the dimension of the channel region of the second cell transistor in the first direction. To do.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device that can be easily integrated on a semiconductor chip by being embedded with a peripheral circuit including a logic circuit, can be electrically erased, and has a small cell area. it can.

  Hereinafter, the present invention will be described in more detail with reference to the drawings.

(First embodiment)
FIG. 1 is an equivalent circuit diagram showing a partial configuration of a memory cell array of the nonvolatile semiconductor memory device according to the first embodiment. As shown in the drawing, the plurality of bit lines BL1, BL2,... BLm are arranged to extend in the first direction. In addition, a plurality of word lines and source lines (two word lines WL1, WL2, and source lines, respectively) are extended in a second direction intersecting with the extending direction of the plurality of bit lines BL1, BL2,. Only SL1 and SL2 are shown).

  Memory cells MC are respectively arranged at the intersections between the bit lines BL and the source lines SL. Each of the memory cells MC has a configuration in which a selection transistor 11 made of an N-channel MOS transistor and a cell transistor 12 made of an N-channel MOS transistor are connected in series. The source of the selection transistor 11 is connected to the corresponding bit line BL (any one of BL1, BL2,... BLm), and the gate electrode is connected to the corresponding word line WL (WL1 or WL2). The source of the selection transistor 11 is connected to the drain of the cell transistor 12. The source of the cell transistor 12 is connected to the corresponding source line SL (SL1 or SL2).

  Each of the cell transistors 12 has an N + type diffusion layer formed in a part of the surface region of the substrate on the side close to the selection transistor 11. In FIG. 1, this N + type diffusion layer is indicated by a broken line. The gate electrode of the cell transistor 12 is not electrically connected to any of them, and is in a floating state in terms of potential.

  In general, the memory cell is divided into a plurality of blocks, and the source lines SL are wired in common in units of blocks.

  2 is a pattern plan view showing a part of the memory cells extracted from the memory cell array in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line AA in FIG.

  In a P-type semiconductor substrate (or a P-well formed on an N-type semiconductor substrate) 21, N + type diffusion layers 22a to 22e are formed so as to be separated from each other and arranged in a line. N + type diffusion layer 22a constitutes the source region of cell transistor 12 in the memory cell. The N + type diffusion layer 22b constitutes the drain region of the cell transistor 12 and the source region of the selection transistor 11 in the memory cell. The N + type diffusion layer 22c forms the drain region of the select transistor 11 in two adjacent memory cells sharing the same bit line. The N + type diffusion layer 22d constitutes the source region of the cell transistor 12 and the drain region of the selection transistor 11 in the memory cell. The N + type diffusion layer 22e constitutes the source region of the cell transistor 12 in the memory cell.

  The N + type diffusion layers 22a and 22e are respectively extended in the horizontal direction in FIG. 2 and become source lines SL1 and SL2 wired in common to a plurality of memory cells.

  On the substrate 21 between the N + type diffusion layers 22a and 22b, a gate electrode 24 formed by patterning a conductive layer, for example, a polycrystalline silicon layer, is formed via a gate insulating film 23. The gate electrode 24 is not electrically connected anywhere and is in a floating state.

  A gate electrode 25 formed using the same conductive layer as the gate electrode 24 is formed on the substrate 21 between the N + type diffusion layers 22b and 22c with a gate insulating film 23 interposed therebetween. The gate electrode 25 extends in the horizontal direction in FIG. 2 and becomes a word line WL1 wired in common to a plurality of memory cells.

  Similarly, a gate electrode 26 formed using the same conductive layer as the gate electrode 24 is formed on the substrate 21 between the N + type diffusion layers 22c and 22d via a gate insulating film 23. Yes. The gate electrode 26 is extended in the horizontal direction in FIG. 2 to become a word line WL2 wired in common to a plurality of memory cells.

  A gate electrode 27 formed using the same conductive layer as the gate electrode 24 is formed on the substrate 21 between the N + type diffusion layers 22d and 22e with a gate insulating film 23 interposed therebetween. . The gate electrode 27 is not electrically connected anywhere and is in a floating state.

  Further, an N + type diffusion layer 28 is formed in a portion in contact with the N + type diffusion layer 22b between the N + type diffusion layers 22a and 22b, that is, in the surface region of the substrate 21 below the gate electrode 24. Similarly, an N + type diffusion layer 28 is formed between the N + type diffusion layers 22d and 22e, that is, in the surface region of the substrate 21 below the gate electrode 27, in a part in contact with the N + type diffusion layer 22d.

  Further, an interlayer insulating film 29 is formed on the entire surface including on the gate electrodes 24 to 27, and a contact hole 30 is formed in the interlayer insulating film 29 so that a part of the N + type diffusion layer 22c is exposed. A wiring layer 31 is formed so as to fill the contact hole 30. The wiring layer 31 becomes a bit line BL extending in a direction intersecting with the extending direction of the gate electrodes 25 and 26.

  Further, as shown in FIG. 3, the dimension L1 in the bit line direction (extending direction of the wiring layer 31) of the channel region portion where the N + type diffusion layer 28 is formed has no N + type diffusion layer 28 formed. The channel region portion is formed to be larger than the dimension L2 in the bit line direction.

  Next, the operation of the nonvolatile semiconductor memory device shown in FIG. 1 will be described with reference to FIGS. FIG. 4 shows an example of voltages applied to the source line SL, word line WL, and bit line BL at the time of data writing (programming), erasing and reading, and FIG. 5 shows memory cells before and after programming. The transition state of the threshold voltage Vth is shown.

  First, the program operation will be described. It should be noted that after the semiconductor chip is manufactured, electrons are previously emitted from the gate electrode of the cell transistor 12, that is, the gate electrodes 24 and 27, and the threshold voltage Vth of the cell transistor 12 has a negative value. To do. This initial state is assumed to be a “1” storage state as shown in FIG.

  During programming, a positive voltage, for example, 4.5 V is applied to the selected bit line BL. 0 V (ground voltage) is applied to the unselected bit line BL. A voltage Von that turns on the selection transistor 11, for example, 2V, is applied to the selected word line WL to which the memory cell to be programmed is connected. 0 V is applied to the unselected word line WL and the source line SL to which the unselected selection transistor 11 is connected.

  As a result, the drain region of the cell transistor 12 of the selected memory cell becomes the voltage 4.5 V applied to the bit line BL. In addition, 0 V of the source line SL is transmitted to the source region of the cell transistor 12. Here, an N + type diffusion layer 28 is formed in a part of the channel region on the selection transistor 11 side of the cell transistor 12, and an n type MOS capacitor is interposed between the N + type diffusion layer 28 and the gate electrode 24 or 27. It is configured. For this reason, when a voltage of 4.5 V is applied to the drain region of the cell transistor 12, the gate potential of the cell transistor 12 rises due to capacitive coupling by the MOS capacitor, and the cell transistor 12 is turned on. As a result, a current flows between the source and drain regions of the cell transistor 12, and hot electrons are generated. Hot electrons generated in this way are injected into the gate electrode (gate electrode 24 or 27) from the edge of the cell transistor 12 on the source region (N + type diffusion layer 22a or 22e) side. Then, the threshold voltage of the cell transistor 12 having a negative value in the initial state shifts in the positive direction. The state after the shift is set to the “0” storage state as shown in FIG.

  That is, by being programmed, the threshold voltage of the cell memory cell 12 shifts in the positive direction. The threshold voltage of the cell transistor 12 in the unselected memory cell 12 that is not programmed remains at the original negative polarity.

  Further, in the surface region of the substrate under the gate electrode of the cell transistor 12, the dimension L1 of the part where the N + type diffusion layer 28 is formed is larger than the dimension L2 of the part where the N + type diffusion layer 28 is not formed. During programming, the capacitive coupling between the drain region and the gate electrode of the cell transistor 12 is increased, the potential of the gate electrode of the cell transistor 12 can be sufficiently increased, and the writing efficiency can be increased.

  Next, the data erasing operation will be described.

  When erasing is performed, a positive high voltage of about 7 V, for example, is applied to the source line SL and the selected word line WL to which the memory cell to be erased is connected. In addition, 0 V is applied to the bit line BL. In this case, the selected word line WL and the source line SL need to be raised at the same time. This is for preventing the breakdown of the gate insulating film of the selection transistor 11 by simultaneously raising the voltage of the channel region and the gate electrode of the selection transistor 11.

  By applying a positive high voltage to the selected word line WL, the selection transistor 11 is sufficiently turned on, and 0 V is output to the drain region of the cell transistor 12. The gate potential of the cell transistor 12 is lowered due to capacitive coupling between the drain region of the cell transistor 12 and the gate electrode. On the other hand, a positive high voltage is applied to the source region of the cell transistor 12 from the source line SL. As a result, electrons are extracted from the gate electrode to the source region (N + type diffusion layer 22a or 22e) of the cell transistor 12 near the edge of the gate electrode of the cell transistor 12, and the threshold voltage of the cell transistor 12 is initially negative. Return to the state. The initial state is performed by extracting electrons from the gate electrode of the cell transistor 12 in this way.

  In this case, as an erase unit, block erase is performed when an erase voltage of 7 V is applied only to one source line SL, and page erase is performed when an erase voltage is applied in parallel to all the source lines SL. . As a result, block erase or page erase can be selected.

  Next, a data read operation will be described.

  At the time of reading, a read voltage is applied to the selected bit line BL to which a memory cell to be read is connected. The value of this read voltage is, for example, about 0.8V. A voltage Von that turns on the selection transistor 11 is applied to the word line WL to which the memory cell to be read is connected. The value of the voltage Von is about 2V, for example. A voltage of 0 V is applied to the unselected bit line BL. Further, 0 V is applied to all the source lines SL.

  When the selection transistor 11 is turned on, a read voltage is transmitted to the drain region of the cell transistor 12 in the selected memory cell. In addition, the voltage of 0 V applied to the source line SL is transmitted to the source region of the cell transistor 12.

  At this time, if the selected memory cell is in the “1” storage state, that is, if the threshold voltage of the cell transistor 12 is a negative value in the initial state, the cell transistor 12 is turned on and the bit line BL is connected via the cell transistor 12. Current flows through On the other hand, if the selected memory cell is in the “0” storage state, that is, programmed, and the threshold voltage of the cell transistor 12 changes to a positive value, the cell transistor 12 is turned off and the cell transistor 12 No current flows through the bit line BL. Then, whether or not current flows through the bit line BL is determined by a sense amplifier (not shown), and data “1” and “0” are detected.

  By the way, in the above memory cell, the potential of the gate electrode floating in potential is raised by capacitive coupling when data is written, so that the coupling state between the N + type diffusion layer 28 and the gate electrode is increased. The amount of writing changes depending on. For this reason, at the time of writing, data is read out immediately after writing to a memory cell that has been written for a certain period of time. If the threshold voltage is not within the predetermined distribution width, the writing operation is performed. It is necessary to repeat the writing operation and the reading operation until they fall within a predetermined distribution width. Such an operation is generally called a write verify operation.

  Also in the case of the first embodiment, a write verify operation may be performed at the time of writing. By performing the write verify operation, it is possible to adjust the threshold distribution of “0” data to fall within a predetermined range after writing, as shown in FIG.

  Thus, in the nonvolatile semiconductor memory device of the first embodiment, data can be erased electrically. Further, since it is not necessary to provide an N-type well independently for each memory cell as in the prior art, the cell area is also relatively small.

(Second Embodiment)
FIG. 6 is an equivalent circuit diagram showing a partial configuration of the memory cell array of the nonvolatile semiconductor memory device according to the second embodiment. Also in this embodiment, as in the case of the first embodiment, a plurality of bit lines, word lines, and source lines are arranged, and a memory cell MC is provided at each intersection of each bit line BL and source line SL. Has been placed. Further, each memory cell MC has a configuration in which a selection transistor 11 made of an N-channel MOS transistor and a cell transistor 12 made of an N-channel MOS transistor are connected in series.

  The source region of the select transistor 11 is connected to the corresponding source line SL (SL1 or SL2), and the gate electrode is connected to the corresponding word line WL (WL1 or WL2). The source region of the cell transistor 12 is connected to the drain region of the selection transistor 11. The drain region of the cell transistor 12 is connected to a corresponding bit line BL (any one of BL1, BL2,... BLm).

  In the cell transistor 12, an N + type diffusion layer is formed in the surface region of the substrate 21 on the side close to the bit line BL, and the gate electrode is not electrically connected to any of them and is in a floating state in potential. Has been. Therefore, the cell transistor 12 is shown as comprising a MOS transistor 12a and an n-type MOS capacitor 12b connected between the gate electrode and drain region of the MOS transistor 12a.

  FIG. 7 is a pattern plan view showing a part of the memory cells extracted from the memory cell array in FIG. 6, and FIG. 8 is a cross-sectional view taken along line BB in FIG.

  In a P-type semiconductor substrate (or a P-well formed on an N-type semiconductor substrate) 21, N + type diffusion layers 22A to 22G are formed so as to be separated from each other and arranged in a line. The N + type diffusion layer 22 </ b> A constitutes the source region of the selection transistor 11. The N + type diffusion layer 22 </ b> B constitutes the drain region of the selection transistor 11 and the source region of the cell transistor 12. The N + type diffusion layer 22C constitutes the drain region of the MOS transistor 12a. The N + type diffusion layer 22D corresponds to one end of the MOS capacitor 12b in two adjacent memory cells sharing the bit line.

  The N + type diffusion layer 22E constitutes the drain region of the MOS transistor 12a. The N + type diffusion layer 22F constitutes the source region of the MOS transistor 12a and the drain region of the selection transistor 11. The N + type diffusion layer 22 </ b> G constitutes the source region of the selection transistor 11.

  The N + type diffusion layers 22A and 22G are extended in the horizontal direction in FIG. 7 to become source lines SL1 and SL2 wired in common to a plurality of memory cells.

  On the substrate 21 between the N + type diffusion layers 22A and 22B, a gate electrode 25 formed by patterning a conductive layer, for example, a polycrystalline silicon layer, is formed via a gate insulating film 23. The gate electrode 25 is extended in the horizontal direction in FIG. 7 to become a word line WL1 wired in common to a plurality of memory cells. Similarly, on the substrate 21 between the N + type diffusion layers 22F and 22G, a gate electrode 26 formed using the same conductive layer as the gate electrode 25 is formed via a gate insulating film 23. Yes. The gate electrode 26 is extended in the horizontal direction in FIG. 7 to become a word line WL2 wired in common to a plurality of memory cells.

  On the substrate 21 between the N + type diffusion layers 22B and 22C, a gate electrode 24A formed using the same conductive layer as the gate electrode 25 is formed via a gate insulating film 23. . On the substrate 21 between the N + type diffusion layers 22C and 22D, a gate electrode 24B formed using the same conductive layer as the gate electrode 25 is formed via a gate insulating film 23. The gate electrodes 24A and 24B are connected to each other to form one gate electrode 24 as shown in FIG. 7, and the planar shape thereof is a U-shape.

  Similarly, a gate electrode 27B formed using the same conductive layer as the gate electrode 25 is formed on the substrate 21 between the N + type diffusion layers 22D and 22E via the gate insulating film 23. Yes. On the substrate 21 between the N + type diffusion layers 22E and 22F, a gate electrode 27A formed using the same conductive layer as the gate electrode 25 is formed via a gate insulating film 23. The gate electrodes 27B and 27A are also connected to each other to form one gate electrode 27 as shown in FIG. 7, and the planar shape thereof is a U-shape.

  Further, an N + type diffusion layer 28 is formed in the surface region of the substrate 21 located between the N + type diffusion layers 22C and 22D and between the N + type diffusion layers 22D and 22E.

  As shown in FIG. 8, the dimension L1 in the bit line direction (extending direction of the wiring layer 31) of the surface region portion of the substrate on which the N + type diffusion layer 28 is formed is a channel where the N + type diffusion layer 28 is not formed. It is formed to be larger than the dimension L2 of the region portion in the bit line direction.

  An interlayer insulating film 29 is formed on the entire surface of the gate electrode. A contact hole 30 is formed in the interlayer insulating film 29 so that a part of the N + type diffusion layer 22D is exposed. A wiring layer 31 is formed so as to be buried. The wiring layer 31 is extended in a direction intersecting with the extending direction of the gate electrodes 25 and 26 of the selection transistor 11 to become the bit line BL.

  Next, the operation of the nonvolatile semiconductor memory device shown in FIG. 6 will be described.

  First, the program operation will be described. After the semiconductor chip is manufactured, electrons are emitted in advance from the gate electrode of the cell transistor 12, that is, the gate electrodes 24 and 27, and the threshold voltage Vth of the MOS transistor 12a has a negative value. To do. This initial state is set to the “1” storage state as shown in FIG.

  During programming, a positive voltage, for example, 4.5 V is applied to the selected bit line BL. 0 V is applied to the non-selected bit line BL. A voltage Von, for example, 2V, for turning on the selection transistor 11 is applied to the selected word line WL to which the memory cell to be programmed is connected. 0 V is applied to the unselected word line WL and the source line SL to which the unselected selection transistor 11 is connected.

  As a result, 0 V of the source line SL is transmitted to the source region of the MOS transistor 12a of the selected memory cell. In addition, one electrode of the MOS capacitor 12b of the selected memory cell, that is, the N + type diffusion layer 28 has a voltage of 4.5 V applied to the bit line BL. The voltage of 4.5 V applied to the bit line BL is transmitted to the drain region (N + type diffusion layer 22C or 22E) of the MOS transistor 12a. Due to capacitive coupling by the MOS capacitor 12b, the gate potential of the MOS transistor 12a rises, and the MOS transistor 12a is turned on. As a result, current flows between the source and drain of the MOS transistor 12a, and hot electrons are generated. Hot electrons generated in this way are injected into the gate electrode (gate electrode 24 or 27) from the edge of the MOS transistor 12a on the source region (N + type diffusion layer 22B or 22F) side. Then, the threshold voltage of the MOS transistor 12a having a negative value in the initial state shifts in the positive direction. After the shift, the “0” storage state is entered as shown in FIG.

  That is, by programming, the threshold voltage of the MOS transistor 12a in the memory cell 12 shifts in the positive polarity direction. The threshold voltage of the MOS transistor 12a in the unselected memory cell 12 that is not programmed remains at the original negative polarity.

  Further, the dimension L1 in the bit line direction of the surface region portion of the substrate where the N + type diffusion layer 28 is formed is larger than the dimension L2 in the bit line direction of the channel region portion where the N + type diffusion layer 28 is not formed. At the time of programming, the capacitive coupling in the MOS capacitor is increased, the gate potential of the MOS transistor 12a can be sufficiently increased, and the writing efficiency can be increased.

  Next, the data erasing operation will be described.

  When erasing is performed, a positive high voltage of about 7 V, for example, is applied to the source line SL and the selected word line WL to which the memory cell to be erased is connected. In addition, 0 V is applied to the bit line BL. Also in this case, the selected word line WL and the source line SL need to be raised at the same time for the same reason as described above.

  By applying 0V to the bit line BL, the gate potential of the MOS transistor 12a is lowered due to capacitive coupling by the MOS capacitor 12b. As a result, electrons are extracted from the gate electrode to the source region (N + type diffusion layer 22B or 22F) near the edge of the gate electrode of the MOS transistor 12a, and the threshold voltage of the MOS transistor 12a is a negative value in the initial state. Return to. The previous initial state is performed by extracting electrons from the gate electrode of the MOS transistor 12a in this way.

  In this case, as an erase unit, block erase is performed when an erase voltage of 7 V is applied only to one source line SL, and page erase is performed when an erase voltage is applied in parallel to all the source lines SL. . As a result, block erase or page erase can be selected.

  Next, a data read operation will be described.

  At the time of reading, a read voltage is applied to the selected bit line BL to which a memory cell to be read is connected. The value of this read voltage is, for example, about 0.8V. A voltage Von that turns on the selection transistor 11 is applied to the word line WL to which the memory cell to be read is connected. The value of the voltage Von is about 2V, for example. A voltage of 0 V is applied to the unselected bit line BL. Further, 0 V is applied to all the source lines SL.

  When the selection transistor 11 is turned on, 0V is transmitted to the source region of the MOS transistor 12a in the selected memory cell. Further, the read voltage applied to the selected bit line BL passes through one electrode of the MOS capacitor 12b in the selected memory cell, that is, the N + type diffusion layer 28 to the drain region of the MOS transistor 12a, that is, the N + type diffusion layer 22C or 22E. It is transmitted.

  At this time, if the selected memory cell is in the “1” storage state, that is, if the threshold voltage of the MOS transistor 12a is a negative value in the initial state, the MOS transistor 12a is turned on, and the selection transistor 11 and the cell transistor 12 are connected in series. Current flows through the bit line BL. On the other hand, if the selected memory cell is in the “0” storage state, that is, if programming is performed and the threshold voltage of the MOS transistor 12a has a positive value, the MOS transistor 12a is turned off, and the cell transistor 12 is turned off. Therefore, no current flows through the bit line BL. Then, whether or not current flows through the bit line BL is determined by a sense amplifier (not shown), and data “1” and “0” are detected.

  Also in the case of the second embodiment, in each memory cell, the potential of the gate electrode floating in potential is raised by capacitive coupling at the time of data writing, so that the coupling by the MOS capacitor 12b is performed. The amount of writing varies depending on the state. Therefore, at the time of writing, the write verify operation as described above may be performed.

  Thus, even in the nonvolatile semiconductor memory device of the second embodiment, data can be erased electrically. Further, since it is not necessary to provide an N-type well independently for each memory cell as in the prior art, the cell area is also relatively small.

  In the first and second embodiments, the case where a voltage of 0 V is applied to the selected bit line at the time of erasing data has been described. This is a positive voltage slightly higher than 0 V, for example, You may make it apply the voltage of 1-2V as shown in FIG. At the time of data erasure, by applying a positive voltage to the selected bit line, electrons in the gate electrode of the cell transistor 12 in FIG. 1 or the MOS transistor 12a in FIG. Shifts to a negative value, the cell transistor 12 or the MOS transistor 12a is turned off because the voltage of the bit line is positive. As a result, current can be prevented from flowing from the source line to the bit line during erasing.

(First Modification of Second Embodiment)
Next, a first modification of the second embodiment will be described.

  FIG. 9 is a pattern plan view showing a part of memory cells extracted from the memory cell array in FIG. 9, parts corresponding to those in the pattern plan view of FIG. 7 are denoted by the same reference numerals, description thereof is omitted, and only parts different from FIG. 7 are described below.

  In FIG. 7, the case where the gate electrodes 24 and 27 of the cell transistor 12 have a U-shaped planar shape has been described. However, in the case of the first modification, the gate electrodes 24 and 27 of the cell transistor 12 are used. Has a square shape. That is, compared with FIG. 7, the N + type diffusion layers 22 </ b> C and 22 </ b> E are omitted, and the region where the N + type diffusion layers 22 </ b> C and 22 </ b> E exist becomes a part of the channel region of the cell transistor 12. An N + type diffusion layer 28 is formed in part of the surface region of the substrate on the bit line side of the cell transistor 12.

  Also in this case, the dimension in the bit line direction of the portion where the N + type diffusion layer 28 is formed in the surface region of the substrate below the gate electrodes 24 and 27 is that of the portion where the N + type diffusion layer 28 is not formed. Greater than dimensions. In other words, the length of the MOS capacitor corresponding to the channel region of the MOS transistor is made longer than that of the MOS transistor, and the capacitive coupling by the MOS capacitor during programming is increased.

  In the nonvolatile semiconductor memory device of the first modification, the same effect as that of the second embodiment can be obtained, and the N + type diffusion layer 22C existing between the MOS transistor and the MOS capacitor can be obtained. , 22E is not formed, so that the cell area can be further reduced.

(Second modification of the second embodiment)
Next, a second modification of the second embodiment will be described.

  In the second embodiment, the case where the selection transistor 11 in each memory cell MC is arranged on the source line side and the cell transistor 12 is arranged on the bit line side has been described. As shown in FIG. Contrary to the second embodiment, that is, the selection transistor 11 in each memory cell MC may be arranged on the bit line side, and the cell transistor 12 may be arranged on the source line side.

  Also in this second modification, the same effect as in the second embodiment can be obtained.

  In the second modification, the source lines are connected in common in the memory cell array without dividing the source line, and the source voltage generation is performed from the end of the memory cell array to the common source line without going through the decoding transistor. A circuit may be connected. The source voltage generation circuit generates source voltages having various values as shown in FIG. 4 at the time of data writing / erasing / reading in the memory cell. The film thickness of the gate insulating film under the gate electrode of the MOS transistor in the source voltage generation circuit is made the same as that of the gate insulating film under the gate electrode of the MOS transistor in the memory cell.

  As described above, when the source voltage generation circuit is connected to the common source line without using the decoding transistor, the following effects can be obtained. That is, a high voltage is applied to the source line at the time of erasing. When a decoding transistor is provided, it is necessary to increase the thickness of the gate oxide film so that the decoding transistor can withstand this high voltage. If the transistor having such a thick gate oxide film is not formed in the logic circuit, it must be formed independently, and a nonvolatile memory device cannot be manufactured by a process compatible with the logic circuit. Without the decoding transistor, it is not necessary to form a transistor having a thick gate oxide film.

  By the way, in the nonvolatile semiconductor memory devices of the above-described embodiments and modifications, the memory cell MC is substantially composed of two MOS transistors, and the gate electrodes of both transistors are the same conductive layer, for example, polycrystalline. The silicon layer can be formed by patterning. Therefore, as shown in the block diagram of FIG. 11, the nonvolatile semiconductor memory device 100 including the memory cell array shown in FIGS. 1, 6 and 10 is integrated on the same semiconductor chip together with the peripheral circuit 200 formed of the logic circuit. The gate electrodes of both transistors in the memory cell MC can be simultaneously formed using the same conductive layer as the gate electrode of the MOS transistor formed in the peripheral circuit 200. The peripheral circuit 200 includes an address decoder circuit for selecting a memory cell in the nonvolatile semiconductor memory device 100, a sense amplifier circuit, a data input / output circuit, and a sequence control for controlling a write / erase / read operation. Circuits are included.

  Next, the memory cells in the memory cell array shown in FIGS. 1, 6 and 10 are divided into output transistors (logic I / O) requiring high breakdown voltage and logic transistors (logic transistors) requiring high speed. The manufacturing process in the case of integration on the same semiconductor chip together with the peripheral circuit having the above is schematically described.

  First, as shown in FIG. 12A, after a plurality of P-type well regions 42 are formed in an N-type semiconductor substrate 41, an element isolation groove is formed in the substrate 41, and an oxide film is formed in the groove. The element isolation region 43 is formed by embedding.

  Next, as shown in FIG. 12B, impurity diffusion is performed in the channel region 44 of the memory cell array and the logic I / O formation planned region of the logic circuit, and then the first oxide film 45 is deposited on the entire surface by a deposition method or the like. Form. The first oxide film 45 becomes a transistor and a gate insulating film of the logic I / O in the memory cell, and its film thickness is set in a range of 5 to 13 nm, for example.

  Thereafter, as shown in FIG. 12C, after the first oxide film 45 on the formation region of the logic transistor requiring high speed is selectively removed, impurity diffusion is performed in the channel region 46 in this region. After that, a second oxide film 47 is formed on the entire surface by a deposition method or the like. The second oxide film 47 serves as a gate insulating film of the logic transistor, and its film thickness is made thinner than that of the first oxide film 45.

  Next, as shown in FIG. 12D, a conductive layer 48 for forming a gate electrode is deposited on the entire surface. For example, a polycrystalline silicon layer is used as the conductive layer 48.

  Subsequently, as shown in FIG. 13A, the conductive layer 48 is patterned and gate processing is performed to form a gate electrode 49. At this time, the gate insulating films of the transistors in the memory cell array and the gate electrode 49 of the logic I / O in the logic circuit are each composed of the first oxide film 45 and have the same film thickness.

  Next, as shown in FIG. 13B, an N-type impurity is introduced into the substrate 41 using the gate electrode 49 as a mask to form source / drain diffusion regions 50 of each transistor. At this time, an N-type impurity is also implanted into the surface of each gate electrode 49 to form an impurity implantation region 51.

  Further, the N + type diffusion layer 28 in the previous MOS capacitor diffuses N type impurities into the MOS capacitor region simultaneously with the impurity diffusion in the channel region 44 in the logic I / O formation planned region of the memory cell array and logic circuit. Alternatively, after processing the gate electrode, N-type impurities are formed by doping the MOS capacitor region through the gate electrode by ion implantation with a high acceleration voltage.

  Thereafter, as shown in FIG. 13C, an interlayer insulating film 52 is deposited, a contact hole leading to the surface of the source / drain diffusion region 50 is opened in the interlayer insulating film 52, and this contact hole is opened. By forming the conductive layer 53 so as to be buried, the terminal is taken out from each source / drain diffusion region 50. Then, a multilayer wiring is formed by stacking the required number of interlayer insulating films 52.

  According to such a method, the memory cell in the nonvolatile semiconductor memory device 100 and the transistor in the peripheral circuit 200 can be manufactured using the same manufacturing process. That is, the process is greatly simplified compared to the case of manufacturing a conventional nonvolatile semiconductor memory device using a transistor having a stacked gate structure, and the manufacturing cost is almost the same as that of a normal MOS type semiconductor integrated circuit device not including a memory cell array. Absent.

  Needless to say, the present invention is not limited to the above-described embodiments and modifications, and various modifications are possible. For example, in the above-described embodiment and modification, the case where both the selection transistor and the cell transistor in the memory cell are configured by N-channel MOS transistors has been described, but this is configured by using P-channel MOS transistors, respectively. It may be.

  The equivalent circuit of the memory cell array when a P-channel MOS transistor is used is the same as that of FIGS. 1, 6 and 10, and an N-channel MOS transistor is simply replaced with a P-channel MOS transistor.

  When P-channel MOS transistors are used as the selection transistor and the cell transistor, the selection transistor and the cell transistor are formed in an N-type well provided in a P-type semiconductor substrate. In this case, the gate electrodes of the selection transistor and the cell transistor are formed using the same conductive layer as in the case of using the N-channel MOS transistor. Further, a P + type diffusion layer is formed in a part of the channel region of the cell transistor.

  When data is programmed in a memory cell using a P-channel MOS transistor, there are two voltage application methods.

  In the first method, 0V is applied to the N-type well and the source line, a voltage such as 0V is applied to the word line to turn on the selection transistor composed of a P-channel MOS transistor, and the negative voltage is applied to the bit line. A positive voltage, for example -5V, is applied.

  As a result, 0 V of the source line is transmitted to the source region of the MOS transistor of the selected memory cell. In addition, a voltage of −5 V applied to the bit line is transmitted to the electrode on the substrate side of the MOS capacitor of the selected memory cell. Then, due to capacitive coupling by the MOS capacitor, the gate potential of the cell transistor drops and the cell transistor is turned on. As a result, a hole current flows between the source and drain of the MOS transistor, thereby generating hot electrons. The hot electrons are injected into the gate electrode at the edge of the source region of the MOS transistor, and the program is executed. Is called.

  In the second method, a positive high voltage is applied to the N-type well and the source line, and a voltage such as 0 V is applied to the word line so that the selection transistor composed of a P-channel MOS transistor is turned on. 0V is applied to the line.

  As a result, the positive high voltage applied to the source line is transmitted to the source region of the MOS transistor of the selected memory cell. The voltage of 0V applied to the bit line is transmitted to the electrode on the substrate side of the MOS capacitor of the selected memory cell. Then, due to capacitive coupling by the MOS capacitor, the gate potential of the cell transistor drops and the cell transistor is turned on. As a result, a hole current flows between the source and drain of the MOS transistor, thereby generating hot electrons. The hot electrons are injected into the gate electrode at the edge of the source region of the MOS transistor, and the program is executed. Is called.

  When data is read, a positive voltage is applied to the N-type well, 0 V is applied to the selected bit line and the selected word line, and N is applied to each of the unselected bit line, the unselected word line, and the source line. The same positive voltage as that applied to the mold well is applied.

  If the selected memory cell is in a write state, the threshold voltage of the MOS transistor of the cell transistor is a positive value, so that the cell transistor is turned on and a current flows through the bit line.

  On the other hand, if the selected memory cell is not in the write state, the threshold voltage of the MOS transistor of the cell transistor is a negative value, so that the cell transistor is turned off and no current flows through the bit line. Then, whether or not current flows through the bit line is determined by the sense amplifier, and data of “0” and “1” is detected.

  FIG. 14 collectively shows voltages at the time of programming and reading when a P-channel transistor is used as the selection transistor and the cell transistor.

1 is an equivalent circuit diagram showing a configuration of a part of a memory cell array of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a pattern plan view showing a part of memory cells extracted from the memory cell array in FIG. 1. Sectional drawing along the AA line in FIG. FIG. 2 is a diagram illustrating an example of voltages applied to each unit during operation of the nonvolatile semiconductor memory device in FIG. 1. FIG. 3 is a diagram showing transition states of threshold values of memory cells before and after programming in the nonvolatile semiconductor memory device of FIG. 1. FIG. 6 is an equivalent circuit diagram showing a configuration of a part of a memory cell array of the nonvolatile semiconductor memory device according to the second embodiment. FIG. 7 is a pattern plan view showing a part of memory cells extracted from the memory cell array in FIG. 6. Sectional drawing along the BB line in FIG. FIG. 10 is a pattern plan view showing a part of memory cells extracted from a memory cell array according to a first modification of the second embodiment. FIG. 10 is an equivalent circuit diagram showing a configuration of a part of a memory cell array of a nonvolatile semiconductor memory device according to a second modification of the second embodiment. The block diagram which shows the semiconductor chip with which the non-volatile semiconductor memory device containing the memory cell array by the 1st, 2nd embodiment and the 1st, 2nd modification of 2nd Embodiment, and the peripheral circuit were integrated. Sectional drawing which shows the manufacturing process of the semiconductor chip shown in FIG. Sectional drawing which shows the manufacturing process following FIG. FIG. 10 is a diagram showing an example of voltages applied to each part during operation of a nonvolatile semiconductor memory device using a P-channel transistor. The element sectional view of the conventional memory cell. FIG. 16 is an equivalent circuit diagram of a memory cell array having the memory cell of FIG. 15.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Selection transistor, 12 ... Cell transistor, 12a ... MOS transistor, 12b ... MOS capacitor, MC ... Memory cell, BL1, BL2, ... BLm ... Bit line, SL1, SL2 ... Source line, WL1, WL2: Word line.

Claims (5)

A selection transistor comprising a MOS transistor having a gate electrode;
A source line connected to one end of the selection transistor;
A word line connected to the gate electrode of the selection transistor and extending in a first direction ;
A first cell transistor having a gate electrode, having one end connected to the other end of the selection transistor, and comprising a MOS transistor having the same polarity as the selection transistor;
A second cell transistor having a gate electrode, one end connected to the other end of the first cell transistor, and a MOS transistor having the same polarity as the selection transistor;
A memory cell array formed on a semiconductor substrate including a bit line connected to the other end of the second cell transistor and extending in a second direction intersecting the first direction ;
A diffusion region having the same conductivity type as the source / drain region of the cell transistor is formed in the channel region of the second cell transistor,
The gate electrodes of the first and second cell transistors are connected to each other and are not electrically connected to each other and are in a potential floating state, and the dimension of the channel region of the second cell transistor in the second direction is the first. A non-volatile semiconductor memory device, wherein the size of the channel region of one cell transistor is larger than the dimension in the second direction . A selection transistor comprising a MOS transistor having a gate electrode;
A bit line connected to one end of the select transistor and extending in a first direction ;
A word line connected to the gate electrode of the select transistor and extending in a second direction intersecting the first direction ;
A first cell transistor having a gate electrode, having one end connected to the other end of the selection transistor, and comprising a MOS transistor having the same polarity as the selection transistor;
A second cell transistor having a gate electrode, one end connected to the other end of the first cell transistor, and a MOS transistor having the same polarity as the selection transistor;
A memory cell array formed on a semiconductor substrate including a source line connected to the other end of the second cell transistor;
A diffusion region having the same conductivity type as the source / drain region of the cell transistor is formed in the channel region of the first cell transistor,
The gate electrodes of the first and second cell transistors are connected to each other and are not electrically connected to each other and are in a potential floating state. The dimension of the channel region of the first cell transistor in the first direction is the first size . A nonvolatile semiconductor memory device, wherein the channel region of a two-cell transistor is larger than the dimension in the first direction . The gate electrodes of the first and second cell transistors, flat surface shape as claimed in claim 1, wherein it is connected to coloration of the U-shaped nonvolatile semiconductor Symbol憶置. The selection transistor and the first and second cell transistors are both N-channel MOS transistors,
When programming the first and second cell transistors, a ground voltage is supplied to the source line, a first positive voltage is supplied to the word line, and the first voltage is supplied to the bit line. The nonvolatile semiconductor memory device according to claim 1, wherein a second positive voltage different from the first voltage is supplied. The selection transistor and the first and second cell transistors are both N-channel MOS transistors,
When performing data erasure of the first and second cell transistors, a positive first voltage is supplied to the source line, a second positive voltage is supplied to the word line, and the bit 3. The nonvolatile semiconductor memory device according to claim 1, wherein a ground voltage is supplied to the line.

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