JP5182513B2 - Image processing apparatus and power saving control method thereof - Google Patents

Description

The present invention relates to an image processing apparatus using an interface having a function of shifting to a power saving state (low power state) when an idle state of a link between devices continues for a predetermined time as an interface between devices, and power saving control thereof. about the mETHODS.

  In an image forming apparatus such as a digital copying machine or a digital multifunction peripheral (MFP: multi-function printer), it is represented by PCI (Peripheral Component Interconnect) as a connection means between devices such as a CPU, an image processing module, and a memory. Parallel interface is used. However, the parallel interface has problems such as racing and skew, and the transfer rate has become insufficient for use in high-speed, high-quality image forming apparatuses. It has been proposed to use a certain PCI Express (registered trademark: hereinafter referred to as PCIe) for an image forming apparatus (see Patent Document 1).

  PCIe is a standard for interconnecting devices via a communication path called a link, and is defined by PCISIG (Peripheral Component Interconnect Special Interest Group).

  In the PCIe standard, ASPM (Active State Power Management) by hardware is defined in addition to the transition to the power saving state by software as a standard regarding power management (power management). In the ASPM, when the ASPM control bit of the configuration register in the PCIe interface circuit is enabled, the transition from the normal state (active state) to the power saving states L0s and L1 is made after a certain idle period. When communication is necessary, the link state is returned from the power saving state to the normal state by hardware. As a result, frequent power saving control can be performed by reducing wasteful power consumption during the idle period of the link without intervention of software, which has a great effect on reducing power consumption.

  However, since recovery time of about several microseconds is required to return from the power saving states L0s and L1 to the normal state, isochronous (Isochronous) such as data writing from the image reading unit to the memory is required. In the necessary data transfer, transition to the power saving state at the start or during the transfer of the image data may lead to the occurrence of an abnormal image. For this reason, there is a problem that ASPM cannot be used in the PCIe link serving as a data transmission path from the image reading unit to the memory, and the power saving function cannot be used.

Japanese Patent Laid-Open No. 2005-210653

  The present invention has been made to solve such a problem, and its object is to make a transition to a power saving state when an idle state of a link between devices continues for a predetermined time as an interface between devices. In an image processing apparatus having an interface having a function, the above-mentioned interface, which is an image data transmission path from the image reading unit, can use a function to shift to a power saving state without affecting the transfer of image data. Is to do.

1st invention of this application is an image processing apparatus provided with the interface which has a function which changes to an electric power saving state, when the idle state of the link between the said devices continues for a predetermined time as an interface between devices, Disabling an image data transfer device that transfers image data generated by the reading unit and a function of transitioning to the power saving state of the interface of the image data transfer device based on an image reading start instruction from the operation unit And means for carrying out the above.
A second invention of the present application is an image processing apparatus provided with an interface having a function of transitioning to a power saving state when an idle state of a link between devices continues for a predetermined time as an interface between devices, An image data transfer device that transfers image data generated by the reading unit, a unit that detects input of the image data read by the image reading unit to the image data transfer device, and an input of image data is detected by the unit And a means for disabling the function of the interface of the image data transfer device to transition to the power saving state.
According to a third aspect of the present invention, there is provided a power saving control method for an image processing apparatus including an interface having a function of transitioning to a power saving state when an idle state of a link between devices continues for a predetermined time as an interface between devices. A step of detecting an image reading start instruction to the image reading device, and transitioning to the power saving state of the interface of the image data transfer device for transferring image data from the image reading device based on the detection And a step of disabling the function to be performed .

  According to the present invention, in an image processing apparatus having an interface having a function of transitioning to a power saving state when an idle state of a link between devices continues for a predetermined time as an interface between devices, With the above-described interface, which is an image data transmission path, it is possible to use the function of transitioning to the above power saving state without affecting the transfer of image data.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a block diagram showing an image processing apparatus according to the first embodiment of the present invention. This image processing apparatus is configured as a part of a digital multi-function peripheral, and includes a CPU 100, an operation panel 101, a scanner 102, ASICs (Application Specific Integrated Circuits) 103, 104, and 106, and a memory 105. .

  The PCIe link 107 is connected between the CPU 100 and the ASIC 103 and between the ASIC 103 and the ASIC 104. The ASIC 106 is an interface module for the operation panel 101.

  The CPU 100 has a function of controlling the entire image processing apparatus. Further, the CPU 100 has a built-in PCIe interface (I / F) circuit 109, and the PCIe interface circuit 109 has a built-in configuration register 109a. Although not shown, the CPU 100 is connected to a ROM that stores a program used during the operation and a RAM that serves as a work area.

  The operation panel 101 includes various operation keys and an LCD panel, and is used for inputting various instructions when the user uses the image forming apparatus. The scanner 102 reads image data of a document set by a user and generates image data.

  The ASIC 104 has a built-in PCIe interface circuit 112, and the PCIe interface circuit 112 has a built-in configuration register 112a. The ASIC 104 performs predetermined image processing on the image data input from the scanner 102 and transfers the image data to the ASIC 103 via the PCIe link 107.

  The ASIC 103 includes a PCIe interface circuit 111. The PCIe interface circuit 111 includes a configuration register 111a. The ASIC 103 performs predetermined image processing on the image data transferred from the ASIC 104 and transfers the image data to the memory 105 via the PCIe link 107.

  In the image processing apparatus having the above configuration, when the user sets a document on the scanner 102 and presses the start button on the operation panel 101, this is detected by the ASIC 106 and transmitted to the CPU 100. Recognizing the instruction to start image reading, the CPU 100 sets the L0s / L1 entry of the ASPM control bit of the link control register in the configuration registers 109a to 112a in the PCIe interface circuits 109 to 112 to “disable”. . This setting follows the support bit of ASPM in the link capability register of each device, that is, the bit of the register indicating whether or not the device supports L0s and L1 of ASPM. As a result, even when an idle cycle of 7 μsec or longer occurs on the PCIe link 107, the image data from the scanner 102 can be normally stored in the memory 105 because the transition to L0s / L1 does not occur.

  Here, the PCIe interface circuit 109 in the CPU 100 and the downstream (downstream) PCIe interface circuit 111 in the ASIC 103 are the root complex in the PCIe hierarchy, and the upstream (upstream) PCIe interface circuit 110 in the ASIC 103. The PCIe interface circuit 112 on the upstream (upstream) side in the ASIC 104 is an endpoint.

  The ASPM control bit of the link control register in the PCIe interface circuit 109 is set by the CPU 100 directly accessing the register. The ASPM control bit of the link control register in the PCIe interface circuit 110 is linked to the link in the configuration register 110a by the CPU 100 using the configuration address register and the configuration data register provided in the PCIe interface circuit 109 as a window. Set by accessing the control register. That is, the configuration register in the endpoint is accessed via the configuration address register and configuration data register in the root complex. In addition, since these access procedures are known, detailed description is abbreviate | omitted.

  Similarly, the control bit of ASPM of the link control register in the PCIe interface circuit 111 and the PCIe interface circuit 112 is stored in the configuration register address register and the configuration data register in the PCIe interface circuit 111 which is the root complex. Access and set as a window.

  As described above, according to the image processing apparatus of the first embodiment of the present invention, the ASPM function is disabled based on the instruction to start image reading. Therefore, the power consumption by ASPM can be reduced without generating an abnormal image. Reduction is possible.

[Second Embodiment]
FIG. 2 is a block diagram showing an image processing apparatus according to the second embodiment of the present invention. In this figure, the same reference numerals as those in FIG.

  The image processing apparatus includes a CPU 100, a scanner 102, ASICs 103 and 200, and a memory 105. The ASIC 200 includes a DMA (Direct Memory Access) controller (hereinafter referred to as DMAC) 201 and an interrupt controller 202 in addition to the PCIe interface circuits 203 and 204 that are a root complex and an endpoint, respectively.

  The DMAC 201 transfers image data transferred from the scanner 102 to the ASIC 104 and transferred from the ASIC 104 to the ASIC 200 via the PCIe link 107 to the memory 105 via the PCIe link 107 and the CPU 100. The interrupt controller 202 sends an interrupt signal to the CPU 100 via the PCIe link 107 when the DMAC 201 completes transfer of a predetermined amount of image data set in advance by the CPU 100.

  That is, in the case of transfer using the DMAC 201, the software of the CPU 100 knows the data transfer amount from the ASIC 104 in advance, and makes settings corresponding to the DMAC 201. Therefore, the completion of the transfer of the DMAC 201 indicates that all the image data sent from the scanner 102 has been transferred to the memory 105.

  When the transfer completion interrupt factor from the DMAC 201 is asserted, the interrupt controller 202 requests the PCIe interface circuit 204 to issue an interrupt. The PCIe interface circuit 204 issues an MSI (Message signaled Interrupt) interrupt to the CPU 100 to notify the software of completion of transfer of image data from the DMAC 201. In view of this, the software performs configuration write access to the configuration registers 109a to 112a in the PCIe interface circuits 109 to 112 as in the first embodiment, and the L0s of the control bits of the ASPM of each link control register The / L1 entry is set to “enable”.

  As described above, according to the second embodiment of the present invention, the ASPM is enabled again based on the completion of the DMA transfer of the image data generated by the scanner 102 in the ASIC 200, thereby excluding the time of image data transfer. It becomes possible to reduce power consumption by ASPM in all periods.

[Third Embodiment]
FIG. 3 is a block diagram showing an image processing apparatus according to the third embodiment of the present invention. In this figure, the same reference numerals as those in FIG.

  The image processing apparatus includes a CPU 100, a scanner 102, ASICs 103 and 300, and a memory 105. The ASIC 300 includes a timer 301 and an interrupt controller 302 in addition to the PCIe interface circuits 303 and 304 that are a root complex and an endpoint, respectively.

  The timer 301 counts a predetermined reference clock, and when image data is input to the PCIe interface circuit 303, an image data detection signal having a line period or a frame period of the image data generated by the circuit is used. Reset. Further, when a predetermined time is counted (time up), a time up signal is sent to the interrupt controller 302. When receiving the time-up signal from the timer 301, the interrupt controller 302 sends an interrupt signal to the CPU 100 via the PCIe link 107, similarly to the interrupt controller 202 of FIG. 2 (second embodiment).

  Upon receiving this interrupt signal, the CPU 100 performs configuration write access to the configuration registers 109a to 112a in the PCIe interface circuits 109 to 112, and controls the ASPM of each link control register, as in the second embodiment. Set the L0s / L1 entry in the bit to “enable”. Thus, ASPM can be set to “enable” after the transfer of the image data from the scanner 102 is completed.

  In the third embodiment of the present invention, the ASIC 300 is configured to transfer the image data from the scanner 102 by directly specifying the address of the memory 105 without mounting the DMAC in the ASIC 300. I can't know when to finish. Therefore, a timer 301 is provided in the ASIC 300, the input of image data from the ASIC 104 is monitored, it is determined that the transfer has been completed when there is no input for a certain period, and an interrupt signal is sent to the CPU 100. Since the ASPM is set to “enable” based on the interrupt, even when the ASIC 300 has no way of knowing the end of the image data transfer, it knows the timing when the ASPM should be “enabled” again. Can be executed.

[Fourth Embodiment]
FIG. 4 is a block diagram showing an image processing apparatus according to the fourth embodiment of the present invention. In this figure, the same reference numerals as those in FIG.

  The image processing apparatus includes a CPU 100, a scanner 102, ASICs 401 and 402, and a memory 105. The ASIC 401 includes a scanner input interface circuit 403 and a PCIe interface circuit 404 as an end point. The ASIC 402 includes a timer 407 and a register access circuit 408 in addition to the PCIe interface circuits 405 and 406, which are a root complex and an endpoint, respectively.

  When the image data sent from the scanner 102 is input, the scanner input interface circuit 403 sends an image data detection signal to the timer 407 and the register access circuit 408 in the line cycle or frame cycle. The timer 407 counts the reference clock and is reset by the image data detection signal. When a predetermined time is counted (time up), a time up signal is sent to the register access circuit 408.

  The register access circuit 408 can access the configuration registers 405 a and 406 a in the PCIe interface circuits 405 and 406 in the ASIC 402. In addition, the configuration register 404a in the PCIe interface circuit 404 serving as an endpoint can be accessed via the configuration address register and the configuration data register in the PCIe interface circuit 405 serving as the root complex. However, since the ASIC 402 is an endpoint device for the CPU 100, the register access circuit 408 in the ASIC 402 cannot access the configuration register 109a in the PCIe interface circuit 109 that is the root complex.

  In the image processing apparatus of the present embodiment having the above configuration, the scanner interface circuit 403 sends an image data detection signal to the timer 407 and the register access circuit 408 when the image data generated by the scanner 102 is input.

  Upon receiving the image data detection signal, the register access circuit 408 performs configuration write access to the configuration register 406a in the PCIe interface circuit 406, and “disables” the entry of L0s of Tx (the link from the ASIC 402 to the CPU 100). Set to. In addition, the configuration register 405a in the PCIe interface circuit 405 that is the root complex is used as a window, the configuration register 404a in the PCIe interface circuit 404 that is the endpoint is accessed for configuration write, and Tx (link from the ASIC 401 to the 402). ) Of L0s is set to “disable”.

  Here, L0s is one of the power saving states defined by ASPM, and “enable / disable” can be set for each direction (only on the transmission side) as shown in FIG. Since Rx (in the case of FIG. 4, the link from the ASIC 402 to 401 and the link from the CPU 100 to the ASIC 402) is opposite to the image data transfer direction, the entry of L0s may remain “enabled”. This operation is premised on the case where the device supports only L0s and does not support L1, or the case where L1 is disabled. This is because, when both L0S and L1 are enabled, after a lapse of 7 μsec, a transition is made to L1, which is a deeper power saving state. The situation where L1 must be disabled is that it takes a very long time to recover (device dependent), and even if the enable / disable is controlled by the register access circuit, the transfer of image data will be hindered. Cases can be considered.

  As a result, the data path from the scanner 102 to the memory 105 does not enter the power saving state (L0s) and is always in the active state (L0), so that the image data is transferred without delay. At this time, since the ASPM remains “enabled” in the data path from the CPU 100 to the ASIC 401, if there is no packet to be transferred, the data path transits to L0s after a prescribed idle cycle.

  When the image data is input from the scanner 102 to the scanner input interface 403 for a certain period and, as a result, when the image data detection signal is not input to the timer 407 for a certain period, the timer 407 sends a time-up signal to the register access circuit 408. Upon receiving the time-up signal, the register access circuit 408 accesses the configuration register 406a in the PCIe interface circuit 406 and sets the L0s entry of Tx to “enable”. Further, the configuration register 404a in the PCIe interface circuit 404 serving as the endpoint is accessed via the configuration address register and configuration data register in the PCIe interface circuit 405 serving as the root complex, and the entry of L0s of Tx is set to “ Set to “Enable”.

  As a result, the L0s entries of the bidirectional paths of all the PCIe links 107 are “enabled”, so that the power saving state is entered when idling. Here, the time-up time of the timer 407 can be set from the software of the CPU 100, and an optimal value (minimum value) according to the system is set based on factors such as the page interval of the document set on the scanner 102. Thus, the period of the power saving state can be maximized. Note that the “disable” of the L0s entry is merely “disabled” temporarily so as not to disturb the transfer that requires isochronism, and normal data that does not require isochronism. In transfer, it is used with “enable”, and transition to the normal state (L0) and return to L0s are performed as necessary.

  As described above, according to the fourth embodiment of the present invention, the register access circuit 408 is provided in the ASIC 402, and “disable” of the ASPM is set without intervention of the CPU 100. Can do. For this reason, the power saving state can be maintained until immediately before the image data is input to the ASIC 401. Further, as soon as the transfer of the image data is completed, it is possible to immediately transition to the power saving state. That is, it is possible to realize power saving control for a very short time that cannot be realized when the CPU 100 is interposed. Further, by setting the period until ASPM is “enabled” again to an optimum period according to the system, the power saving effect by ASPM can be maximized.

[Fifth Embodiment]
FIG. 6 is a block diagram showing an ASIC according to the fifth embodiment of the present invention. This ASIC can be used for, for example, the ASICs 103 and 104 in the image processing apparatus of FIG.

  The ASIC 601 includes a PCIe interface circuit 602, a clock generator 603, and functional modules 604a to 604c. External devices 605 and 606 are connected to the function modules 604b and 604c, respectively.

  The PCIe interface circuit 602 includes a configuration register 602a and an LTSSM register 602b. The LTSSM register 602b is a register indicating the state (state) of the LTSSM. LTSSM is defined in the PCIe standard as indicating the link state of PCIe. The state of the LTSSM is expressed by a state machine state (L0, L0s, L1, L2, etc.) called LTSSM.

  The clock generator 603 has two AND circuits 603a and 603b to which a clock supplied from an SSCG (spread spectrum generator) 607 outside the ASIC 601 and an output signal (status signal) of the LTSSM register 602b are input. The output is supplied as a clock to the function modules 604b and 604c, respectively. Therefore, the function modules 604b and 604c receive / stop the clock according to the state of the LTSSM of PCIe. On the other hand, the clock supplied from the SSCG 607 is supplied to the functional module 604a as it is.

  As in the clock generator 603, two AND circuits 609 and 610 to which the clock supplied from the SSCG 607 and the output of the LTSSM register 602b are input are provided outside the ASIC 601. , Supplied to external devices 605 and 606. Accordingly, the external devices 605 and 606 also receive / stop the clock according to the state of the LTSSM of PCIe, similarly to the function modules 604b and 604c connected thereto.

  Among the states defined by the LTSSM, L0s, L1, and L2 are low power consumption (power saving) states, and a signal indicating that these states are output from the LTSSM register 602b to the AND circuits 603a and 603b, and the SSCG 607 By masking the clock from, the clock supply to a predetermined functional module in the ASIC 601 can be stopped according to the state of the PCIe link. Thereby, the power consumption of ASICA 601 can be reduced. As described above, PCIe defines an automatic transition to a power-saving state called ASPM, which does not involve a CPU and is performed automatically by hardware, so that a dynamic clock can be used without complicated control by software. Gating is possible, and frequent power saving control in the ASIC 610 can be realized.

  Further, by outputting the output signal (status signal) of the LTSSM register 602b to the outside of the ASIC 601 and masking the clock on the substrate, the supply of the clock to the external devices 605 and 606 on the substrate is stopped, thereby the ASIC 601. In addition, power consumption can be reduced at the board level.

[Sixth Embodiment]
FIG. 7 is a block diagram showing a semiconductor device according to the sixth embodiment of the present invention. This semiconductor device can be used for, for example, the ASIC 103 and the CPU 100 in the image processing apparatus of FIG.

  This semiconductor device has a semiconductor integrated circuit 701 and a semiconductor integrated circuit 702 connected by a PCIe link 704. A memory 703 is connected to the semiconductor integrated circuit 701.

  The semiconductor integrated circuit 701 includes a CPU core 701a and a PCIe interface circuit 701b that is a root complex. The semiconductor integrated circuit 702 is an ASIC and includes an arbiter 705, functional modules 706 to 709 connected to the arbiter 705, and a PCIe interface circuit 710 as an end point. A PCIe interface circuit 701 b in the semiconductor integrated circuit 701 and a PCIe interface circuit 710 in the semiconductor integrated circuit 702 are connected by a PCIe link 704.

  Also, the semiconductor integrated circuit 702 supplies power to the power domains A, B, and C in the semiconductor integrated circuit 702 based on the status signal 712 from the LTSSM register 710a built in the PCIe interface circuit 710 (power on / off). Is provided with a power control unit 711 capable of individually controlling the power supply. That is, the power supply control unit 711 has the function modules 706 and 707 included in the power supply domain A, the function modules 707 and 708 included in the power supply domain B, and the PCIe interface circuit 710 and the power supply control unit 711 included in the power supply domain C. In the power domain, it is possible to control on / off individually for each power domain.

  Reduction of power consumption by clock gating as in the fifth embodiment (FIG. 6) does not suppress power consumption due to leakage current. In this embodiment, the leakage current in the chip can be reduced by inputting the status signal 712 indicating the state of the LTSSM to the power supply control unit 711 and using it for power supply control. In particular, when ASPM is enabled, PCIe link idle is detected and the transition is automatically performed by hardware, so the power consumption can be reduced frequently without the software being aware of it.

  As described above, in PCIe, the time required for restoration differs depending on the state of LTSSM. That is, it takes a longer time to recover from the deep energy saving state than to recover from the shallow energy saving state. In this embodiment, the power domains are divided into modules that are problematic if time is required for recovery, modules that do not have problems even if time is required, and modules that cannot be turned off, and are supplied to each power domain for each LTSSM state. (For example, when LTSSM = L0s, the power supply of “power supply domain A” is turned off, and when LTSSM = L1, the power supply of “power supply domain A” and “power supply domain B” is turned off, etc.) Optimal power control can be performed without affecting the power.

[Seventh Embodiment]
FIG. 8 is a block diagram showing a semiconductor device according to the seventh embodiment of the present invention. This semiconductor device includes a semiconductor integrated circuit 801 and a semiconductor integrated circuit 802 connected by a PCIe link 804. A memory 803 is connected to the semiconductor integrated circuit 801, and the semiconductor integrated circuit 802 is connected to a network 805.

  The semiconductor integrated circuit 801 is composed of SoC (System on Chip), an arbiter 806, a CPU core 807, a memory controller 808, and functional modules 809 to 810 that are connected to the arbiter 806, and a PCIe interface circuit that is a root complex. 811 and a power supply capable of individually controlling power supply (power on / off) to the power domains A and B in the semiconductor integrated circuit 801 based on the status signal 813 from the LTSSM register 811a built in the PCIe interface circuit 811 A control unit 812 is provided.

  That is, the power supply control unit 812 has the arbiter 806, CPU core 807, memory controller 808, and functional modules 809 to 810 included in the power supply domain A, and the PCIe interface circuit 811 and power supply control unit 812 included in the power supply domain B. In each power domain, on / off control can be individually performed for each power domain.

  The semiconductor integrated circuit 802 includes an arbiter 802a, a PCIe interface circuit 802b, a USB interface circuit 802c, and an Ethernet (registered trademark) interface circuit 802d, which are endpoints connected to the arbiter 802a. The PCIe interface circuit 802 b is connected to the PCIe interface circuit 811 in the semiconductor integrated circuit 801 by the PCIe link 804, and the Ethernet (registered trademark) interface circuit 802 d is connected to the LAN 805.

  When this semiconductor device is mounted on the image forming apparatus, when the image forming apparatus transitions to the low power consumption state, the CPU core 807 in the semiconductor integrated circuit 801 accesses the PCIe interface circuit 811 and connects the PCIe link 804 to the L1. Transition to a state. In parallel, the CPU core 807 saves the system setting information in the memory 803 and prepares for transition to power off (STR: Suspend to RAM).

  When the CPU core 807 is ready to be powered off, the power of the power domain A is turned off. At this time, power is still supplied to the memory 803 and the power domain B in the semiconductor integrated circuit 801.

  The semiconductor integrated circuit 802 monitors a return factor, detects a request from the host connected to the Ethernet (registered trademark) interface circuit 804d, the USB interface circuit 802c, and the like to the image forming apparatus, and detects the PCIe interface circuit. 802 b issues a PME (Power Management Event) message to the semiconductor integrated circuit 801 via the PCIe link 804.

  The PCIe link 804 between the semiconductor integrated circuit 801 and the semiconductor integrated circuit 802 which is the opposite device transitions to L0 which is an active state. The power control unit 812 restarts the supply of power to the power domain A using the transition to L0 as a trigger. The CPU core 807 takes out the system setting information saved in the memory 803 and returns to the state before the power is turned off.

  In the seventh embodiment of the present invention, since recovery from energy saving is performed by hardware, the power of the CPU core 807 can be turned off, so that the power can be significantly reduced. In addition, since the software is not involved in power control, it can focus on returning to the state before the power is turned off, so that the system can start up quickly. In other words, since the LTSSM state information is used without intervention of software for returning from the power-off state, the CPU core itself can also be turned off in a configuration incorporating the CPU core. Furthermore, since no software is involved in the power recovery, the time required for the recovery is short, and the power consumption can be reduced frequently without affecting the operation of the device.

[Eighth Embodiment]
FIG. 9 is a block diagram showing a semiconductor device according to an eighth embodiment of the present invention. In this figure, the same reference numerals as those in FIG. 8 are assigned to the same or corresponding parts as those in FIG. 8 (seventh embodiment).

  In the semiconductor device of this embodiment, the functional module 814 in the semiconductor device 801 is the power domain C, the power controller 812 is the power domain D, and the beacon detector 815 is the power domain E. A personal computer (hereinafter, PC) 816 is connected to the USB interface circuit 802c in the semiconductor device 802.

  That is, the function module 814 related to a request (print output or the like) from the PC 815 is made independent as the power domain C, and the beacon detector 815 is made independent as the power domain E in the PCIe interface portion.

  In the semiconductor device of this embodiment, when there is no request from the PC 816 for a certain period of time, or when the request on the PC 816 side ends and the driver in the PC 816 determines that the PCIe link 804 may transition to the energy saving state. The LTSSM in the PCIe interface circuit 802b is changed to L2.

  When the power supply control unit 812 disposed in the power supply domain D to which power is always supplied detects the transition of the PCIe link 804 to L2, the power supply control unit 812 stops supplying power to the power supply domain B and the power supply domain C. At this time, power is supplied to the power domain A scheduled to be used for other functions and the power domain E having the beacon detector 815 that detects a beacon from the semiconductor integrated circuit 802.

  When a request is generated from the PC 816, the semiconductor integrated circuit 802 transmits a beacon to the semiconductor integrated circuit 801. The beacon detection unit 815 notifies the power supply control unit 812 that a beacon has been detected, and the power supply control unit 812 resumes power supply to the power supply domain C and the power supply domain B. The PCIe interface circuit 811 to which the power is supplied performs link training, and makes the PCIe link 804 transition to the active state L0.

  With such a configuration, for example, power is supplied to the necessary related circuits only at the time of print output, and power is not supplied otherwise, so that power consumption of the image forming apparatus can be effectively reduced.

[Ninth Embodiment]
FIG. 10 is a block diagram showing a semiconductor device according to the ninth embodiment of the present invention. This semiconductor device has a semiconductor integrated circuit 901 and a semiconductor integrated circuit 902 connected by a PCIe link 903.

  The semiconductor integrated circuit 901 includes a register bus 904, a PCIe interface circuit 905 that is an end point, a power supply control unit 906, functional modules 907 to 910, and AND circuits 911 to 914. The semiconductor integrated circuit 902 includes a CPU core 902a and a PCIe interface circuit 902b that is a root complex. A PCIe interface circuit 905 in the semiconductor integrated circuit 901 and a PCIe interface circuit 902 b in the semiconductor integrated circuit 902 are connected by a PCIe link 903.

  The power supply control unit 906 sends a control signal to one input of each of the AND circuits 911 to 914 in response to the status signal 915 output from the LTSSM register 905a in the PCIe interface circuit 905. The outputs of the functional modules 907 to 910 are supplied to the other inputs of the AND circuits 911 to 914, respectively. The register bus 904 is connected to the outputs of the AND circuits 911 to 914 and the PCIe interface circuit 905.

  11 and 12 are timing charts for explaining the operation of the semiconductor device of this embodiment. Here, OCP (Open Core Protocol) exchange is shown as an example of a general protocol for exchanging requests.

  As shown in FIG. 11, if the slave can receive a request command (MCmd) issued by the master, a command reception signal (SCmdAccept) is asserted. In other words, the transfer is established when the signal indicating the request from the master and the request reception signal of the target are both valid. In FIG. 11, the transfer is established at the timing t1.

  On the other hand, as shown in FIG. 12, there is usually no cause for waiting for a request in register access, so the command reception signal (SCmdAccept) is asserted for the purpose of eliminating redundant cycles, that is, the target request reception signal is In many cases, it is mounted in a state where it is always enabled. In this case, transfer is established at the timing t1.

  However, if the function module with a register interface is powered down (or clock gated), the command reception signal (SCmdAccept) remains asserted even though the function module cannot respond to register access. (The output is fixed by a retention flip-flop or a normal flip-flop in clock gating). In other words, if the request acceptance signal is valid when the target functional module is powered off, the master recognizes that the request has been accepted even though the request has not actually been accepted. End up. As a result, inconsistency in control is caused such that the desired setting is not made at the time of register write, and a timeout error occurs while waiting for read data at the time of register read.

  Therefore, in the present embodiment, when the command reception signal (SCmdAccept) of the functional modules 907 to 910 is fixed to the asserted state, the signal output from the power control unit 906 according to the status signal 915 indicating the state of the LTSSM. Is supplied to the AND gates 911 to 914 to mask the command reception signal (SCmdAccept) output from the functional modules 907 to 910, so that no power is supplied (or no clock is supplied). The function module can now be powered off without causing inconsistencies when register writes to the domain or hangups due to read data waits during register read access. In other words, by masking the request acceptance signal with the power supply control signal, it is possible to prevent inconsistencies and errors in control during register access to the functional module in the energy saving state.

1 is a block diagram illustrating an image processing apparatus according to a first embodiment of the present invention. It is a block diagram which shows the image processing apparatus of the 2nd Embodiment of this invention. It is a block diagram which shows the image processing apparatus of the 3rd Embodiment of this invention. It is a block diagram which shows the image processing apparatus of the 4th Embodiment of this invention. It is a figure for demonstrating that the setting of the entry of L0s is possible only to one direction. It is a block diagram which shows ASIC of the 5th Embodiment of this invention. It is a block diagram which shows the semiconductor device of the 6th Embodiment of this invention. It is a block diagram which shows the semiconductor device of the 7th Embodiment of this invention. It is a block diagram which shows the semiconductor device of the 8th Embodiment of this invention. It is a block diagram which shows the semiconductor device of the 9th Embodiment of this invention. It is a timing diagram for demonstrating operation | movement of the semiconductor device of the 9th Embodiment of this invention. It is a timing diagram for demonstrating operation | movement of the semiconductor device of the 9th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... CPU, 101 ... Operation panel, 102 ... Scanner, 103,104,106,200,300,401,402,601 ... ASIC, 107 ... PCIe link, 109-112, 203, 204, 303, 304, 404 to 406, 602, 710... PCIe interface circuit, 109a to 112a, 203a, 204a, 303a, 304a, 404a to 406a, 602a... Configuration register, 201. DMAC, 202, 302 ... interrupt controller, 301,407 ... timer, 408 ... register access circuit, 602b, 710a, 811a, 905a ... LTSSM register, 603a, 603b, 609, 610 ... AND circuit, 702, 801 01 ... semiconductor integrated circuit, 711,812,906 ... power supply control unit, the status signal 712,813,915 ··· LTSSM, 807 ··· CPU core.

Claims (8)

As an interface between devices, an image processing apparatus comprising an interface having a function of transitioning to a power saving state when an idle state of a link between the devices continues for a predetermined time,
An image data transfer device for transferring image data generated by the image reading unit;
An image processing apparatus comprising: means for disabling a function of transitioning to the power saving state of the interface of the image data transfer device based on an image reading start instruction from an operation unit. The image processing apparatus according to claim 1.
Means for counting the transfer amount of the image data transfer device;
An image processing apparatus comprising: means for enabling a function of transitioning to the power saving state when the count value of the means reaches a predetermined value. The image processing apparatus according to claim 1.
Means for detecting input of the image data read by the image reading unit to the image data transfer device;
An image processing apparatus comprising: a means for enabling a function of transitioning to the power saving state when the input of the image data is not detected by the means for a predetermined period. As an interface between devices, an image processing apparatus comprising an interface having a function of transitioning to a power saving state when an idle state of a link between the devices continues for a predetermined time,
An image data transfer device for transferring image data generated by the image reading unit;
Means for detecting input of the image data read by the image reading unit to the image data transfer device;
An image processing apparatus comprising: means for disabling a function of transitioning to the power saving state of the interface of the image data transfer device when input of image data is detected by the means. The image processing apparatus according to claim 4.
An image processing apparatus comprising: means for enabling a function of transitioning to the power saving state when the input of the image data is not detected for a predetermined period by the detecting means. In the image processing device according to any one of claims 1 to 5,
The interface includes a register to which data for setting enable / disable of the function is written, and the means for enabling or disabling the unit accesses the register to write the data. A featured image processing apparatus. The image processing apparatus according to any one of claims 1 to 6,
The image processing apparatus according to claim 1, wherein the interface conforms to PCI Express. A power saving control method for an image processing apparatus having an interface having a function of transitioning to a power saving state when an idle state of a link between devices continues for a predetermined time as an interface between devices,
Detecting an image reading start instruction to the image reading device;
And a step of disabling the function of the interface of the image data transfer device for transferring image data from the image reading device based on the detection to transition to the power saving state. Power saving control method .

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